Datasheet MC74HCT14AN, MC74HCT14AD, MC74HCT14AFL1, MC74HCT14AFL2, MC74HCT14AFR1 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 7

1 Publication Order Number:

MC74HCT14A/D

MC74HCT14A

Hex Schmitt-Trigger
Inverter with LSTTL
Compatible Inputs

High–Performance Silicon–Gate CMOS

The MC74HCT14A may be used as a level converter for interfacing

TTL or NMOS outputs to high–speed CMOS inputs.

The HCT14A is identical in pinout to the LS14.

The HCT14A is useful to “square up” slow input rise and fall times.
Due to the hysteresis voltage of the Schmitt trigger, the HCT14A finds
applications in noisy environments.

• Output Drive Capability: 10 LSTTL Loads

• TTL/NMOS–Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1.0 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 72 FETs or 18 Equivalent Gates

LOGIC DIAGRAM

PIN 14 = V

CC

PIN 7 = GND

Y = A

A1

1

2

Y1

A2

3

4

Y2

A3

5

6

Y3

A4

9

8

Y4

A5

11

10

Y5

A6

13

12

Y6

FUNCTION TABLE

Input

A

L
H

Output

Y

H
L

Device Package Shipping

ORDERING INFORMATION

MC74HCT14AN PDIP–14 2000 / Box
MC74HCT14AD SOIC–14

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55 / Rail

MC74HCT14ADR2 SOIC–14 2500 / Reel

MARKING

DIAGRAMS

A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

1

14

PDIP–14
N SUFFIX
CASE 646

MC74HCT14AN

AWLYYWW

SOIC–14
D SUFFIX

CASE 751A

1

14

HCT14A

AWLYWW

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

Y5

A5

Y6

A6

V

CC

Y4

A4

Y2

A2

Y1

A1

GND

Y3

A3

MC74HCT14A

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2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

P

D

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

750
500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

ÎÎÎ

Î

260

Î

Î

_

C

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

4.5

ÎÎ

5.5

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

ÎÎ

+ 125

_

C

tr, t

f

Input Rise and Fall Time (Figure 1)

—

ÎÎ

*

ns

*No Limit when Vin [ 50% VCC, ICC > 1 mA.

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Temperature Limit

ÎÎÎООООООÎООООООÎÎ

Î

V

ÎÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

v

85_C

ÎÎÎ

Î

v

125_C

Symbol

Parameter

Test Conditions

CC

Volts

Min

Max

Min

Max

Min

Max

Unit

ÎÎ

Î

VT+ max

ОООООО

Î

Maximum Positive–Going
Input Threshold Voltage

ОООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

Î

Î

4.5

5.5

ÎÎÎ

Î

1.9

2.1

ÎÎÎ

Î

1.9

2.1

ÎÎÎ

Î

1.9

2.1

V

ÎÎ

Î

VT+ min

ОООООО

Î

Minimum Positive–Going
Input Threshold Voltage

ОООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

Î

Î

4.5

5.5

Î

Î

1.2

1.4

ÎÎÎ

Î

1.2

1.4

ÎÎÎ

Î

1.2

1.4

Î

Î

V

VT– max

Maximum Positive–Going
Input Threshold Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

4.5

5.5

1.2

1.4

1.2

1.4

1.2

1.4

ÎÎ

Î

VT– min

ОООООО

Î

Minimum Positive–Going
Input Threshold Voltage

ОООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

Î

Î

4.5

5.5

Î

Î

0.5

0.6

ÎÎÎ

Î

0.5

0.6

ÎÎÎ

Î

0.5

0.6

Î

Î

ÎÎ

Î

VH max

ОООООО

Î

Maximum Hysteresis
Voltage

ОООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

Î

Î

4.5

5.5

ÎÎÎ

Î

1.4

1.5

ÎÎÎ

Î

1.4

1.5

ÎÎÎ

Î

1.4

1.5

VH min

Minimum Hysteresis
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

4.5

5.5

0.4

0.4

0.4

0.4

0.4
0 4

ÎÎ

Î

V

OH

ОООООО

Î

Minimum High–Level
Output Voltage

ОООООО

Î

Vin < VT–min
|I

out

| v 20 µA

Î

Î

4.5

5.5

Î

Î

4.4

5.4

ÎÎÎ

Î

4.4

5.4

ÎÎÎ

Î

4.4

5.4

Î

Î

V

Vin < VT–min
|I

out

| v 4.0 mA

4.5

3.98

3.84

3.7

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

(continued)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HCT14A

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3

DC CHARACTERISTICS (Voltages Referenced to GND) – continued

Temperature Limit

ÎÎÎОООООÎОООООООÎÎ

Î

V

ÎÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

v

85_C

ÎÎÎ

Î

v

125_C

Symbol

Parameter

Test Conditions

V

CC

Volts

Min

Max

Min

Max

Min

Max

Unit

V

OL

Maximum Low–Level
Output Voltage

Vin ≥ VT+max
|I

out

| v 20 µA

4.5

5.5

0.1

0.1

0.1

0.1

0.1

0.1

V

ÎÎÎОООООÎООООООО

Î

Vin ≥ VT+max
|I

out

| v 4.0 mA

Î

Î

4.5

ÎÎÎ

Î

0.26

ÎÎÎ

Î

0.33

ÎÎÎ

Î

0.4

ÎÎ

Î

I

in

ООООО

Î

Maximum Input
Leakage Current

ООООООО

Î

Vin = VCC or GND

Î

Î

5.5

ÎÎÎ

Î

± 0.1

ÎÎÎ

Î

± 1.0

ÎÎÎ

Î

± 1.0

µA

ÎÎ

Î

I

CC

ООООО

Î

Maximum Quiescent
Supply Current
(per package)

ООООООО

Î

Vin = VCC or GND
I

out

= 0 µA

Î

Î

5.5

ÎÎÎ

Î

1.0

ÎÎÎ

Î

10

ÎÎÎ

Î

40

µA

ÎÎÎОООООÎОООООООÎÎÎÎÎÎÎÎ

Î

≥ – 55_C

ÎÎÎ

Î

25_C to

125_C

Î

Î

ÎÎ

Î

∆I

CC

ООООО

Î

Additional Quiescent
Supply Current

ООООООО

Î

Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
l

out

= 0 µA

Î

Î

5.5

ÎÎÎÎÎ

Î

2.9

ÎÎÎ

Î

2.4

Î

Î

mA

AC CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎООООООÎОООООООÎÎÎОООООООООО

Î

Guaranteed Limit

ÎÎÎООООООÎОООООООÎÎÎÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

v

85_C

ÎÎÎ

Î

v

125_C

Symbol

Parameter

Test Conditions

Min

Max

Min

Max

Min

Max

Unit

ÎÎ

Î

ÎÎ

Î

t

PLH

,

t

PHL

ОООООО

Î

ОООООО

Î

Maximum Propagation
Delay, Input A to Output Y
(L to H)

ООООООО

Î

ООООООО

Î

VCC = 5.0 V ± 10%
CL = 50 pF, Input tr = tf = 6.0 ns

Î

Î

Î

Î

Fig.

1 & 2

Î

Î

Î

Î

32

Î

Î

Î

Î

Î

Î

Î

Î

40

Î

Î

Î

Î

Î

Î

Î

Î

48

ns

ÎÎ

Î

ÎÎ

Î

t

TLH

,

t

THL

ОООООО

Î

ОООООО

Î

Maximum Output
Transition Time.
Any Output

ООООООО

Î

ООООООО

Î

VCC = 5.0 V ± 10%
CL = 50 pF, Input tr = tf = 6.0 ns

Î

Î

Î

Î

Fig.

1 & 2

Î

Î

Î

Î

15

Î

Î

Î

Î

Î

Î

Î

Î

19

Î

Î

Î

Î

Î

Î

Î

Î

22

ns

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Inverter)*

32

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

Figure 1. Switching Waveforms Figure 2. Test Circuit

INPUT A

OUTPUT Y

t

f

t

r

3 V
GND

t

PHL

t

PLH

t

TLH

t

THL

2.7 V

1.3 V

0.3 V

90%

1.3 V
10%

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P ACKAGE DIMENSIONS

PDIP–14

N SUFFIX

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

4. ROUNDED CORNERS OPTIONAL.

17

14 8

B

A

F

HG D

K

C

N

L

J

M

SEATING
PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78

G 0.100 BSC 2.54 BSC

H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC

M 0 10 0 10

N 0.015 0.039 0.39 1.01

____

SOIC–14

D SUFFIX

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

G

P

7 PL

14 8

71

M

0.25 (0.010) B

M

S

B

M

0.25 (0.010) A

S

T

–T–

F

R

X 45

SEATING
PLANE

D 14 PL

K

C

J

M

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

____

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Notes

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Notes

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Notes

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