SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC74HC7266A is identical in pinout to the LS266 and the HC266.
The HC7266 has standard CMOS outputs instead of open–drain outputs.
The device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LSTTL outputs.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 56 FETs or 14 Equivalent Gates
LOGIC DIAGRAM
N SUFFIX
14
1
14
1
14
1
ORDERING INFORMATION
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
Plastic
SOIC
TSSOP
A1
B1
A2
B2
A3
B3
A4
B4
1
2
5
6
8
9
12
13
10
11
PIN 14 = V
PIN 7 = GND
CC
3
Y1
PIN ASSIGNMENT
A1
B1
Y1
Y2
A2
B2
GND
1
2
3
4
6
7
4
Y2
Y3
Y4
Y = A
B
Y = AB + AB
14
13
12
11
105
V
CC
B4
A4
Y4
Y3
B3
9
A3
8
FUNCTION TABLE
Inputs Output
ABY
LLH
LHL
HLL
HHH
3/97
Motorola, Inc. 1997
3–1
REV 1
MC74HC7266A
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
MAXIMUM RATINGS*
Symbol
V
V
I
I
Î
Î
T
Î
Î
DC Supply Voltage (Referenced to GND)
CC
V
DC Input Voltage (Referenced to GND)
in
DC Output Voltage (Referenced to GND)
out
I
DC Input Current, per Pin
in
DC Output Current, per Pin
out
DC Supply Current, VCC and GND Pins
CC
P
Power Dissipation in Still Air Plastic DIP†
D
ОООООООООООО
ОООООООООООО
Storage Temperature
stg
ОООООООООООО
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
ОООООООООООО
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Parameter
SOIC Package†
TSSOP Package†
(Plastic DIP, SOIC or TSSOP Package)
Value
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
± 20
± 25
± 50
750
500
ÎÎÎÎ
450
ÎÎÎÎ
– 65 to + 150
ÎÎÎÎ
ÎÎÎÎ
260
Unit
V
V
V
mA
mA
mA
mW
Î
Î
_
C
Î
_
C
Î
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
should be constrained to the
out
range GND v (Vin or V
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
) v VCC.
out
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
Vin, V
T
A
tr, t
ÎÎ
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
out
Operating Temperature, All Package Types
Input Rise and Fall Time VCC = 2.0 V
f
(Figure 1) VCC = 4.5 V
ОООООООООООО
Parameter
VCC = 6.0 V
Min
2.0
0
– 55
0
0
Î
0
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
ÎÎ
V
IH
ÎÎ
ÎÎ
V
IL
ÎÎ
ÎÎ
V
OH
ÎÎ
ÎÎ
ÎÎÎОООООООÎООООООО
ООООООО
Minimum High–Level Input
ООООООО
Voltage
ООООООО
Maximum Low–Level Input
ООООООО
Voltage
ООООООО
Minimum High–Level Output
ООООООО
Voltage
ООООООО
Parameter
Test Conditions
ООООООО
V
= 0.1 V or VCC – 0.1 V
out
ООООООО
|I
| v 20 µA
out
ООООООО
V
= 0.1 V or VCC – 0.1 V
out
ООООООО
|I
| v 20 µA
out
ООООООО
Vin = VIH or V
ООООООО
|I
| v 20 µA
out
ООООООО
Vin = VIH or VIL|I
IL
| v 2.4 mA
out
|I
| v 4.0 mA
out
|I
| v 5.2 mA
out
Max
6.0
V
CC
+ 125
1000
500
Î
400
Unit
V
V
_
C
ns
Î
V
CC
V
ÎÎ
2.0
ÎÎ
3.0
4.5
ÎÎ
6.0
2.0
ÎÎ
3.0
4.5
ÎÎ
6.0
2.0
ÎÎ
4.5
6.0
ÎÎ
3.0
4.5
ÎÎ
6.0
Guaranteed Limit
– 55 to
25_C
ÎÎ
ÎÎ
ÎÎ
1.5
2.1
3.15
ÎÎ
ÎÎ
ÎÎ
4.2
0.5
ÎÎ
ÎÎ
0.9
1.35
ÎÎ
ÎÎ
1.8
1.9
ÎÎ
ÎÎ
4.4
5.9
ÎÎ
ÎÎ
2.48
3.98
ÎÎ
5.48
ÎÎ
v
85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
v
125_C
ÎÎ
1.5
ÎÎ
2.1
3.15
ÎÎ
4.2
0.5
ÎÎ
0.9
1.35
ÎÎ
1.8
1.9
ÎÎ
4.4
5.9
ÎÎ
2.20
3.70
ÎÎ
5.20
Unit
Î
Î
Î
Î
Î
Î
Î
Î
V
V
V
MOTOROLA High–Speed CMOS Logic Data
3–2
DL129 — Rev 6
MC74HC7266A
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
V
CC
Symbol
Symbol
V
OL
ÎÎ
ÎÎ
ÎÎ
I
in
ÎÎ
I
CC
ÎÎ
Parameter
Parameter
Maximum Low–Level Output
Voltage
ООООООО
ООООООО
ООООООО
Maximum Input Leakage Current
ООООООО
Maximum Quiescent Supply
ООООООО
Current (per Package)
Test Conditions
Test Conditions
Vin = VIH or V
|I
| v 20 µA
out
ООООООО
Vin = VIH or VIL|I
ООООООО
ООООООО
Vin = VCC or GND
ООООООО
Vin = VCC or GND
ООООООО
I
= 0 µA
out
IL
| v 2.4 mA
out
|I
| v 4.0 mA
out
|I
| v 5.2 mA
out
CC
2.0
4.5
ÎÎ
6.0
3.0
4.5
ÎÎ
6.0
ÎÎ
6.0
ÎÎ
6.0
ÎÎ
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
– 55 to
V
V
25_C
0.1
0.1
ÎÎ
0.1
0.26
0.26
ÎÎ
0.26
ÎÎ
± 0.1
ÎÎ
ÎÎ1ÎÎ
v
85_C
0.1
0.1
ÎÎ
0.1
0.33
0.33
ÎÎ
0.33
ÎÎ
± 1.0
ÎÎ
10
v
125_C
0.1
0.1
ÎÎ
0.1
0.40
0.40
ÎÎ
0.40
ÎÎ
± 1.0
ÎÎ
40
ÎÎ
Unit
Unit
Î
Î
Î
µA
Î
µA
Î
V
AC ELECTRICAL CHARACTERISTICS ( C
= 50 pF, Input tr = tf = 6 ns)
L
Guaranteed Limit
Symbol
t
,
PLH
ÎÎ
t
PHL
ÎÎ
t
,
TLH
ÎÎ
t
THL
ÎÎ
C
in
Parameter
Maximum Propagation Delay, Input A or B to Output Y
ООООООООООООООО
(Figures 1 and 2)
ООООООООООООООО
Maximum Output Transition Time, Any Output
ООООООООООООООО
(Figures 1 and 2)
ООООООООООООООО
Maximum Input Capacitance
V
CC
2.0
ÎÎ
3.0
4.5
ÎÎ
6.0
2.0
ÎÎ
3.0
4.5
ÎÎ
6.0
—
– 55 to
V
25_C
100
ÎÎ
80
20
ÎÎ
17
75
ÎÎ
30
15
ÎÎ
13
10
v
85_Cv 125_C
125
ÎÎ
90
25
ÎÎ
21
95
ÎÎ
40
19
ÎÎ
16
10
ÎÎ
ÎÎ
ÎÎ
ÎÎ
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
*Used to determine the no–load dynamic power consumption: PD = CPD V
Motorola High–Speed CMOS Data Book (DL129/D).
INPUT
A OR B
OUTPUT Y
Power Dissipation Capacitance (Per Gate)*
t
t
r
f
90%
50%
10%
t
PLH
90%
50%
t
PHL
V
CC
GND
33
2
f + ICC VCC. For load considerations, see Chapter 2 of the
CC
OUTPUT
DEVICE
UNDER
TEST
10%
150
110
25
19
Î
Î
110
55
22
19
Î
Î
10
TEST POINT
CL*
Unit
ns
ns
pF
pF
High–Speed CMOS Logic Data
DL129 — Rev 6
t
TLH
t
THL
*Includes all probe and jig capacitance
Figure 1. Switching Waveforms Figure 2. T est Circuit
3–3 MOTOROLA
MC74HC7266A
LOGIC DETAIL
(1/4 of Device)
A
Y
B
APPLICATION INFORMATION
Bi φ–L is defined as biphase–level code. Also known as
Manchester Code, this technique utilizes binary phase shift
keying (PSK). The Bi φ–L output shown in Figure 3 carries
both data and synchronization information; therefore, separate data and clock lines are not required to transfer information. A positive–going transition in the middle of the bit
interval indicates a logic zero; a negative–going transition in-
NRZ–L
CLOCK
Figure 3. Biphase–Level Encoder (Manchester Encoder)
NRZ–L
CLOCK
dicates a logic one (see Figure 4).
NRZ–L shown in Figure 3 is non–return–to–zero level
code. This is simply serial data out of a shift register, such as
the HC597.
The Bi φ–L signal must be phase coherent (i.e., no
glitches). Therefore, NRZ–L and clock transitions must be
coincident.
1/4
HC7266A
BI
φ
–L
BI
φ
–L
POSITIVE
LOGIC DATA
101100
BIT
INTERV AL
Figure 4. Timing Diagram
MOTOROLA High–Speed CMOS Logic Data
3–4
DL129 — Rev 6
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
14 8
B
17
A
F
N
SEATING
HG D
PLANE
C
K
L
J
M
MC74HC7266A
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
M 0 10 0 10
____
N 0.015 0.039 0.39 1.01
MILLIMETERSINCHES
SEATING
PLANE
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
–A–
814
P 7 PL
–B–
M M
1
G
D 14 PL
0.25 (0.010) T B A
7
X 45°
C
R
K
M
S S
B0.25 (0.010)
M
J
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
F
MILLIMETERS INCHES
MIN MINMAX MAX
DIM
A
B
C
D
F
G
J
K
M
P
R
8.75
8.55
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC 0.050 BSC
0.25
0.19
0.25
0.10
7
0
°
°
5.80
6.20
0.25
0.50
0.337
0.150
0.054
0.014
0.016
0.008
0.004
0.228
0.010
0.344
0.157
0.068
0.019
0.049
0.009
0.009
7
0
°
°
0.244
0.019
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5 MOTOROLA
MC74HC7266A
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
0.10 (0.004)
SEATING
–T–
PLANE
14X REFK
S
U
T
S
N
0.25 (0.010)
U0.15 (0.006) T
S
2X L/2
0.10 (0.004) V
14
M
8
M
L
PIN 1
IDENT.
1
S
U0.15 (0.006) T
A
–V–
B
–U–
N
F
7
DETAIL E
K
K1
J
J1
SECTION N–N
C
D
G
H
DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
INCHESMILLIMETERS
–W–
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
____
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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◊
MOTOROLA High–Speed CMOS Logic Data
3–6
Mfax is a trademark of Motorola, Inc.
MC74HC7266A/D
DL129 — Rev 6
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