SEMICONDUCTOR TECHNICAL DATA
1
REV 2
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC54/74HC533A is identical in pinout to the LS533. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches a ppear transparent to data (i.e., the o utputs change
asynchronously) when Latch E nable is high. T he Data appears at the
outputs in inverted form. When Latch Enable goes low, data meeting the
setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high-impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HC533A is identical in function to the HC563 but has the data inputs
on the opposite side of the package from the outputs to facilitate PC board
layout.
This device is similar in function to the HC373A, which has noninverting
outputs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 256 FETs or 64 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
18
17
14
13
8
7
4
3
1
OUTPUT ENABLE
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
16
15
12
9
6
5
2
PIN 20 = V
CC
PIN 10 = GND
INVERTING
OUTPUTS
11
LATCH ENABLE
PIN ASSIGNMENT
Q2
D1
D0
Q0
OUTPUT
ENABLE
GND
Q3
D3
D2
Q1 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q6
D6
D7
Q7
V
CC
LATCH
ENABLE
Q4
D4
D5
Q5
FUNCTION TABLE
Inputs Output
Output Latch
Enable Enable D Q
L H H L
L H L H
L L X No Change
H X X Z
X = Don’t Care
Z = High Impedance
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
Ceramic
Plastic
SOIC
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
1
20
1
20
MC54/74HC533A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 35
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
P
D
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
OH
Minimum High–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or V
IL
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
V
OL
Maximum Low–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or V
IL
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
V
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC54/74HC533A
High–Speed CMOS Logic Data
DL129 — Rev 6
3 MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Unit
Guaranteed Limit
V
CC
V
Test Conditions
Parameter
Symbol
Unit
v
125_C
v
85_C
– 55 to
25_C
V
CC
V
Test Conditions
Parameter
Symbol
I
OZ
Maximum Three–State Leakage
Current
Output in High–Impedance State
Vin = VIL or V
IH
V
out
= VCC or GND
6.0
± 0.5
± 5.0
± 10
µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
|I
out
| = 0 µA
6.0
4.0
40
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
Fig.
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
t
PLH
t
PHL
Maximum Propagation Delay, Input D to Q 1, 5 2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
PLH
t
PHL
Maximum Propagation Delay, Latch Enable to Q 2, 5 2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
PLZ
t
PHZ
Maximum Propagation Delay, Output Enable to Q 3, 6 2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
PZL
t
PZH
Maximum Propagation Delay, Output Enable to Q 3, 6 2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
TLH
t
THL
Maximum Output Transition Time, Any Output 1, 5 2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
in
Maximum Input Capacitance
10
10
10
pF
C
out
Maximum Tri–State Output Capacitance (Output in Hi–Impedance State)
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
36
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
MC54/74HC533A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
TIMING REQUIREMENTS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
V
– 55 to 25_C
v
85_C
v
125_C
Symbol
Parameter
Fig.
V
CC
Volts
Min
Max
Min
Max
Min
Max
Unit
t
su
Minimum Setup Time, Input D to Latch Enable 4 2.0
4.5
6.0
25
5.0
5.0
30
6.0
6.0
40
8.0
7.0
ns
t
h
Minimum Hold Time, Latch Enable to Input D 4 2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
t
w
Minimum Pulse Width, Latch Enable 2 2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tr, tfMaximum Input Rise and Fall Times 1 2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
SWITCHING WAVEFORMS
Figure 1. Figure 2.
Figure 3. Figure 4.
10%
50%
90%
10%
50%
90%
Q
INPUT D
t
THL
t
TLH
t
PLH
t
PHL
GND
V
CC
t
f
t
r
V
CC
t
w
GND
t
PHL
t
PLH
Q
50%
50%
LATCH
ENABLE
50%
10%
90%
1.3 V
Q
Q
t
PLZ
t
PZL
t
PHZ
t
PZH
V
OH
V
OL
HIGH
IMPEDANCE
GND
V
CC
50%
OUTPUT
ENABLE
V
CC
V
CC
INPUT D
VALID
GND
50%
50%
GND
LATCH
ENABLE
t
su
t
h
HIGH
IMPEDANCE
MC54/74HC533A
High–Speed CMOS Logic Data
DL129 — Rev 6
5 MOTOROLA
TEST CIRCUITS
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO VCC WHEN
TESTING t
PLZ
AND t
PZL
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
1 k
Ω
Figure 5. Figure 6.
EXPANDED LOGIC DIAGRAM
Q7
19
18
D7
Q6
16
17
D6
Q5
15
14
D5
Q4
12
13
D4
Q1
5
4
D1
Q3
9
8
D3
Q2
6
7
D2
Q0
2
3
D0
1
11
LE
QD
LE
QD
LE
QD
LE
QD
LE
QD
LE
QD
LE
QD
LE
QD
LATCH
ENABLE
OUTPUT
ENABLE
MC54/74HC533A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
6
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 23.88 25.15 0.940 0.990
B 6.60 7.49 0.260 0.295
C 3.81 5.08 0.150 0.200
D 0.38 0.56 0.015 0.022
F 1.40 1.65 0.055 0.065
G 2.54 BSC 0.100 BSC
H 0.51 1.27 0.020 0.050
J 0.20 0.30 0.008 0.012
K 3.18 4.06 0.125 0.160
L 7.62 BSC 0.300 BSC
M 0 15 0 15
N 0.25 1.02 0.010 0.040
_ _ _ _
A
20
1 10
11
B
F
C
SEATING
PLANE
D
H
G
K
N
J
M
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J
20 PL
M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022
G 2.54 BSC0.100 BSC
J 0.21 0.380.008 0.015
K 2.80 3.550.110 0.140
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040
_ __ _
E
1.27 1.770.050 0.070
1
11
10
20
–A–
SEATING
PLANE
K
N
FG
D
20 PL
–T–
M
A
M
0.25 (0.010) T
E
B
C
F
1.27 BSC0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
–B–
20
1
11
10
S
A
M
0.010 (0.25) B
S
T
D20X
M
B
M
0.010 (0.25)
P10X
J
F
G
18X
K
C
–T–
SEATING
PLANE
M
R
X 45
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
_ _
_ _
MC54/74HC533A
High–Speed CMOS Logic Data
DL129 — Rev 6
7 MOTOROLA
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MC54/74HC533A/D
*MC54/74HC533A/D*
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