Datasheet MC74HC4040AFL1, MC74HC4040AFR1, MC74HC4040AFR2, MC74HC4040ADT, MC74HC4040ADTEL Datasheet (MOTOROLA)

...
Semiconductor Components Industries, LLC, 2000
May, 2000 – Rev. 3
1 Publication Order Number:
MC74HC4040A/D
MC74HC4040A
12-Stage Binary Ripple Counter
High–Performance Silicon–Gate CMOS
This device consists of 12 master–slave flip–flops. The output of each flip–flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative–going edge of the Clock input. Reset is asynchronous and active–high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With JEDEC Standard No. 7A Requirements
Chip Complexity: 398 FETs or 99.5 Equivalent Gates
LOGIC DIAGRAM
Q1
9
Q2
7
Q3
6
Q4
5
Q5
3
Q6
2
Q7
4
Q8
13
Q9
12
Q10
14
Clock
10
Reset
11
Pin 16 = V
CC
Pin 8 = GND
1516 14 13 12 11 10
21 34567
V
CC
9
8
Q11 Q10 Q8 Q9 Reset Clock Q1
Q12 Q6 Q5 Q7 Q4 Q3 Q2
GND
Pinout: 16–Lead Plastic Package
(Top View)
Q11
15
Q12
1
SO–16
D SUFFIX
CASE 751B
http://onsemi.com
TSSOP–16 DT SUFFIX CASE 948F
1
16
PDIP–16 N SUFFIX CASE 648
1
16
1
16
MARKING
DIAGRAMS
1
16
MC74HC4040AN
AWLYYWW
1
16
HC4040A
AWLYWW
A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week
HC40
40A
ALYW
1
16
Device Package Shipping
ORDERING INFORMATION
MC74HC4040AN PDIP–16 2000 / Box MC74HC4040AD SOIC–16
48 / Rail MC74HC4040ADR2 SOIC–16 2500 / Reel MC74HC4040ADT TSSOP–16 96 / Rail MC74HC4040ADTR2 TSSOP–16
2500 / Reel
FUNCTION TABLE
Clock Reset Output State
X
L L H
No Charge
Advance to Next State
All Outputs Are Low
MC74HC4040A
http://onsemi.com
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
ÎÎ
Î
P
D
ОООООООООООО
Î
Power Dissipation in Still Air, Plastic DIP†
SOIC Package†
TSSOP Package†
ÎÎÎ
Î
750 500 450
Î
Î
mW
T
stg
Storage Temperature Range
– 65 to + 150
_
C
ÎÎ
Î
T
L
ОООООООООООО
Î
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
ÎÎÎ
Î
260
Î
Î
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
ÎÎ
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
ÎÎ
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
ÎÎ
V
CC
V
T
A
Operating Temperature Range, All Package Types
– 55
ÎÎ
+ 125
_
C
ÎÎ
Î
ÎÎ
Î
tr, t
f
ООООООООООООО
Î
ООООООООООООО
Î
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 3.0 V
VCC = 4.5 V VCC = 6.0 V
Î
Î
Î
Î
0 0 0 0
ÎÎ
ÎÎ
ÎÎ
1000
600 500 400
Î
Î
Î
Î
ns
DC CHARACTERISTICS (Voltages Referenced to GND)
V
Guaranteed Limit
Symbol Parameter Condition
V
CC
V
–55 to 25°C ≤85°C ≤125°C
Unit
V
IH
Minimum High–Level Input Voltage
V
out
= 0.1V or VCC –0.1V
|I
out
| 20µA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
V
IL
Maximum Low–Level Input Voltage
V
out
= 0.1V or VCC – 0.1V
|I
out
| 20µA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
V
OH
Minimum High–Level Output Voltage
Vin = VIH or V
IL
|I
out
| 20µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin =VIH or V
IL
|I
out
| 2.4mA
|I
out
| 4.0mA
|I
out
| 5.2mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
V
OL
Maximum Low–Level Output Voltage
Vin = VIH or V
IL
|I
out
| 20µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance cir­cuit. For proper operation, Vin and V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
MC74HC4040A
http://onsemi.com
3
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol Unit
Guaranteed Limit
V
CC V
ConditionParameter
Symbol Unit≤125°C≤85°C–55 to 25°C
V
CC V
ConditionParameter
Vin = VIH or V
IL|Iout
| 2.4mA
|I
out
| 4.0mA
|I
out
| 5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
I
CC
Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND I
out
= 0µA
6.0 4 40 160 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
AC CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol Parameter
V
CC
V
–55 to 25°C ≤85°C ≤125°C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4)
2.0
3.0
4.5
6.0
10 15 30 50
9.0 14 28 45
8.0 12 25 40
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q1* (Figures 1 and 4)
2.0
3.0
4.5
6.0
96 63 31 25
106
71 36 30
115
88 40 35
ns
t
PHL
Maximum Propagation Delay, Reset to Any Q (Figures 2 and 4)
2.0
3.0
4.5
6.0
45 30 30 26
52 36 35 32
65 40 40 35
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Qn to Qn+1 (Figures 3 and 4)
2.0
3.0
4.5
6.0
69 40 17 14
80 45 21 15
90 50 28 22
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output (Figures 1 and 4)
2.0
3.0
4.5
6.0
75 27 15 13
95 32 19 15
110
36 22 19
ns
C
in
Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
* For TA = 25°C and CL = 50 pF , typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] ns VCC = 3.0 V: tP = [61.5 + 34.4 (n–1)] ns VCC = 6.0V: tP = [24.4 + 12 (n–1)] ns
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
31
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
MC74HC4040A
http://onsemi.com
4
TIMING REQUIREMENTS (Input t
r
= tf = 6 ns)
V
Guaranteed Limit
Symbol Parameter
V
CC
V
–55 to 25°C ≤85°C ≤125°C
Unit
t
rec
Minimum Recovery Time, Reset Inactive to Clock (Figure 2)
2.0
3.0
4.5
6.0
30 20
5 4
40 25
8 6
50 30 12
9
ns
t
w
Minimum Pulse Width, Clock (Figure 1)
2.0
3.0
4.5
6.0
70 40 15 13
80 45 19 16
90 50 24 20
ns
t
w
Minimum Pulse Width, Reset (Figure 2)
2.0
3.0
4.5
6.0
70 40 15 13
80 45 19 16
90 50 24 20
ns
tr, t
f
Maximum Input Rise and Fall Times (Figure 1)
2.0
3.0
4.5
6.0
1000
800 500 400
1000
800 500 400
1000
800 500 400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
PIN DESCRIPTIONS
INPUTS Clock (Pin 10)
Negative–edge triggering clock input. A high–to–low
transition on this input advances the state of the counter.
Reset (Pin 11)
Active–high reset. A high level applied to this input asynchronously resets the counter to its zero state, thus forcing all Q outputs low.
OUTPUTS Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)
Active–high outputs. Each Qn output divides the Clock
input frequency by 2N.
SWITCHING W AVEFORMS
t
f
Clock
Q1
V
CC
GND
90% 50% 10%
t
r
t
w
90%
50%
10%
t
PHL
1/f
MAX
t
PLH
t
TLH
t
THL
Clock
V
CC
GND
t
w
t
rec
50%
Figure 1. Figure 2.
Reset
V
CC
GND
50%
Any Q 50%
t
PHL
MC74HC4040A
http://onsemi.com
5
SWITCHING W AVEFORMS (continued)
50%
Qn
V
CC
GND
50%
Qn+1
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE UNDER
TEST
OUTPUT
Figure 3. Figure 4. Test Circuit
t
PLH
t
PHL
Figure 5. Expanded Logic Diagram
Clock
10
C
C
R
Reset
11
Q
Q
C
C
R
Q
Q
Q1
9
C
CQQ
C
CQQ
C
CQQ
C
C
Q
Q2
7
Q3
6
Q10
14
Q11
15
Q12
1
Q4 = Pin 5 Q5 = Pin 3 Q6 = Pin 2
Q7 = Pin 4 Q8 = Pin 13 Q9 = Pin 12
VCC = Pin 16 GND = Pin 8
MC74HC4040A
http://onsemi.com
6
Clock
Reset
Q1
1 2 4 8 16 32 64 128 256 512 1024 2048 4096
Q2 Q3 Q4 Q5 Q6 Q7 Q8
Q10 Q11
Figure 6. Timing Diagram
Q9
Q12
APPLICATIONS INFORMATION
Time–Base Generator
A 60Hz sinewave obtained through a 100 K resistor connected to a 120 Vac power line through a step down transformer is applied to the input of the MC54/74HC14A, Schmitt-trigger inverter. The HC14A squares–up the input
waveform and feeds the HC4040A. Selecting outputs Q5, Q10, Q11, and Q12 causes a reset every 3600 clocks. The HC20 decodes the counter outputs, produces a single (narrow) output pulse, and resets the binary counter. The resulting output frequency is 1.0 pulse/minute.
HC4040A
Figure 7. Time–Base Generator
Clock Q5
Q10
Q11
Q12
V
CC
13 12 10 9
1 2 4 5
8
1/2
HC20
1/2
HC20
6
1/6 of HC14A
20 pF
100 K
1.0 Pulse/Minute Output
V
CC
110 Vac
15 – 30
Volts
MC74HC4040A
http://onsemi.com
7
P ACKAGE DIMENSIONS
PDIP–16
N SUFFIX
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01
____
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019
____
MC74HC4040A
http://onsemi.com
8
P ACKAGE DIMENSIONS
TSSOP–16 DT SUFFIX
CASE 948F–01
ISSUE O
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C ––– 1.20 ––– 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.
____
SECTION N–N
SEATING PLANE
IDENT.
PIN 1
1
8
16
9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
DETAIL E
F
M
L
2X L/2
–U–
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V
S
T
0.10 (0.004)
–T–
–V–
–W–
0.25 (0.010)
16X REFK
N
N
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .
PUBLICATION ORDERING INFORMATION
CENTRAL/SOUTH AMERICA:
Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
Email: ONlit–spanish@hibbertco.com
ASIA/PACIFIC : LDC for ON Semiconductor – Asia Support
Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
T oll Free from Hong Kong & Singapore:
001–800–4422–3781
Email: ONlit–asia@hibbertco.com
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, T okyo, Japan 141–8549
Phone: 81–3–5740–2745 Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local Sales Representative.
MC74HC4040A/D
NORTH AMERICA Literature Fulfillment:
Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 T oll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: ONlit@hibbertco.com
Fax Response Line: 303–675–2167 or 800–344–3810 T oll Free USA/Canada
N. American Technical Support: 800–282–9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor – European Support
German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)
Email: ONlit–german@hibbertco.com
French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse T ime)
Email: ONlit–french@hibbertco.com
English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK T ime)
Email: ONlit@hibbertco.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
*Available from Germany, France, Italy , England, Ireland
Loading...