Datasheet MC74HC390AFR1, MC74HC390AFL1, MC74HC390ADTEL, MC74HC390ADTR2, MC74HC390AF Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 2

1 Publication Order Number:

MC74HC390A/D

MC74HC390A

Dual 4-Stage Binary Ripple
Counter with

÷

2 and

÷

5

Sections

High–Performance Silicon–Gate CMOS

The MC74HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.

This device consists of two independent 4–bit counters, each
composed of a divide–by–two and a divide–by–five section. The
divide–by–two and divide–by–five counters have separate clock
inputs, and can be cascaded to implement various combinations of ÷ 2
and/or ÷ 5 up to a ÷ 100 counter.

Flip–flops internal to the counters are triggered by high–to–low
transitions of the clock input. A separate, asynchronous reset is
provided for each 4–bit counter. State changes of the Q outputs do not
occur simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and should not
be used as clocks or strobes except when gated with the Clock of the
HC390A.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No 7A

• Chip Complexity: 244 FETs or 61 Equivalent Gates

LOGIC DIAGRAM

Q

A

Q

B

Q

C

Q

D

1, 15

4, 12

2, 14

3, 13

5, 11
6, 10

7, 9

PIN 16 = V

CC

PIN 8 = GND

CLOCK A

RESET

CLOCK B

÷ 2

COUNTER

÷ 5

COUNTER

FUNCTION TABLE

Clock

A B Reset Action

X X H Reset

÷ 2 and ÷ 5

X L Increment

÷ 2

X L Increment

÷ 5

SO–16

D SUFFIX

CASE 751B

http://onsemi.com

TSSOP–16
DT SUFFIX
CASE 948F

1

16

PDIP–16
N SUFFIX
CASE 648

1

16

1

16

MARKING

DIAGRAMS

1

16

MC74HC390AN

AWLYYWW

1

16

HC390A

AWLYWW

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week

HC

390A

ALYW

1

16

Device Package Shipping

ORDERING INFORMATION

MC74HC390AN PDIP–16 2000 / Box
MC74HC390AD SOIC–16

48 / Rail
MC74HC390ADR2 SOIC–16 2500 / Reel
MC74HC390ADT TSSOP–16 96 / Rail
MC74HC390ADTR2 TSSOP–16

2500 / Reel

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

CLOCK B

b

Q

Ab

RESET b

CLOCK A

b

V

CC

Q

Db

Q

Cb

Q

Bb

CLOCK B

a

Q

Aa

RESET a

CLOCK A

a

GND

Q

Da

Q

Ca

Q

Ba

MC74HC390A

http://onsemi.com

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎ

Î

750
500
450

Î

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

ÎÎÎ

Î

260

Î

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

ÎÎ

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

ÎÎ

+ 125

_

C

ÎÎ

Î

ÎÎ

Î

tr, t

f

ООООООООООООО

Î

ООООООООООООО

Î

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 3.0 V

VCC = 4.5 V
VCC = 6.0 V

Î

Î

Î

Î

0
0
0
0

ÎÎ

ÎÎ

ÎÎ

1000

600
500
400

Î

Î

Î

Î

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Î

Symbol

ООООООО

Î

Parameter

ООООООО

Î

Test Conditions

ÎÎ

Î

V

CC
V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

Î

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎ

Î

ÎÎ

Î

V

IH

ООООООО

Î

ООООООО

Î

Minimum High–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

ÎÎÎ

Î

Î

Î

Î

Î

Î

1.5

2.1

3.15

4.2

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

Î

Î

Î

Î

V

ÎÎ

Î

V

IL

ООООООО

Î

Maximum Low–Level Input
Voltage

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

0.5

0.9

1.35

1.8

ÎÎÎ

Î

Î

Î

0.5

0.9

1.35

1.8

ÎÎ

Î

0.5

0.9

1.35

1.8

Î

Î

V

ÎÎ

Î

ÎÎ

Î

V

OH

ООООООО

Î

ООООООО

Î

Minimum High–Level Output
Voltage

ООООООО

Î

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1.9

4.4

5.9

ÎÎÎ

Î

Î

Î

Î

Î

Î

1.9

4.4

5.9

ÎÎ

Î

ÎÎ

Î

1.9

4.4

5.9

Î

Î

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

2.48

3.98

5.48

ÎÎÎ

Î

Î

Î

2.34

3.84

5.34

ÎÎ

Î

2.20

3.70

5.20

Î

Î

ÎÎ

Î

V

OL

ООООООО

Î

Maximum Low–Level Output
Voltage

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

0.1

0.1

0.1

ÎÎÎ

Î

Î

Î

0.1

0.1

0.1

ÎÎ

Î

0.1

0.1

0.1

Î

Î

V

ÎÎ

Î

ÎÎ

Î

ООООООО

Î

ООООООО

Î

ООООООО

Î

ООООООО

Î

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

ÎÎ

Î

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

0.26

0.26

0.26

ÎÎÎ

Î

Î

Î

Î

Î

Î

0.33

0.33

0.33

ÎÎ

Î

ÎÎ

Î

0.40

0.40

0.40

Î

Î

Î

Î

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HC390A

http://onsemi.com

3

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Unit

Guaranteed Limit

V

CC

V

Test Conditions

Parameter

Symbol

Unit

v

125_C

ÎÎÎ

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

ÎÎ

Î

I

in

ООООООО

Î

Maximum Input Leakage
Current

ООООООО

Î

Vin = VCC or GND

ÎÎ

Î

6.0

ÎÎ

Î

± 0.1

ÎÎÎ

Î

Î

Î

± 1.0

ÎÎ

Î

± 1.0

Î

Î

µA

ÎÎ

Î

I

CC

ООООООО

Î

Maximum Quiescent Supply
Current (per Package)

ООООООО

Î

Vin = VCC or GND
I

out

= 0 µA

ÎÎ

Î

6.0

ÎÎ

Î

4

ÎÎÎ

Î

Î

Î

40

ÎÎ

Î

160

Î

Î

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tf = tf = 6 ns)

Guaranteed Limit

ÎÎÎ

Î

Symbol

ОООООООООООООО

Î

Parameter

ÎÎ

Î

V

CC
V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

Î

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎÎ

Î

ÎÎÎ

Î

f

max

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

10
15
30
50

ÎÎÎ

Î

Î

Î

Î

Î

Î

9
14
28
45

ÎÎ

Î

ÎÎ

Î

8
12
25
40

Î

Î

Î

Î

MHz

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

Maximum Propagation Delay, Clock A to QA

(Figures 1 and 3)

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

70
40
24
20

ÎÎÎ

Î

Î

Î

80
45
30
26

ÎÎ

Î

90
50
36
31

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Clock A to QC
(QA connected to Clock B)

(Figures 1 and 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

200
160

58
49

ÎÎÎ

Î

Î

Î

Î

Î

Î

250
185

65
62

ÎÎ

Î

ÎÎ

Î

300
210

70
68

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Clock B to QB

(Figures 1 and 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

70
40
26
22

ÎÎÎ

Î

Î

Î

Î

Î

Î

80
45
33
28

ÎÎ

Î

ÎÎ

Î

90
50
39
33

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Clock B to QC

(Figures 1 and 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

90
56
37
31

ÎÎÎ

Î

Î

Î

Î

Î

Î

105

70
46
39

ÎÎ

Î

ÎÎ

Î

180
100

56
48

Î

Î

Î

Î

ns

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

Maximum Propagation Delay, Clock B to QD

(Figures 1 and 3)

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

70
40
26
22

ÎÎÎ

Î

Î

Î

80
45
33
28

ÎÎ

Î

90
50
39
33

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PHL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Reset to any Q

(Figures 2 and 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

80
48
30
26

ÎÎÎ

Î

Î

Î

Î

Î

Î

95
65
38
33

ÎÎ

Î

ÎÎ

Î

110

75
44
39

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

TLH

,

t

THL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

75
27
15
13

ÎÎÎ

Î

Î

Î

Î

Î

Î

95
32
19
15

ÎÎ

Î

ÎÎ

Î

110

36
22
19

Î

Î

Î

Î

ns

C

in

Maximum Input Capacitance

—

10

ÎÎÎ

10

10

pF

1. For propagation delays with loads other than 50 pF , see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Counter)*

35

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

MC74HC390A

http://onsemi.com

4

TIMING REQUIREMENTS (Input t

r

= tf = 6 ns)

Guaranteed Limit

ÎÎÎ

Î

Symbol

ОООООООООООООО

Î

Parameter

ÎÎ

Î

V

CC
V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

Î

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎÎ

Î

t

rec

ОООООООООООООО

Î

Minimum Recovery Time, Reset Inactive to Clock A or Clock B

(Figure 2)

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

25
15
10

9

ÎÎÎ

Î

Î

Î

30
20
13
11

ÎÎ

Î

40
30
15
13

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

w

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Pulse Width, Clock A, Clock B

(Figure 1)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

75
27
15
13

ÎÎÎ

Î

Î

Î

Î

Î

Î

95
32
19
15

ÎÎ

Î

ÎÎ

Î

110

36
22
19

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

w

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Pulse Width, Reset

(Figure 2)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

75
27
20
18

ÎÎÎ

Î

Î

Î

Î

Î

Î

95
32
24
22

ÎÎ

Î

ÎÎ

Î

110

36
30
28

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

tf, t

f

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Input Rise and Fall Times

(Figure 1)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1000

800
500
400

ÎÎÎ

Î

Î

Î

Î

Î

Î

1000

800
500
400

ÎÎ

Î

ÎÎ

Î

1000

800
500
400

Î

Î

Î

Î

ns

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

PIN DESCRIPTIONS

INPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)

Clock A is the clock input to the ÷ 2 counter; Clock B is

the clock input to the ÷ 5 counter. The internal flip–flops are
toggled by high–to–low transitions of the clock input.

CONTROL INPUTS
Reset (Pins 2, 14)

Asynchronous reset. A high at the Reset input prevents

counting, resets the internal flip–flops, and forces Q

A

through QD low.

OUTPUTS
QA (Pins 3, 13)

Output of the ÷ 2 counter.

QB, QC, QD (Pins 5, 6, 7, 9, 10, 11)

Outputs of the ÷ 5 counter. QD is the most significant bit.

QA is the least significant bit when the counter is connected
for BCD output as in Figure 4. QB is the least significant bit
when the counter is operating in the bi–quinary mode as in
Figure 5.

SWITCHING W AVEFORMS

Q

t

r

t

f

t

PLH

t

PHL

t

TLH

t

THL

V

CC

GND

CLOCK

10%

50%

90%

1/f

max

t

w

t

rec

RESET

Figure 1. Figure 2.

V

CC

GND

V

CC

GND

10%

50%

90%

Q

CLOCK

50%

50%

50%

t

PHL

t

w

10%

MC74HC390A

http://onsemi.com

5

C

D

R

Q
Q

0123456789

EXPANDED LOGIC DIAGRAM

TIMING DIAGRAM

(QA Connected to Clock B)

Q

A

Q

B

Q

C

Q

D

CLOCK A

RESET

Q

A

Q

B

Q

C

Q

D

CLOCK A

CLOCK B

RESET

3, 13

5, 11

6, 10

7, 9

1, 15

4, 12

2, 14

C

D

R

Q
Q

C

D

R

Q
Q

C

DRQ

0123456

TEST CIRCUIT

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

Figure 3.

MC74HC390A

http://onsemi.com

6

APPLICATIONS INFORMATION

Each half of the MC54/74HC390A has independent ÷ 2
and ÷ 5 sections (except for the Reset function). The ÷ 2 and
÷ 5 counters can be connected to give BCD or bi–quinary
(2–5) count sequences. If Output QA is connected to the
Clock B input (Figure 4), a decade divider with BCD output
is obtained. The function table for the BCD count sequence
is given in Table 1.

To obtain a bi–quinary count sequence, the input signals
connected to the Clock B input, and output QD is connected
to the Clock A input (Figure 5). QA provides a 50% duty
cycle output. The bi–quinary count sequence function table
is given in Table 2.

Table 1. BCD Count Sequence*

Output

Count

Q

D

Q

C

Q

B

Q

A

0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L
9 H L L H

*QA connected to Clock B input.

Table 2. Bi–Quinary Count Sequence**

Output

Count

Q

A

Q

D

Q

C

Q

B

0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
8 H L L L

9 H L L H
10 H L H L
11 H L H H
12 H H L L

**QD connected to Clock A input.

CONNECTION DIAGRAMS

1, 15

÷ 2

COUNTER

CLOCK A

RESET

Figure 4. BCD Count Figure 5. Bi-Quinary Count

÷ 2

COUNTER

÷ 5

COUNTER

÷ 5

COUNTER

CLOCK B

CLOCK A

RESET

CLOCK B

1, 15

Q

A

Q

B

Q

C

Q

D

3, 13

5, 11

6, 10

7, 9

4, 12

2, 14

Q

A

Q

B

Q

C

Q

D

3, 13

5, 11
6, 10

7, 9

4, 12

2, 14

MC74HC390A

http://onsemi.com

7

P ACKAGE DIMENSIONS

PDIP–16

N SUFFIX

CASE 648–08

ISSUE R

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

A
B
C
D

F
G
H

J
K

L
M

S

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50
0°

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74
10°

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295
0°

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305
10°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

B

18

916

F

H

G

D

16 PL

S

C

–T

–

SEATING
PLANE

K

J

M

L

TA0.25 (0.010)

M M

0.25 (0.010) T B A

M

S S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G
J
K
M
P
R

9.80

3.80

1.35

0.35

0.40

0.19

0.10
0°

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

0.25
7°

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004
0°

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.009
7°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

1

8

916

–A

–

–B

–

D

16 PL

K

C

G

–T

–

SEATING

PLANE

R X 45°

M

J

F

P 8 PL

0.25 (0.010) B

M M

SOIC–16

D SUFFIX

CASE 751B–05

ISSUE J

MC74HC390A

http://onsemi.com

8

P ACKAGE DIMENSIONS

TSSOP–16
DT SUFFIX

CASE 948F–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.

____

SECTION N–N

SEATING
PLANE

IDENT.

PIN 1

1

8

16

9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

DETAIL E

F

M

L

2X L/2

–U–

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V

S

T

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

N

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

PUBLICATION ORDERING INFORMATION

CENTRAL/SOUTH AMERICA:

Spanish Phone: [phone] (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–[e-mail]

ASIA/PACIFIC : LDC for ON Semiconductor – Asia Support

Phone: [phone] (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

T oll Free from Hong Kong & Singapore:

001–800–4422–3781

Email: ONlit–[e-mail]

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, T okyo, Japan 141–8549

Phone: [phone]
Email: [e-mail]

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

MC74HC390A/D

NORTH AMERICA Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA

Phone: [phone] or 800–344–3860 T oll Free USA/Canada
Fax: [phone] or 800–344–3867 Toll Free USA/Canada
Email: [e-mail]

Fax Response Line: 303–675–2167 or 800–344–3810 T oll Free USA/Canada

N. American Technical Support: 800–282–9855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor – European Support

German Phone: [phone] (M–F 1:00pm to 5:00pm Munich Time)

Email: ONlit–[e-mail]

French Phone: [phone] (M–F 1:00pm to 5:00pm Toulouse T ime)

Email: ONlit–[e-mail]

English Phone: [phone] (M–F 12:00pm to 5:00pm UK T ime)

Email: [e-mail]

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

*Available from Germany, France, Italy , England, Ireland