Datasheet MC74HC390ADT Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

1

REV 0

 Motorola, Inc. 1995

10/95

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÷

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High–Performance Silicon–Gate CMOS

The MC54/74HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.

This device consists of two independent 4–bit counters, each composed
of a divide–by–two and a divide–by–five section. The divide–by–two and
divide–by–five counters have separate clock inputs, and can be cascaded to
implement various combinations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter.

Flip–flops internal to the counters are triggered by high–to–low transitions
of the clock input. A separate, asynchronous reset is provided for each 4–bit
counter. State changes o f the Q outputs do n ot occur simultaneously
because of internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used as clocks or strobes
except when gated with the Clock of the HC390A.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No 7A

• Chip Complexity: 244 FETs or 61 Equivalent Gates

LOGIC DIAGRAM

Q

A

Q

B

Q

C

Q

D

1, 15

4, 12

2, 14

3, 13

5, 11
6, 10

7, 9

PIN 16 = V

CC

PIN 8 = GND

CLOCK A

RESET

CLOCK B

÷

2

COUNTER

÷

5

COUNTER

This document contains information on a product under development. Motorola reserves the right
to change or discontinue this product without notice.



PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

CLOCK B

b

Q

Ab

RESET b

CLOCK A

b

V

CC

Q

Db

Q

Cb

Q

Bb

CLOCK B

a

Q

Aa

RESET a

CLOCK A

a

GND

Q

Da

Q

Ca

Q

Ba

FUNCTION TABLE

Clock

A B Reset Action

X X H Reset

÷ 2 and ÷ 5

X L Increment

÷ 2

X L Increment

÷ 5

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

Ceramic
Plastic
SOIC
TSSOP

1

16

1

16

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

1

16

1

16

DT SUFFIX

TSSOP PACKAGE

CASE 948F–01

MC54/74HC390A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

P

D

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

TSSOP Package†

750
500
450

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

(Ceramic DIP)

260
300

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 3.0 V

VCC = 4.5 V
VCC = 6.0 V

0
0
0
0

1000

600
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

3.0

4.5

6.0

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

3.0

4.5

6.0

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

V

V

OH

Minimum High–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC54/74HC390A

High–Speed CMOS Logic Data
DL129 — Rev 6

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Unit

Guaranteed Limit

V

CC

V

Test Conditions

Parameter

Symbol

Unit

v

125_C

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

V

OL

Maximum Low–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

3.0

4.5

6.0

0.26

0.26

0.26

0.33

0.33

0.33

0.40

0.40

0.40

I

in

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

4

40

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tf = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

f

max

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 3)

2.0

3.0

4.5

6.0

10
15
30
50

9
14
28
45

8
12
25
40

MHz

t

PLH

,

t

PHL

Maximum Propagation Delay, Clock A to QA

(Figures 1 and 3)

2.0

3.0

4.5

6.0

70
40
20
16

80
45
25
21

90
50
30
27

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Clock A to QC
(QA connected to Clock B)

(Figures 1 and 3)

2.0

3.0

4.5

6.0

200
160

35
30

250
185

45
40

300
210

60
50

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Clock B to QB

(Figures 1 and 3)

2.0

3.0

4.5

6.0

70
40
20
16

80
45
25
21

90
50
30
27

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Clock B to QC

(Figures 1 and 3)

2.0

3.0

4.5

6.0

90
56
32
25

105

70
38
31

180
100

45
40

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Clock B to QD

(Figures 1 and 3)

2.0

3.0

4.5

6.0

70
40
20
16

80
45
25
21

90
50
30
27

ns

t

PHL

Maximum Propagation Delay, Reset to any Q

(Figures 2 and 3)

2.0

3.0

4.5

6.0

80
48
28
21

95
65
32
25

110

75
40
30

ns

MC54/74HC390A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tf = tf = 6 ns)

Unit

Guaranteed Limit

V

CC

V

Parameter

Symbol

Unit

v

125_C

v

85_C

– 55 to

25_C

V

CC

V

Parameter

Symbol

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

2.0

3.0

4.5

6.0

75
27
15
13

95
32
19
15

110

36
22
19

ns

C

in

Maximum Input Capacitance

—

10

10

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Counter)*

35

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (Input t

r

= tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

t

rec

Minimum Recovery Time, Reset Inactive to Clock A or Clock B

(Figure 2)

2.0

3.0

4.5

6.0

25
15

5
5

30
20

6
5

40
30
10

7

ns

t

w

Minimum Pulse Width, Clock A, Clock B

(Figure 1)

2.0

3.0

4.5

6.0

75
27
15
13

95
32
19
15

110

36
22
19

ns

t

w

Minimum Pulse Width, Reset

(Figure 2)

2.0

3.0

4.5

6.0

75
27
15
13

95
32
19
15

110

36
22
19

ns

tf, t

f

Maximum Input Rise and Fall Times

(Figure 1)

2.0

3.0

4.5

6.0

1000

800
500
400

1000

800
500
400

1000

800
500
400

ns

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC390A

High–Speed CMOS Logic Data
DL129 — Rev 6

5 MOTOROLA

PIN DESCRIPTIONS

INPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)

Clock A is the clock input to the ÷ 2 counter; Clock B is the
clock input to the ÷ 5 counter. The internal flip–flops are
toggled by high–to–low transitions of the clock input.

CONTROL INPUTS
Reset (Pins 2, 14)

Asynchronous reset. A high at the Reset input prevents
counting, resets the internal flip–flops, and forces QA through
QD low.

OUTPUTS
QA (Pins 3, 13)

Output of the ÷ 2 counter.

QB, QC, QD (Pins 5, 6, 7, 9, 10, 11)

Outputs of the ÷ 5 counter. QD is the most significant bit.
QA is the least significant bit when the counter is connected
for BCD output as in Figure 4. QB is the least significant bit
when the counter is operating in the bi–quinary mode as in
Figure 5.

SWITCHING WAVEFORMS

Q

t

r

t

f

t

PLH

t

PHL

t

TLH

t

THL

V

CC

GND

CLOCK

10%

50%

90%

1/f

max

t

w

t

rec

RESET

Figure 1. Figure 2.

V

CC

GND

V

CC

GND

10%

50%

90%

Q

CLOCK

50%

50%

50%

t

PHL

t

w

10%

TEST CIRCUIT

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 3.

MC54/74HC390A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

6

C

D

R

Q
Q

0 1 2 3 4 5 6 7 8 9

EXPANDED LOGIC DIAGRAM

TIMING DIAGRAM

(QA Connected to Clock B)

Q

A

Q

B

Q

C

Q

D

CLOCK A

RESET

Q

A

Q

B

Q

C

Q

D

CLOCK A

CLOCK B

RESET

3, 13

5, 11

6, 10

7, 9

1, 15

4, 12

2, 14

C

D

R

Q
Q

C

D

R

Q
Q

C

DRQ

0 1 2 3 4 5 6

MC54/74HC390A

High–Speed CMOS Logic Data
DL129 — Rev 6

7 MOTOROLA

APPLICATIONS INFORMATION

Each half of the MC54/74HC390A has independent ÷ 2
and ÷ 5 sections (except for the Reset function). The ÷ 2 and
÷ 5 counters can be connected to give BCD or bi–quinary
(2–5) count sequences. If Output QA is connected to the
Clock B input (Figure 4), a decade divider with BCD output is
obtained. The function table for the BCD count sequence is
given in Table 1.

To obtain a bi–quinary count sequence, the input signals
connected to the Clock B input, and output QD is connected
to the Clock A input (Figure 5). QA provides a 50% duty cycle
output. T he bi–quinary count sequence function t able is
given in Table 2.

Table 1. BCD Count Sequence*

Output

Count

Q

D

Q

C

Q

B

Q

A

0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L
9 H L L H

*QA connected to Clock B input.

Table 2. Bi–Quinary Count Sequence**

Output

Count

Q

A

Q

D

Q

C

Q

B

0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
8 H L L L

9 H L L H
10 H L H L
11 H L H H
12 H H L L

**QD connected to Clock A input.

CONNECTION DIAGRAMS

1, 15

÷

2

COUNTER

CLOCK A

RESET

Figure 4. BCD Count Figure 5. Bi-Quinary Count

÷

2

COUNTER

÷

5

COUNTER

÷

5

COUNTER

CLOCK B

CLOCK A

RESET

CLOCK B

1, 15

Q

A

Q

B

Q

C

Q

D

3, 13

5, 11
6, 10

7, 9

4, 12

2, 14

Q

A

Q

B

Q

C

Q

D

3, 13

5, 11
6, 10

7, 9

4, 12

2, 14

MC54/74HC390A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

8

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

ISSUE V

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

19.05

6.10
—

0.39

1.40

0.21

3.18

19.93

7.49

5.08

0.50

1.65

0.38

4.31

0

°

0.51

15

°

1.01

1.27 BSC

2.54 BSC

7.62 BSC

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

0.750

0.240
—

0.015

0.055

0.008

0.125

0.785

0.295

0.200

0.020

0.065

0.015

0.170

0.050 BSC

0.100 BSC

0.300 BSC

A
B
C
D
E
F
G
J
K
L
M
N

0

°

0.020

15

°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.

1 8

916

–A

–

–B

–

C

K

N

G

E

F

D 16 PL

–T

–

SEATING

PLANE

M

L

J 16 PL

0.25 (0.010) T A

M

S

0.25 (0.010) T B

M

S

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

A
B
C
D
F
G
H

J
K
L
M
S

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50
0

°

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74
10

°

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295
0

°

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305
10

°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

B

1 8

916

F

H

G

D

16 PL

S

C

–T

–

SEATING
PLANE

K

J

M

L

T A0.25 (0.010)

M M

0.25 (0.010) T B A

M

S S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G

J
K
M
P
R

9.80

3.80

1.35

0.35

0.40

0.19

0.10
0

°

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

0.25
7

°

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004
0

°

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.009
7

°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

1

8

916

–A

–

–B

–

D 16 PL

K

C

G

–T

–

SEATING

PLANE

R X 45°

M

J

F

P 8 PL

0.25 (0.010) B

M M

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

MC54/74HC390A

High–Speed CMOS Logic Data
DL129 — Rev 6

9 MOTOROLA

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011

J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.

_ _ _ _

SECTION N–N

SEATING
PLANE

IDENT.

PIN 1

1

8

16

9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

ÉÉ

ÉÉ

ÉÉ

DETAIL E

F

M

L

2X L/2

–U–

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V

S

T

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

N

How to reach us:
USA/EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,

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INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

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MC54/74HC390A/D

*MC54/74HC390A/D*

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