Motorola MC74HC365AD, MC74HC365ADT, MC74HC365AN Datasheet



SEMICONDUCTOR TECHNICAL DATA

1

REV 0.1

 Motorola, Inc. 1997

3/97

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High–Performance Silicon–Gate CMOS

The MC74HC365A is identical in pinout to the LS365. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.

This device is a high–speed hex buffer with 3–state outputs and two
common active–low Output Enables. When either of the enables is high, the
buffer outputs are placed into high–impedance states. The HC365A has
noninverting outputs.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 90 FETs or 22.5 Equivalent Gates

LOGIC DIAGRAM

A3

A4

A5

A0

A1

A2

2

4

6

10

12

14

OUTPUT ENABLE 1

1

15

PIN 16 = V

CC

PIN 8 = GND

OUTPUT ENABLE 2

Y3

Y4

Y5

Y0

Y1

Y2

3

5

7

9

11

13

This document contains information on a new product. Specifications and information herein are subject to
change without notice.



PIN ASSIGNMENT

FUNCTION TABLE

X = don’t care
Z = high impedance

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

A4

Y5

A5

OUTPUT
ENABLE 2

V

CC

Y3

A3

Y4

A1

Y0

A0

OUTPUT

ENABLE 1

GND

Y2

A2

Y1

Inputs Output

Enable1Enable

2AY

L

L
H
X

L
L
X

H

L
H
X
X

L
H
Z
Z

D SUFFIX

SOIC PACKAGE

16–LEAD

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

16–LEAD

CASE 648–08

ORDERING INFORMATION

MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

Plastic
SOIC
TSSOP

DT SUFFIX

TSSOP PACKAGE

16–LEAD

CASE 948F–01

MC74HC365A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

Î

Î

Î

P

D

ОООООООООООО

Î

ОООООООООООО

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎ

Î

ÎÎÎÎ

750
500
450

Î

Î

Î

mW

Î

T

stg

ОООООООООООО

Storage Temperature

ÎÎÎÎ

– 65 to + 150

Î

_

C

Î

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

ÎÎÎÎ

Î

260

Î

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur .

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

ÎÎ

Î

tr, t

f

ОООООООООООО

Î

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

Î

Î

0
0
0

Î

Î

1000

500
400

Î

Î

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Î

Symbol

ООООООО

Î

Parameter

ООООООО

Î

Test Conditions

ÎÎ

Î

V

CC

V

ÎÎ

– 55 to

25_C

ÎÎ

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎ

Î

ÎÎ

Î

ÎÎ

V

IH

ООООООО

Î

ООООООО

Î

ООООООО

Minimum High–Level Input
Voltage

ООООООО

Î

ООООООО

Î

ООООООО

V

out

= VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

ÎÎ

1.5

2.1

3.15

4.2

ÎÎ

Î

ÎÎ

Î

ÎÎ

1.5

2.1

3.15

4.2

ÎÎ

Î

ÎÎ

Î

ÎÎ

1.5

2.1

3.15

4.2

Î

Î

Î

Î

Î

V

ÎÎ

Î

ÎÎ

Î

V

IL

ООООООО

Î

ООООООО

Î

Maximum Low–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

0.50

0.90

1.35

1.80

ÎÎ

Î

ÎÎ

Î

0.50

0.90

1.35

1.80

ÎÎ

Î

ÎÎ

Î

0.50

0.90

1.35

1.80

Î

Î

Î

Î

V

ÎÎ

Î

ÎÎ

Î

V

OH

ООООООО

Î

ООООООО

Î

Minimum High–Level Output
Voltage

ООООООО

Î

ООООООО

Î

Vin = V

IH

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

ÎÎ

1.9

4.4

5.9

ÎÎ

Î

ÎÎ

Î

1.9

4.4

5.9

ÎÎ

Î

ÎÎ

Î

1.9

4.4

5.9

Î

Î

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = V

IH

|I

out

| v 3.6 mA

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

2.48

3.98

5.48

ÎÎ

Î

2.34

3.84

5.34

ÎÎ

Î

2.20

3.70

5.20

Î

Î

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HC365A

High–Speed CMOS Logic Data
DL129 — Rev 6

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Unit

Guaranteed Limit

V

CC

V

Test Conditions

Parameter

Symbol

Unit

v

125_C

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

ÎÎ

Î

V

OL

ООООООО

Î

Maximum Low–Level Output
Voltage

ООООООО

Î

Vin = V

IL

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

0.1

0.1

0.1

ÎÎ

Î

0.1

0.1

0.1

ÎÎ

Î

0.1

0.1

0.1

Î

Î

V

ÎÎ

Î

ÎÎ

ООООООО

Î

ООООООО

ООООООО

Î

ООООООО

Vin = V

IL

|I

out

| v 3.6 mA

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

ÎÎ

Î

ÎÎ

3.0

4.5

6.0

ÎÎ

ÎÎ

0.26

0.26

0.26

ÎÎ

Î

ÎÎ

0.33

0.33

0.33

ÎÎ

Î

ÎÎ

0.40

0.40

0.40

Î

Î

Î

ÎÎ

I

in

ООООООО

Maximum Input Leakage Current

ООООООО

Vin = VCC or GND

ÎÎ

6.0

ÎÎ

± 0.1

ÎÎ

± 1.0

ÎÎ

± 1.0

Î

µA

ÎÎ

Î

ÎÎ

Î

I

OZ

ООООООО

Î

ООООООО

Î

Maximum Three–State
Leakage Current

ООООООО

Î

ООООООО

Î

Output in High–Impedance State
Vin = VIL or V

IH

V

out

= VCC or GND

ÎÎ

Î

ÎÎ

Î

6.0

ÎÎ

ÎÎ

± 0.5

ÎÎ

Î

ÎÎ

Î

± 5.0

ÎÎ

Î

ÎÎ

Î

± 10

Î

Î

Î

Î

µA

ÎÎ

I

CC

ООООООО

Maximum Quiescent Supply
Current (per Package)

ООООООО

Vin = VCC or GND
I

out

= 0 µA

ÎÎ

6.0

ÎÎ4ÎÎ40ÎÎ

160

Î

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

ÎÎ

Î

Symbol

ООООООООООООООО

Î

Parameter

ÎÎ

Î

V

CC

V

ÎÎ

– 55 to

25_C

ÎÎ

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎ

Î

ÎÎ

Î

t

PLH

,

t

PHL

ООООООООООООООО

Î

ООООООООООООООО

Î

Maximum Propagation Delay, Input A to Output Y

(Figures 1 and 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

120

60
24
20

ÎÎ

Î

ÎÎ

Î

150

75
30
26

ÎÎ

Î

ÎÎ

Î

180

90
36
31

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

ÎÎ

t

PLZ

,

t

PHZ

ООООООООООООООО

Î

ООООООООООООООО

Î

ООООООООООООООО

Maximum Propagation Delay, Output Enable to Output Y

(Figures 2 and 4)

ÎÎ

Î

ÎÎ

Î

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

ÎÎ

220
110

44
37

ÎÎ

Î

ÎÎ

Î

ÎÎ

275
140

55
47

ÎÎ

Î

ÎÎ

Î

ÎÎ

330
170

66
56

Î

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

PZL

,

t

PZH

ООООООООООООООО

Î

ООООООООООООООО

Î

Maximum Propagation Delay, Output Enable to Output Y

(Figures 2 and 4)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

220
110

44
37

ÎÎ

Î

ÎÎ

Î

275
140

55
47

ÎÎ

Î

ÎÎ

Î

330
170

66
56

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

TLH

,

t

THL

ООООООООООООООО

Î

ООООООООООООООО

Î

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

60
22
12
10

ÎÎ

Î

ÎÎ

Î

75
28
15
13

ÎÎ

Î

ÎÎ

Î

90
34
18
15

Î

Î

Î

Î

ns

C

in

Maximum Input Capacitance

—

10

10

10

pF

ÎÎ

Î

C

out

ООООООООООООООО

Î

Maximum Three–State Output Capacitance
(Output in High–Impedance State)

ÎÎ

Î

—

ÎÎ15ÎÎ

Î

15

ÎÎ

Î

15

Î

Î

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Buffer)*

35

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

MC74HC365A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

SWITCHING W AVEFORMS

V

CC

GND

t

f

t

r

INPUT A

OUTPUT Y

10%

50%

90%

10%

50%

90%

t

TLH

t

PLH

t

PHL

t

THL

OUTPUT ENABLE

OUTPUT Y

OUTPUT Y

50%

50%

50%

90%

10%

t

PZL

t

PLZ

t

PZHtPHZ

V

CC

GND
HIGH

IMPEDANCE
V

OL

V

OH

HIGH
IMPEDANCE

Figure 1. Figure 2.

TEST CIRCUITS

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

CONNECT TO VCC WHEN
TESTING t

PLZ

AND t

PZL

.
CONNECT TO GND WHEN
TESTING t

PHZ

AND t

PZH

.

1 k

Ω

Figure 3. Figure 4.

INPUT A

OUTPUT ENABLE 1
OUTPUT ENABLE 2

V

CC

TO OTHER

FIVE BUFFERS

Y

LOGIC DETAIL

ONE OF 6
BUFFERS

MC74HC365A

High–Speed CMOS Logic Data
DL129 — Rev 6

5 MOTOROLA

OUTLINE DIMENSIONS

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

A
B
C
D
F
G
H
J
K
L
M
S

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50
0

°

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74
10

°

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295
0

°

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305
10

°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

B

18

916

F

H

G

D

16 PL

S

C

–T

–

SEATING
PLANE

K

J

M

L

TA0.25 (0.010)

M M

0.25 (0.010) T B A

M

S S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G
J

K
M
P
R

9.80

3.80

1.35

0.35

0.40

0.19

0.10
0

°

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

0.25
7

°

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004
0

°

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.009
7

°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

1

8

916

–A

–

–B

–

D 16 PL

K

C

G

–T

–

SEATING

PLANE

R X 45°

M

J

F

P 8 PL

0.25 (0.010) B

M M

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

MC74HC365A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

6

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

ÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006

F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011

J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MA TERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.

____

SECTION N–N

SEATING
PLANE

IDENT.

PIN 1

1

8

16

9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

DETAIL E

F

M

L

2X L/2

–U–

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V

S

T

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

N

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USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,

P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315
Mfax: [e-mail] – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

INTERNET: http://www.mot.com/SPS/

MC74HC365A/D

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