MOTOROLA MC74HC273AFR2, MC74HC273AH, MC74HC273AN, MC74HC273AFEL, MC74HC273AFL1 Datasheet
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Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 8
1 Publication Order Number:
MC74HCT273A/D
MC74HCT273A
Octal D Flip-Flop with
Common Clock and Reset
with LSTTL-Compatible
Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT273A may be used as a level converter for
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.
The HCT273A is identical in pinout to the LS273.
This device consists of eight D flip–flops with common Clock and
Reset inputs. Each flip–flop is loaded with a low–to–high transition of
the Clock input. Reset is asynchronous and active low.
• Output Drive Capability: 10 LSTTL Loads
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 284 FETs or 71 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0
11
CLOCK
D1
D2
D3
D4
D5
D6
D7
18
17
14
13
8
7
4
3
1
RESET
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
16
15
12
9
6
5
2
PIN 20 = V
CC
PIN 10 = GND
NONINVERTING
OUTPUTS
FUNCTION TABLE
Inputs Output
Reset Clock D Q
LXX L
HHH
HLL
H L X No Change
H X No Change
X = Don’t Care
Z = High Impedance
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MARKING
DIAGRAMS
1
20
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
SOIC WIDE–20
DW SUFFIX
CASE 751D
HCT273A
AWLYYWW
PDIP–20
N SUFFIX
CASE 738
1
20
MC74HCT273AN
AWLYYWW
1
20
1
20
Device Package Shipping
ORDERING INFORMATION
MC74HCT273AN PDIP–20 1440 / Box
MC74HCT273ADW SOIC–WIDE
38 / Rail
MC74HCT273ADWR2 SOIC–WIDE 1000 / Reel
PIN ASSIGNMENT
Q2
D1
D0
Q0
RESET
GND
Q3
D3
D2
Q1 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q6
D6
D7
Q7
V
CC
CLOCK
Q4
D4
D5
Q5
MC74HCT273A
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2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
ÎÎ
Î
P
D
ОООООООООООО
Î
Power Dissipation in Still Air Plastic DIP†
SOIC Package†
ÎÎÎ
Î
750
500
Î
Î
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or Plastic DIP)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
ÎÎ
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
4.5
ÎÎ
5.5
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
ÎÎ
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
ÎÎ
+ 125
_
C
tr, t
f
Input Rise and Fall Time (Figure 1)
0
ÎÎ
500
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
ÎÎ
Î
Symbol
ООООООО
Î
Parameter
ООООООО
Î
Test Conditions
ÎÎ
Î
V
CC
V
ÎÎ
Î
– 55 to
25_C
ÎÎÎ
Î
Î
Î
v
85_C
ÎÎ
Î
v
125_C
Î
Î
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
4.5
5.5
2.0
2.0
ÎÎÎ
2.0
2.0
2.0
2.0
V
ÎÎ
Î
V
IL
ООООООО
Î
Maximum Low–Level Input
Voltage
ООООООО
Î
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
ÎÎ
Î
4.5
5.5
ÎÎ
Î
0.8
0.8
ÎÎÎ
Î
Î
Î
0.8
0.8
ÎÎ
Î
0.8
0.8
Î
Î
V
ÎÎ
Î
V
OH
ООООООО
Î
Minimum High–Level Output
Voltage
ООООООО
Î
Vin = VIH or V
IL
|I
out
| v 20 µA
ÎÎ
Î
4.5
5.5
ÎÎ
Î
4.4
5.4
ÎÎÎ
Î
Î
Î
4.4
5.4
ÎÎ
Î
4.4
5.4
Î
Î
V
Vin = VIH or V
IL
|I
out
| v 4.0 mA
4.5
3.98
ÎÎÎ
3.84
3.7
ÎÎ
Î
V
OL
ООООООО
Î
Maximum Low–Level Output
Voltage
ООООООО
Î
Vin = VIH or V
IL
|I
out
| v 20 µA
ÎÎ
Î
4.5
5.5
ÎÎ
Î
0.1
0.1
ÎÎÎ
Î
Î
Î
0.1
0.1
ÎÎ
Î
0.1
0.1
Î
Î
V
ÎÎÎОООООООÎООООООО
Î
Vin = VIH or V
IL
|I
out
| v 4.0 mA
ÎÎ
Î
4.5
ÎÎ
Î
0.26
ÎÎÎ
Î
Î
Î
0.33
ÎÎ
Î
0.4
Î
Î
I
in
Maximum Input Leakage
Current
Vin = VCC or GND
5.5
± 0.1
ÎÎÎ
± 1.0
± 1.0
µA
ÎÎ
Î
I
CC
ООООООО
Î
Maximum Quiescent Supply
Current (per Package)
ООООООО
Î
Vin = VCC or GND
I
out
= 0 µA
ÎÎ
Î
5.5
ÎÎ
Î
4.0
ÎÎÎ
Î
Î
Î
40
ÎÎ
Î
160
Î
Î
µA
∆I
CC
Additional Quiescent Supply
Vin = 2.4 V, Any One Input
p
≥ –55_C
ОООООО
25_C to 125_C
ÎÎÎООООООО
Î
Current
ООООООО
Î
V
i
n
=
V
CC
or
GND, Other In uts
l
out
= 0 µA
ÎÎ
Î
5.5
ÎÎ
Î
2.9
ОООООО
Î
ÎÎÎÎ
Î
2.4
Î
Î
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HCT273A
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AC ELECTRICAL CHARACTERISTICS (V
CC
= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
ÎÎÎ
Î
Symbol
ОООООООООООООО
Î
Parameter
ÎÎ
Î
Fig.
ÎÎ
Î
– 55 to
25_C
ÎÎÎ
Î
Î
Î
v
85_C
ÎÎ
Î
v
125_C
Î
Î
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
1, 4
30
ÎÎÎ
24
20
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q
1, 4
25
ÎÎÎ
28
35
ns
t
PHL
Maximum Propagation Delay, Reset to Q
2, 4
25
ÎÎÎ
28
35
ns
ÎÎÎ
Î
t
TLH
,
t
THL
ОООООООООООООО
Î
Maximum Output Transition Time, Any Output
ÎÎ
Î
1, 5
ÎÎ
Î
18
ÎÎÎ
Î
Î
Î
20
ÎÎ
Î
22
Î
Î
ns
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Gate)*
30
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (V
CC
= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to 25_C
v
85_C
v
125_C
Symbol
Parameter
Fig.
Min
Max
Min
Max
Min
Max
Unit
t
su
Minimum Setup Time, Data to Clock
3
10
12
15
ns
t
h
Minimum Hold Time, Clock to Data
3
3.0
3.0
3.0
ns
t
rec
Minimum Recovery Time, Set or Reset Inactive to Clock
2
5.0
5.0
5.0
ns
t
w
Minimum Pulse Width, Clock
1
12
15
18
ns
t
w
Minimum Pulse Width, Set or Reset
2
12
15
18
ns
tr, tfMaximum Input Rise and Fall Times
1
500
500
500
ns
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