Motorola MC54HC273AJ, MC74HC273AN, MC74HC273ADW, MC74HC273ADT Datasheet



ОООООООООО

Î

ОООООООООО

SEMICONDUCTOR TECHNICAL DATA

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High–Performance Silicon–Gate CMOS

The MC54/74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of eight D flip–flops with common Clock and Reset inputs. Each flip–flop is loaded with a low–to–high transition of the Clock input. Reset is asynchronous and active low.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 264 FETs or 66 Equivalent Gates

LOGIC DIAGRAM

2

Q0

5

Q1

6

Q2

9

Q3

12 15 16 19

NONINVERTING

Q4 Q5 Q6 Q7

PIN 20 = V PIN 10 = GND

OUTPUTS

CC

DATA

INPUTS

D0 D1 D2 D3 D4 D5 D6 D7

CLOCK

RESET

3 4 7 8 13 14 17 18

11

1



J SUFFIX

20

1

20

1

20

1

20

1

ORDERING INFORMATION

MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW MC74HCXXXADT

PIN ASSIGNMENT

RESET

Q0 D0 D1

Q1 5 Q2 D2 D3 Q3

GND

CERAMIC PACKAGE

CASE 732–03

PLASTIC PACKAGE

CASE 738–03

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

TSSOP PACKAGE

CASE 948E–02

1 2

3 4

20 19

18 17

16 6 7 8 9 10

15

14

13

12

11

N SUFFIX

DT SUFFIX

Ceramic Plastic SOIC TSSOP

V

CC Q7 D7

D6 Q6

Q5 D5 D4 Q4 CLOCK

Design Criteria

Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation

ООООООООО

Speed Power Product

* Equivalent to a two–input NAND gate.

2/97

 Motorola, Inc. 1997

3–1

Value

66

1.5

5.0

ÎÎ

.0075

Units

ea ns

µW

Î

pJ

FUNCTION TABLE

Inputs Output

Reset Clock D Q

LXX L HHH HLL H L X No Change H X No Change

REV 7

MC54/74HC273A

Î

MAXIMUM RATINGS*

Symbol

V

Î

T

Î

DC Supply Voltage (Referenced to GND)

CC

V

DC Input Voltage (Referenced to GND)

in

DC Output Voltage (Referenced to GND)

out

I

DC Input Current, per Pin

in

I

DC Output Current, per Pin

out

I

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air, Plastic or Ceramic DIP†

D

ОООООООООООО

Storage Temperature

stg

ОООООООООООО

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

ОООООООООООО

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Parameter

SOIC Package†

TSSOP Package†

Plastic DIP, SOIC or TSSOP Package

(Ceramic DIP)

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

± 20 ± 25 ± 50

750 500

ÎÎÎÎ

450

ÎÎÎÎ

– 65 to + 150

ÎÎÎÎ

260 300

ÎÎÎÎ

Unit

V V

V mA mA mA

mW

Î

_

C

Î

_

C

Î

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

should be constrained to the

out

range GND v (Vin or V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

) v VCC.

out

RECOMMENDED OPERATING CONDITIONS

Symbol

V

CC

Vin, V

T

A

tr, t

ÎÎ

DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND)

out

Operating Temperature, All Package Types Input Rise and Fall Time VCC = 2.0 V

f

(Figure 1) VCC = 4.5 V

ОООООООООООО

Parameter

VCC = 6.0 V

Min

2.0 0

– 55

0 0

Î

0

Î

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Symbol

ÎÎ

V

IH

ÎÎ

V

IL

ÎÎ

V

OH

ÎÎ

ООООООО

Minimum High–Level Input

ООООООО

Voltage

ООООООО

Maximum Low–Level Input

ООООООО

Voltage

ООООООО

Minimum High–Level Output Voltage

ООООООО

Parameter

Test Conditions

ООООООО

V

= VCC – 0.1 V

out

ООООООО

|I

| v 20 µA

out

ООООООО

V

= 0.1 V

out

ООООООО

|I

| v 20 µA

out

ООООООО

Vin = V

IH

|I

| v 20 µA

out

ООООООО

Vin = V

IH

ООООООО

|I

| v 2.4 mA

out

|I

| v 6.0 mA

out

|I

| v 7.8 mA

out

Max

6.0

V

CC

+ 125

1000

500

Î

400

Î

Unit

V V

_

C

ns

Î

V

CC

V

ÎÎ

2.0

ÎÎ

3.0

4.5

ÎÎ

6.0

2.0

ÎÎ

3.0

4.5

ÎÎ

6.0

2.0

4.5

ÎÎ

6.0

3.0

ÎÎ

4.5

6.0

ÎÎ

Guaranteed Limit

– 55 to

25_C

ÎÎ

1.5

2.1

3.15

ÎÎ

4.2

0.5

ÎÎ

0.9

1.35

1.8

ÎÎ

1.9

4.4

ÎÎ

5.9

ÎÎ

2.48

ÎÎ

3.98

5.48

ÎÎ

v

85_C

1.5

2.1

3.15

4.2

0.5

0.9

1.35

1.8

1.9

4.4

5.9

2.34

3.84

5.34

v

125_C

ÎÎ

1.5

ÎÎ

2.1

3.15

ÎÎ

4.2

0.5

ÎÎ

0.9

1.35

ÎÎ

1.8

1.9

4.4

ÎÎ

5.9

2.2

ÎÎ

3.7

5.2

ÎÎ

Unit

Î

V

MOTOROLA High–Speed CMOS Logic Data

3–2

DL129 — Rev 6

MC54/74HC273A

Î

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

V

Symbol

V

OL

ÎÎ

ÎÎÎОООООООÎООООООО

I

in

I

OZ

ÎÎ

I

CC

ÎÎ

Maximum Low–Level Output Voltage

ООООООО

Maximum Input Leakage Current Maximum Three–State Leakage

Current

ООООООО

Maximum Quiescent Supply Current (per Package)

ООООООО

Parameter

Output in High–Impedance State

Test Conditions

Vin = V

IL

|I

| v 20 µA

out

ООООООО

Vin = V

IL

|I

| v 2.4 mA

out

|I

| v 6.0 mA

out

|I

| v 7.8 mA

out

Vin = VCC or GND

Vin = VIL or V

ООООООО

V

= VCC or GND

out

IH

Vin = VCC or GND I

= 0 µA

out

ООООООО

CC

2.0

4.5

6.0

ÎÎ

3.0

4.5

ÎÎ

6.0

ÎÎ

6.0

ÎÎ

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

– 55 to

V

25_C

0.1

ÎÎ

0.26

ÎÎ

0.26

± 0.1 ± 0.5

ÎÎ

4.0

ÎÎ

v

85_C

0.1

ÎÎ

0.33

ÎÎ

0.33

± 1.0 ± 5.0

ÎÎ

40

ÎÎ

v

125_C

0.1

ÎÎ

0.4

ÎÎ

0.4

± 1.0

± 10

ÎÎ

160

ÎÎ

Unit

V

Î

µA µA

Î

µA

Î

AC ELECTRICAL CHARACTERISTICS (C

= 50 pF, Input tr = tf = 6.0 ns)

L

Guaranteed Limit

Symbol

ÎÎ

f

max

ÎÎ

t

PLH

t

PHL

ÎÎ

t

PHL

ÎÎ

t

TLH

t

THL

ÎÎ

C

in

ÎÎ

V

ООООООООООООООО

Parameter

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

ООООООООООООООО

Maximum Propagation Delay, Clock to Q

(Figures 1 and 4)

ООООООООООООООО

Maximum Propagation Delay, Reset to Q

(Figures 2 and 4)

ООООООООООООООО

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

ООООООООООООООО

Maximum Input Capacitance

ОООООООООООООООООО

CC

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

– 55 to

V

25_C

ÎÎ

6.0 15

ÎÎ

30 35

ÎÎ

145

90

ÎÎ

29 25

ÎÎ

145

90

ÎÎ

29 25

ÎÎ

75 27

ÎÎ

15 13

ÎÎ

ÎÎ10ÎÎ

v

85_C

ÎÎ

5.0 10

ÎÎ

24 28

ÎÎ

180 120

ÎÎ

36 31

ÎÎ

180 120

ÎÎ

36 31

ÎÎ

95 32

ÎÎ

19 16

ÎÎ

10

v

125_C

ÎÎ

4.0

8.0

ÎÎ

20 24

ÎÎ

220 140

ÎÎ

44 38

ÎÎ

220 140

ÎÎ

44 38

ÎÎ

110

36

ÎÎ

22 19

ÎÎ

10

ÎÎ

Unit

Î

MHz

Î

pF

Î

ns

NOTE:For propagation delays with loads other than 50 pF , and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

*Used to determine the no–load dynamic power consumption: PD = CPD V

Motorola High–Speed CMOS Data Book (DL129/D).

Power Dissipation Capacitance (Per Enabled Output)*

48

2

f + ICC VCC. For load considerations, see Chapter 2 of the

CC

pF

High–Speed CMOS Logic Data DL129 — Rev 6

3–3 MOTOROLA

MC54/74HC273A

V

CC

Î

TIMING REQUIREMENTS (C

Symbol

t

su

Î

t

h

Î

t

rec

Î

t

w

Î

t

w

Î

tr, t

f

Î

Minimum Setup Time, Data to Clock

ООООООООООО

Minimum Hold Time, Clock to Data

ООООООООООО

Minimum Recovery Time, Reset Inactive to Clock

ООООООООООО

Minimum Pulse Width, Clock

ООООООООООО

Minimum Pulse Width, Reset

ООООООООООО

Maximum Input Rise and Fall Times

ООООООООООО

Parameter

= 50 pF, Input tr = tf = 6.0 ns)

L

Fig.

3

ÎÎ

3

ÎÎ

2

ÎÎ

1

ÎÎ

2

ÎÎ

1

ÎÎ

V

Volts

2.0

3.0

ÎÎ

4.5

ÎÎ

6.0

2.0

3.0

ÎÎ

4.5

ÎÎ

6.0

2.0

3.0

ÎÎ

4.5

ÎÎ

6.0

2.0

3.0

ÎÎ

4.5

ÎÎ

6.0

2.0

3.0

ÎÎ

4.5

ÎÎ

6.0

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

– 55 to 25_C

Min

Max

60 23

Î

12

Î

10

Î

3.0

Î

3.0

Î

3.0

Î

5.0

Î

5.0

Î

5.0

Î

60 23

Î

12

Î

10

Î

60 23

Î

12

Î

10

Î

1000

800

Î

500 400

Î

Guaranteed Limit

v

85_C

Min

Max

75 27

Î

15

Î

13

Î

3.0

Î

3.0

Î

3.0

Î

5.0

Î

5.0

Î

5.0

Î

75 27

Î

15

Î

13

Î

75 27

Î

15

Î

13

Î

1000

800

Î

500 400

Î

v

Min

90 32

Î

18

Î

15

3.0

Î

3.0

Î

3.0

5.0

Î

5.0

Î

5.0 90

32

Î

18

Î

15 90

32

Î

18

Î

15

Î

125_C

Max

ÎÎ

1000

ÎÎ

800 500 400

Unit

ns

Î

ns

Î

ns

Î

ns

Î

ns

Î

ns

Î

MOTOROLA High–Speed CMOS Logic Data

3–4

DL129 — Rev 6

SWITCHING WAVEFORMS

MC54/74HC273A

CLOCK

Q

DATA

CLOCK

90%

50%

10%

50%

10%

t

90%

50%

r

t

w

1/f

t

PLH

t

TLH

Figure 1.

t

su

max

VALID

t

50%

t

f

PHL

t

h

t

THL

V

CC

GND

V

CC

GND

V

CC

GND

RESET

Q

CLOCK

t

w

50%

t

PHL

50%

t

rec

50%

Figure 2.

EXPANDED LOGIC DIAGRAM

V

CC

GND

V

CC

GND

Figure 3.

TEST POINT

OUTPUT

DEVICE UNDER

TEST

*Includes all probe and jig capacitance

CL*

Figure 4. T est Circuit

DATA

INPUTS

D0

D1

D2

D3

D4

D5

D6

D7

3

4

7

8

13

14

17

18

11

C

Q

D

R

C

Q

D

R

C

Q

D

R

C

Q

D

R

C

Q

D

R

C

Q

D

R

C

Q

D

R

C

Q

D

R

2

5

6

9

12

15

16

19

Q0

Q1

Q2

Q3

NONINVERTING

OUTPUTS

Q4

Q5

Q6

Q7

High–Speed CMOS Logic Data DL129 — Rev 6

1

3–5 MOTOROLA

MC54/74HC273A

OUTLINE DIMENSIONS

–T–

SEATING PLANE

CERAMIC PACKAGE

20

110

A

F

H

D

SEATING PLANE

–A–

20

1

E

FG

11

B

C

K

G

D

20 PL

N

11

J

B

10

K

N

0.25 (0.010) T

M

PLASTIC PACKAGE

J SUFFIX

CASE 732–03

ISSUE E

L

M

N SUFFIX

CASE 738–03

ISSUE E

C

M

A

L

J

20 PL

0.25 (0.010) T

NOTES:

1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

3. DIMENSIONS A AND B INCLUDE MENISCUS.

DIM MIN MAX MIN MAX

A 23.88 25.15 0.940 0.990 B 6.60 7.49 0.260 0.295 C 3.81 5.08 0.150 0.200 D 0.38 0.56 0.015 0.022 F 1.40 1.65 0.055 0.065 G 2.54 BSC 0.100 BSC H 0.51 1.27 0.020 0.050 J 0.20 0.30 0.008 0.012 K 3.18 4.06 0.125 0.160 L 7.62 BSC 0.300 BSC M 0 15 0 15

____

N 0.25 1.02 0.010 0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

DIM MIN MAX MIN MAX

A 25.66 27.171.010 1.070 B 6.10 6.600.240 0.260 C 3.81 4.570.150 0.180 D 0.39 0.550.015 0.022

M

B

E F G 2.54 BSC0.100 BSC J 0.21 0.380.008 0.015 K 2.80 3.550.110 0.140 L 7.62 BSC0.300 BSC

M

M 0 15 0 15 N 0.51 1.010.020 0.040

INCHESMILLIMETERS

MILLIMETERSINCHES

1.27 BSC0.050 BSC

1.27 1.770.050 0.070

____

DW SUFFIX

–A–

20

11

–B–

1

10

D20X

0.010 (0.25) B

M

S

A

T

S

PLASTIC SOIC PACKAGE

CASE 751D–04

ISSUE E

P10X

M

0.010 (0.25)

B

J

F

R

X 45

_

C

SEATING

–T–

18X

G

K

PLANE

MOTOROLA High–Speed CMOS Logic Data

M

3–6

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009

M 0 7 0 7

__

P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029

INCHESMILLIMETERS

__

DL129 — Rev 6

MC54/74HC273A

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948E–02

ISSUE A

20X REFK

S

U0.15 (0.006) T

0.10 (0.004) V

M

S

U

T

S

K

2X

L/2

L

PIN 1 IDENT

110

1120

B

JJ1

–U–

N

S

U0.15 (0.006) T

A

K1

SECTION N–N

0.25 (0.010)

M

–V–

N

F

DETAIL E

C

G

H

DETAIL E

0.100 (0.004)

SEATING

–T–

PLANE

D

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.

INCHES

6.60 0.260

–W–

MILLIMETERS

DIMAMIN MAX MIN MAX

6.40 0.252

B 4.30 4.50 0.169 0.177 C 1.20 0.047

––– –––

D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030

G 0.65 BSC 0.026 BSC

H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

____

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◊

High–Speed CMOS Logic Data

3–7 MOTOROLA

Mfax is a trademark of Motorola, Inc.

MC74HC273A/D

DL129 — Rev 6

Motorola MC54HC273AJ, MC74HC273AN, MC74HC273ADW, MC74HC273ADT Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual