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MC74HC174AFL1
Datasheet (MOTOROLA)
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Datasheet MC74HC174AFR2, MC74HC174AFEL, MC74HC174AFL1, MC74HC174AFL2, MC74HC174ADTR2 Datasheet (MOTOROLA)

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Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 7
1 Publication Order Number:
MC74HC174A/D
MC74HC174A
Hex D Flip-Flop with Common Clock and Reset
High–Performance Silicon–Gate CMOS
This device consists of six D flip–flops with common Clock and Reset inputs. Each flip–flop is loaded with a low–to–high transition of the Clock input. Reset is asynchronous and active–low.
• Output Drive Capability: 10 LSTTL Loads
• TTL NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 162 FETs or 40.5 Equivalent Gates
LOGIC DIAGRAM
PIN 16 = V
CC
PIN 8 = GND
3 4
6 11 13 14
2 5
7 10 12 15
D0 D1 D2 D3 D4 D5
Q0 Q1
Q2 Q3 Q4 Q5
CLOCK
9
RESET
1
DATA
INPUTS
NONINVERTING
OUTPUTS
FUNCTION TABLE
Inputs Output
Reset Clock D Q
LXX L HHH HLL H L X No Change H X No Change
ООООООООО
Design Criteria
Value
Units
ООООООООО
Î
ООООООО
Î
Internal Gate Count*
Î
Î
40.5
Î
Î
ea.
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
µW
Speed Power Product
.0075
pJ
*Equivalent to a two–input NAND gate.
SO–16
D SUFFIX
CASE 751B
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1
16
PDIP–16 N SUFFIX CASE 648
1
16
MARKING
DIAGRAMS
1
16
MC74HC174AN
AWLYYWW
1
16
HC174A
AWLYWW
A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week
Device Package Shipping
ORDERING INFORMATION
MC74HC174AN PDIP–16 2000 / Box MC74HC174AD SOIC–16
48 / Rail
MC74HC174ADR2 SOIC–16 2500 / Reel
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Q4
D4
D5
Q5
V
CC
CLOCK
Q3
D3
D1
D0
Q0
RESET
GND
Q2
D2
Q1
MC74HC174A
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2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
out
DC Output Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
P
D
Power Dissipation in Still Air, Plastic DIP†
SOIC Package†
750 500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
ÎÎ
Î
T
L
ОООООООООООО
Î
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
ÎÎÎ
Î
260
Î
Î
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
ÎÎ
Î
tr, t
f
ООООООООООООО
Î
Input Rise and Fall Time (Figure 1) VCC = 2.0 V
VCC = 4.5 V VCC = 6.0 V
Î
Î
0 0 0
1000
500 400
Î
Î
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
ÎÎ
Î
Symbol
ОООООООО
Î
Parameter
ОООООО
Î
Test Conditions
ÎÎ
Î
V
CC V
ÎÎ
Î
– 55 to
25_C
Î
Î
v
85_C
ÎÎ
Î
v
125_C
Î
Î
Unit
ÎÎ
Î
ÎÎ
Î
V
IH
ОООООООО
Î
ОООООООО
Î
Minimum High–Level Input Voltage
ОООООО
Î
ОООООО
Î
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
ÎÎ
Î
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
Î
ÎÎ
Î
1.5
3.15
4.2
Î
Î
Î
Î
1.5
3.15
4.2
ÎÎ
Î
ÎÎ
Î
1.5
3.15
4.2
Î
Î
Î
Î
V
ÎÎ
Î
V
IL
ОООООООО
Î
Maximum Low–Level Input Voltage
ОООООО
Î
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
Î
0.5
1.35
1.8
Î
Î
0.5
1.35
1.8
ÎÎ
Î
0.5
1.35
1.8
Î
Î
V
ÎÎ
Î
V
OH
ОООООООО
Î
Minimum High–Level Output Voltage
ОООООО
Î
Vin = VIH or V
IL
|I
out
| v 20 µA
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
Î
1.9
4.4
5.9
Î
Î
1.9
4.4
5.9
ÎÎ
Î
1.9
4.4
5.9
Î
Î
V
ÎÎ
Î
ÎÎ
Î
ОООООООО
Î
ОООООООО
Î
ОООООО
Î
ОООООО
Î
Vin = VIH or V
IL
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
ÎÎ
Î
ÎÎ
Î
4.5
6.0
ÎÎ
Î
ÎÎ
Î
3.98
5.48
Î
Î
Î
Î
3.84
5.34
ÎÎ
Î
ÎÎ
Î
3.7
5.2
Î
Î
Î
Î
ÎÎ
Î
V
OL
ОООООООО
Î
Maximum Low–Level Output Voltage
ОООООО
Î
Vin = VIH or V
IL
|I
out
| v 20 µA
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
Î
0.1
0.1
0.1
Î
Î
0.1
0.1
0.1
ÎÎ
Î
0.1
0.1
0.1
Î
Î
V
ÎÎÎООООООООÎОООООО
Î
Vin = VIH or V
IL
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
ÎÎ
Î
4.5
6.0
ÎÎ
Î
0.26
0.26
Î
Î
0.33
0.33
ÎÎ
Î
0.4
0.4
Î
Î
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance cir­cuit. For proper operation, Vin and V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
MC74HC174A
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3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Unit
Guaranteed Limit
V
CC
V
Test Conditions
Parameter
Symbol
Unit
v
125_C
v
85_C
– 55 to
25_C
V
CC
V
Test Conditions
Parameter
Symbol
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
ÎÎ
Î
I
CC
ОООООООО
Î
Maximum Quiescent Supply Current (per Package)
ОООООО
Î
Vin = VCC or GND I
out
= 0 µA
ÎÎ
Î
6.0
ÎÎ
Î
4.0
Î
Î
40
ÎÎ
Î
160
Î
Î
µA
NOTES:
1. Information on typical parametric values along with high frequency or heavy load considerations, can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Total Supply Current = ICC + S∆ICC.
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
ÎÎÎ
Î
Symbol
ОООООООООООООО
Î
Parameter
ÎÎ
Î
V
CC V
ÎÎ
Î
– 55 to
25_C
Î
Î
v
85_C
ÎÎ
Î
v
125_C
Î
Î
Unit
ÎÎÎ
Î
f
max
ОООООООООООООО
Î
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
Î
6.0 30 35
Î
Î
4.8 24 28
ÎÎ
Î
4.0 20 24
Î
Î
MHz
ÎÎÎ
Î
t
PLH
t
PHL
ОООООООООООООО
Î
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
Î
110
22 19
Î
Î
140
28 24
ÎÎ
Î
165
33 28
Î
Î
ns
ÎÎÎ
Î
t
PLH
t
PHL
ОООООООООООООО
Î
Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
Î
110
21 19
Î
Î
140
28 24
ÎÎ
Î
160
32 27
Î
Î
ns
ÎÎÎ
Î
t
TLH
t
THL
ОООООООООООООО
Î
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
Î
75 15 13
Î
Î
95 19 16
ÎÎ
Î
110
22 19
Î
Î
ns
C
in
Maximum Input Capacitance
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
62
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
V
– 55 to 25_C
ÎÎÎÎ
v
85_C
v
125_C
Symbol
Parameter
Fig.
CC
V
Min
Max
ÎÎ
Min
Max
Min
Max
Unit
ÎÎ
Î
t
su
ООООООООООО
Î
Minimum Setup Time, Data to Clock
Î
Î
3
Î
Î
2.0
4.5
6.0
Î
Î
50 10
9.0
Î
ÎÎ
Î
Î
65 13 11
ÎÎÎ
Î
75 15 13
ÎÎÎ
Î
ns
ÎÎ
Î
t
h
ООООООООООО
Î
Minimum Hold Time, Clock to Data
Î
Î
3
Î
Î
2.0
4.5
6.0
Î
Î
5.0
5.0
5.0
Î
ÎÎ
Î
Î
5.0
5.0
5.0
ÎÎÎ
Î
5.0
5.0
5.0
ÎÎÎ
Î
ns
ÎÎ
Î
t
rec
ООООООООООО
Î
Minimum Recovery Time, Reset Inactive to Clock
Î
Î
2
Î
Î
2.0
4.5
6.0
Î
Î
5.0
5.0
5.0
Î
ÎÎ
Î
Î
5.0
5.0
5.0
ÎÎÎ
Î
5.0
5.0
5.0
ÎÎÎ
Î
ns
ÎÎ
Î
t
w
ООООООООООО
Î
Minimum Pulse Width, Clock
Î
Î
1
Î
Î
2.0
4.5
6.0
Î
Î
75 15 13
Î
ÎÎ
Î
Î
95 19 16
ÎÎÎ
Î
110
22 19
ÎÎÎ
Î
ns
ÎÎ
Î
ÎÎ
Î
t
w
ООООООООООО
Î
ООООООООООО
Î
Minimum Pulse Width, Reset
Î
Î
Î
Î
2
Î
Î
Î
Î
2.0
4.5
6.0
Î
Î
Î
Î
75 15 13
Î
Î
ÎÎ
Î
Î
Î
Î
95 19 16
Î
Î
Î
Î
Î
Î
Î
Î
110
22 19
Î
Î
Î
Î
Î
Î
Î
Î
ns
ÎÎ
Î
tr, t
f
ООООООООООО
Î
Maximum Input Rise and Fall Times
Î
Î
1
Î
Î
2.0
4.5
6.0
ÎÎÎ
1000
500 400
ÎÎ
ÎÎÎ
Î
1000
500 400
ÎÎÎ
Î
1000
500 400
Î
Î
ns
MC74HC174A
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4
CLOCK
9
D0
3
RESET
1
D1
4
D2
6
D3
11
D4
13
D5
14
C
Q
D
R
2
5
7
10
12
15
Q0
Q1
Q2
Q3
Q4
Q5
EXPANDED LOGIC DIAGRAM
50%
V
CC
GND
V
CC
GND
50%
CLOCK
Q
RESET
t
PHL
Figure 1.
50%
DATA
CLOCK
V
CC
V
CC
GND
Figure 2.
VALID
GND
t
su
t
h
1/f
max
CLOCK
Q
t
r
t
f
V
CC
GND
90%
50%
10%
90%
50%
10%
t
PLH
t
PHL
t
TLH
t
THL
t
w
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE UNDER
TEST
OUTPUT
Figure 3. Figure 4. Test Circuit
SWITCHING W AVEFORMS
C
Q
D
R
C
Q
D
R
C
Q
D
R
C
Q
D
R
C
Q
D
R
t
w
t
rec
50%
MC74HC174A
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5
P ACKAGE DIMENSIONS
PDIP–16
N SUFFIX
CASE 648–08
ISSUE R
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A B C D F G H J K L M S
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50 0°
0.51
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74 10°
1.01
0.740
0.250
0.145
0.015
0.040
0.008
0.110
0.295 0°
0.020
0.770
0.270
0.175
0.021
0.070
0.015
0.130
0.305 10°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
2.54 BSC
1.27 BSC
0.100 BSC
0.050 BSC
–A
–
B
18
916
F
H
G
D
16 PL
S
C
–T
–
SEATING PLANE
K
J
M
L
TA0.25 (0.010)
M M
0.25 (0.010) T B A
M
S S
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A B C D F G J K M P R
9.80
3.80
1.35
0.35
0.40
0.19
0.10 0°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25 7°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004 0°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009 7°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
1
8
916
–A
–
–B
–
D
16 PL
K
C
G
–T
–
SEATING
PLANE
R X 45°
M
J
F
P 8 PL
0.25 (0.010) B
M M
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
MC74HC174A
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6
Notes
MC74HC174A
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7
Notes
MC74HC174A
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8
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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .
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MC74HC174A/D
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