MOTOROLA MC74HC03AFR1, MC74HC03AFR2, MC74HC03AN, MC74HC03AFEL, MC74HC03AFL1 Datasheet

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 8

1 Publication Order Number:

MC74HC03A/D

MC74HC03A

Quad 2-Input NAND Gate
with Open-Drain Outputs

High–Performance Silicon–Gate CMOS

The MC74HC03A is identical in pinout to the LS03. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.

The HC03A NAND gate has, as its outputs, a high–performance
MOS N–Channel transistor. This NAND gate can, therefore, with a
suitable pullup resistor, be used in wired–AND applications. Having
the output characteristic curves given in this data sheet, this device can
be used as an LED driver or in any other application that only requires
a sinking current.

• Output Drive Capability: 10 LSTTL Loads With Suitable Pullup

Resistor

• Outputs Directly Interface to CMOS, NMOS and TTL

• High Noise Immunity Characteristic of CMOS Devices

• Operating Voltage Range: 2 to 6V

• Low Input Current: 1µA

• In Compliance With the JEDEC Standard No. 7A Requirements

• Chip Complexity: 28 FETs or 7 Equivalent Gates

DESIGN GUIDE

Criteria Value Unit

Internal Gate Count* 7.0 ea
Internal Gate Propagation Delay 1.5 ns
Internal Gate Power Dissipation 5.0 µW
Speed Power Product 0.0075 pJ

* Equivalent to a two–input NAND gate

PIN 14 = V

CC

PIN 7 = GND
* Denotes open–drain outputs

LOGIC DIAGRAM

3,6,8,11

Y*

1,4,9,12

A

2,5,10,13

B

OUTPUT

PROTECTION

DIODE

V

CC

Pinout: 14–Lead Packages (Top View)

1314 12 11 10 9 8

21 34567

V

CC

B4 A4 Y4 B3 A3 Y3

A1 B1 Y1 A2 B2 Y2 GND

Device Package Shipping

ORDERING INFORMATION

MC74HC03AN PDIP–14 2000 / Box
MC74HC03AD SOIC–14

http://onsemi.com

55 / Rail

MC74HC03ADR2 SOIC–14 2500 / Reel

MARKING

DIAGRAMS

A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

MC74HC03ADT TSSOP–14 96 / Rail
MC74HC03ADTR2 TSSOP–14

2500 / Reel

TSSOP–14
DT SUFFIX

CASE 948G

HC

03A

ALYW

1

14

1

14

PDIP–14

N SUFFIX

CASE 646

MC74HC03AN

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

1

14

HC03A

AWLYWW

L
L
H
H

L
H
L
H

FUNCTION TABLE

Inputs Output

AB

Z
Z
Z
L

Y

Z = High Impedance

MC74HC03A

http://onsemi.com

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎ

Î

750
500
450

Î

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

ÎÎÎ

Î

260

Î

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

ÎÎ

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

ÎÎ

+ 125

_

C

ÎÎ

Î

tr, t

f

ООООООООООООО

Î

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

Î

Î

0
0
0

ÎÎ

ÎÎ

1000

500
400

Î

Î

ns

DC CHARACTERISTICS (Voltages Referenced to GND)

V

Guaranteed Limit

Symbol Parameter Condition

CC

V

–55 to 25°C ≤85°C ≤125°C Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1V or VCC –0.1V

|I

out

| ≤ 20µA

2.0

3.0

4.5

6.0

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1V or VCC – 0.1V

|I

out

| ≤ 20µA

2.0

3.0

4.5

6.0

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

V

V

OL

Maximum Low–Level Output
Voltage

V

out

= 0.1V or VCC – 0.1V

|I

out

| ≤ 20µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or VIL|I

out

| ≤ 2.4mA

|I

out

| ≤ 4.0mA

|I

out

| ≤ 5.2mA

3.0

4.5

6.0

0.26

0.26

0.26

0.33

0.33

0.33

0.40

0.40

0.40

I

in

Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0µA

6.0 1.0 10 40 µA

I

OZ

Maximum Three–State Leakage
Current

Output in High–Impedance State
Vin = VIL or V

IH

V

out

= VCC or GND

6.0 ±0.5 ±5.0 ±10 µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HC03A

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3

AC CHARACTERISTICS (C

L

= 50pF, Input tr = tf = 6ns)

Guaranteed Limit

Symbol Parameter

V

CC

V

–55 to 25°C ≤85°C ≤125°C Unit

t

PLZ

,

t

PZL

Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)

2.0

3.0

4.5

6.0

120

45
24
20

150

60
30
26

180

75
36
31

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0

3.0

4.5

6.0

75
27
15
13

95
32
19
16

110

36
22
19

ns

C

in

Maximum Input Capacitance 10 10 10 pF

C

out

Maximum Three–State Output Capacitance
(Output in High–Impedance State)

10 10 10 pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

C

PD

Power Dissipation Capacitance (Per Buffer)*

8.0

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).