MOTOROLA MC74AC259, MC74ACT259 Technical data
MC74AC259
MC74AC259
MC74ACT259
8 Bit Addressable Latch
The MC74AC259/74ACT259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and also a 1-of-8 decoder and demultiplexer with active HIGH outputs. The device also incorporates an active LOW Common Clear for resetting all latches, as well as an active LOW Enable. It is functionally identical to the ALS259 8-bit addressable latch.
•Serial-to-Parallel Conversion
•Eight Bits of Storage with Output of Each Bit Available
•Random (Addressable) Data Entry
•Active High Demultiplexing or Decoding Capability
•Easily Expandable
•Common Clear
FUNCTIONAL DESCRIPTION
The MC74AC259/74ACT259 has four modes of operation as shown in the Mode Selection Table. In the addressable latch mode, data on the Data line (D) is written into the addressed latch. The addressed latch will follow the data input with all nonaddressed latches remaining in their previous states in the memory mode. All latches remain in their previous state and are unaffected by the Data or Address inputs.
In the one-of-eight decoding or demultiplexing mode, the addressed output will follow the state of the D input with all other outputs in the LOW state. In the clear mode all outputs are LOW and unaffected by the address and data inputs. When operating the MC74AC/ACT259 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The Mode Select Function Table summarizes the operations of the MC74AC/ACT259.
VCC |
MR |
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E |
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D |
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Q7 |
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Q6 |
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Q5 |
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Q4 |
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16 |
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15 |
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14 |
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13 |
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12 |
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11 |
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10 |
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9 |
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1 |
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6 |
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8 |
A0 |
A1 |
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A2 |
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Q0 |
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Q1 |
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Q2 |
Q3 |
GND |
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8-BIT
ADDRESSABLE
LATCH
N SUFFIX
CASE 648-08
PLASTIC
D SUFFIX
CASE 751B-05
PLASTIC
LOGIC SYMBOL
E D
A0
A1
A2 MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
FACT DATA
5-1
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MC74AC259 MC74ACT259 |
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MODE SELECT TABLE |
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E |
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MR |
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Mode |
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L |
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H |
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Addressable Latch |
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H |
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H |
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Memory |
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L |
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L |
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Active HIGH 8-Channel Demultiplexer |
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H |
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L |
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Clear |
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H = HIGH Voltage Level |
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L = LOW Voltage Level |
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MODE SELECT-FUNCTION TABLE |
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Operating |
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Inputs |
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Outputs |
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Mode |
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MR E D A0 |
A1 |
A2 |
Q0 |
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Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
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Master Reset |
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L |
H |
X |
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L |
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L |
L |
L |
L |
L |
L |
L |
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L |
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d |
L |
L |
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Q = d |
L |
L |
L |
L |
L |
L |
L |
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Demultiplex |
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L |
L |
d |
H |
L |
L |
L |
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Q = d |
L |
L |
L |
L |
L |
L |
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L |
L |
d |
L |
H |
L |
L |
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L |
Q = d |
L |
L |
L |
L |
L |
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(Active HIGH |
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• • |
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• • |
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Decoder when |
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• • |
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• • |
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D = H) |
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• • |
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• |
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• • |
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L |
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d |
H |
H |
H |
L |
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L |
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Q = d |
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Store |
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H |
H |
X |
X |
X |
X |
q0 |
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q1 |
q2 |
q3 |
q4 |
q5 |
q6 |
q7 |
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(Do Nothing) |
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H |
L |
d |
L |
L |
L |
Q = d |
q1 |
q2 |
q3 |
q4 |
q5 |
q6 |
q7 |
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H |
L |
d |
H |
L |
L |
q0 |
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Q = d |
q2 |
q3 |
q4 |
q5 |
q6 |
q7 |
Addressable |
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H |
L |
d |
L |
H |
L |
q0 |
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q1 |
Q = d |
q3 |
q4 |
q5 |
q6 |
q7 |
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• • |
• |
• |
• |
• |
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• • |
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Latch |
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• • |
• |
• |
• |
• |
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• • |
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• |
• |
• |
• |
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• • |
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• |
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• |
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• • |
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• |
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H |
L |
d |
H H H |
q0 |
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q1 |
q2 |
q3 |
q4 |
q5 |
q6 |
Q = d |
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H = HIGH Voltage Level
L = LOW Voltage Level X = Immaterial
d = HIGH or LOW Data one setup time prior to the LOW-to-HIGH Enable transition
q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared.
FACT DATA
5-2
MC74AC259 MC74ACT259
Q7
Q6
Q5
MR
Q4
Q3
A2
A1
A0 
Q2
Q1 D 
E
Q0
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
FACT DATA
5-3
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