MOTOROLA MC74AC175, MC74ACT175 Technical data

MC74AC175

MC74ACT175

Quad D Flip Flop With

Master Reset

The MC74AC/ACT175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops, when MR is low.

The MC74AC/ACT175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input's state is transferred to the corresponding flip-flop's output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The MC74AC/ACT175 is useful for applications where the Clock and Master Reset are common to all storage elements.

•Outputs Source/Sink 24 mA

•′ACT175 Has TTL Compatible Inputs

Pinout: 16-Lead Packages (Top View)

VCC			Q3		Q3		D3		D2		Q2		Q2		CP
	16		15		14		13		12		11		10		9

PIN NAMES


D0 ± D3				Data Inputs
CP				Clock Pulse Input
MR				Master Reset Input
Q	0 ±	Q	3	Outputs
Q0 ± Q3				Outputs


1	2	3	4	5	6	7	8
MR	Q0	Q0	D0	D1	Q1	Q1	GND

TRUTH TABLE

QUAD D FLIP-FLOP WITH MASTER RESET

N SUFFIX

CASE 648-08

PLASTIC

D SUFFIX

CASE 751B-05

PLASTIC

LOGIC SYMBOL

Inputs

Outputs

Q1 Q2 Q2 Q3 Q3

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= LOW-to-HIGH Transition of Clock

FACT DATA

5-1

MC74AC175 MC74ACT175

LOGIC DIAGRAM

MR	CP	D3		D2		D1		D0
		D	Q	D	Q	D	Q	D	Q
		CP	Q	CP	Q	CP	Q	CP	Q
		CD		CD		CD		CD

Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

MAXIMUM RATINGS*

Symbol	Parameter	Value	Unit

VCC	DC Supply Voltage (Referenced to GND)	±0.5 to +7.0	V
Vin	DC Input Voltage (Referenced to GND)	±0.5 to VCC + 0.5	V
Vout	DC Output Voltage (Referenced to GND)	±0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin	± 20	mA
Iout	DC Output Sink/Source Current, per Pin	± 50	mA
ICC	DC VCC or GND Current per Output Pin	± 50	mA
Tstg	Storage Temperature	±65 to +150	°C

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Typ	Min	Unit

VCC	Supply Voltage	′AC	2.0	5.0	6.0	V

		′ACT	4.5	5.0	5.5
		′ACT	4.5	5.0	5.5

Vin, Vout	DC Input Voltage, Output Voltage (Ref. to GND)		0		VCC	V
	Input Rise and Fall Time (Note 1)	VCC @ 3.0 V		150
tr, tf	Input Rise and Fall Time (Note 1)	VCC @ 4.5 V		40		ns/V
tr, tf	′AC Devices except Schmitt Inputs	VCC @ 4.5 V		40		ns/V
		VCC @ 5.5 V		25
tr, tf	Input Rise and Fall Time (Note 2)	VCC @ 4.5 V		10		ns/V
tr, tf	′ACT Devices except Schmitt Inputs	VCC @ 5.5 V		8.0		ns/V
		VCC @ 5.5 V		8.0
TJ	Junction Temperature (PDIP)				140	°C
TA	Operating Ambient Temperature Range		±40	25	85	°C
IOH	Output Current Ð HIGH				±24	mA
IOL	Output Current Ð LOW				24	mA

1.Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.

2.Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.

FACT DATA

5-2

+ 4 hidden pages