Datasheet MC74ACT163DR2, MC74ACT163M, MC74ACT161MR2, MC74ACT161D, MC74ACT161DR2 Datasheet (MOTOROLA)
...
5-1
FACT DATA
The MC74AC161/74ACT161 and MC74AC163/74ACT163 are high-speed
synchronous modulo-16 binary counters. They are synchronously presettable for
application in programmable dividers and have two types of Count Enable inputs
plus a Terminal Count output for versatility in forming synchronous multistage
counters. The MC74AC161/74ACT161 has an asynchronous Master Reset input
that overrides all other inputs and forces the outputs LOW. The MC74AC163/
74ACT163 has a Synchronous Reset input that overrides counting and parallel
loading and allows the outputs to be simultaneously reset on the rising edge of
the clock.
• Synchronous Counting and Loading
• High-Speed Synchronous Expansion
• Typical Count Rate of 125 MHz
• Outputs Source/Sink 24 mA
• ′ACT161 and ′ACT163 Have TTL Compatible Inputs
1516 14 13 12 11 10
21 3 4 5 6 7
V
CC
9
8
TC Q0Q1Q2Q3CET PE
*R CP P0P1P2P3CEP GND
PIN NAMES
CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock Pulse Input
MR (′161) Asynchronous Master Reset Input
SR
(′163) Synchronous Reset Input
P0–P3Parallel Data Inputs
PE Parallel Enable Input
Q0–Q3Flip-Flop Outputs
TC Terminal Count Output
SYNCHRONOUS
PRESETTABLE
BINARY COUNTER
N SUFFIX
CASE 648-08
PLASTIC
D SUFFIX
CASE 751B-05
PLASTIC
LOGIC SYMBOL
*MR for ′161
*SR
for ′163
PE P0P1P
2
CEP
P
3
CET
CP
*R Q0Q1Q2Q
3
TC
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
5-2
FACT DATA
FUNCTIONAL DESCRIPTION
The MC74AC161/74ACT161 and MC74AC163/74ACT163
count modulo-16 binary sequence. From state 15 (HHHH)
they increment to state 0 (LLLL). The clock inputs of all
flip-flops are driven in parallel through a clock buffer. Thus all
changes of the Q outputs (except due to Master Reset of the
′161) occur as a result of, and synchronous with, the
LOW-to-HIGH transition of the CP input signal. The circuits
have four fundamental modes of operation, in order of
precedence: asynchronous reset (′161), synchronous reset
(′163), parallel load, count-up and hold. Five control inputs —
Master Reset (MR
, ′161), Synchronous Reset (SR, ′163),
Parallel Enable (PE
), Count Enable Parallel (CEP) and Count
Enable Trickle (CET) determine the mode of operation, as
shown in the Mode Select Table. A LOW signal on MR
overrides all other inputs and asynchronously forces all
outputs LOW. A LOW signal on SR
overrides counting and
parallel loading and allows all outputs to go LOW on the next
rising edge of CP . A LOW signal on PE
overrides counting and
allows information on the Parallel Data (Pn) inputs to be loaded
into the flip-flops on the next rising edge of CP . With PE
and MR
(′161) or SR (′163) HIGH, CEP and CET permit counting when
both are HIGH. Conversely, a LOW signal on either CEP or
CET inhibits counting.
The MC74AC161/74ACT161 and MC74AC163/74ACT163
use D-type edge-triggered flip-flops and changing the SR
, PE,
CEP and CET inputs when the CP is in either state does not
cause errors, provided that the recommended setup and hold
times, with respect to the rising edge of CP, are observed.
The T erminal Count (TC) output is HIGH when CET is HIGH
and counter is in state 15. To implement synchronous
multistage counters, the TC outputs can be used with the CEP
and CET inputs in two different ways. Please refer to the
MC74AC568 data sheet. The TC output is subject to decoding
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops, counters or registers.
Logic Equations:Count Enable = CEP
•CET•PE
TC = Q
0•Q1•Q2•Q3
•CET
MODE SELECT TABLE
*SR
PE
CET CEP
Action on the Rising
Clock Edge ( )
L X X X Reset (Clear)
H L X X Load (Pn → Qn)
H H H H Count (Increment)
H H L X No Change (Hold)
H H X L No Change (Hold)
*For ′163 only
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
STATE DIAGRAM
15
0
14
13
12
5
4
6
7
8
1 2 3
11 10 9
C
D
PE
P
0
P
1
P
2
CEP
P
3
CET
CP
Q
0
Q
1
Q
2
Q
3
TC
MR ′161
SR
′163
′
163
ONLY
′163
CP
Q
0
Q
0
CP
DETAIL A
DETAIL A DETAIL A DETAIL A
D CP D
Q Q
LOGIC DIAGRAM
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
′
161
ONLY
′161
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
5-3
FACT DATA
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Sink/Source Current, per Pin ±50 mA
I
CC
DC VCC or GND Current per Output Pin ±50 mA
T
stg
Storage Temperature –65 to +150 °C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended
Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
′AC 2.0 5.0 6.0
VCCSupply Voltage
′ACT 4.5 5.0 5.5
V
Vin, V
out
DC Input Voltage, Output Voltage (Ref. to GND) 0 V
CC
V
VCC @ 3.0 V 150
tr, t
f
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
VCC @ 4.5 V 40 ns/V
r
, t
f
′AC Devices except Schmitt Inputs
VCC @ 5.5 V 25
Input Rise and Fall Time (Note 2)
VCC @ 4.5 V 10
tr, t
f
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
VCC @ 5.5 V 8.0
ns/V
T
J
Junction Temperature (PDIP) 140 °C
T
A
Operating Ambient Temperature Range –40 25 85 °C
I
OH
Output Current — High –24 mA
I
OL
Output Current — Low 24 mA
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
5-4
FACT DATA
DC CHARACTERISTICS
74AC 74AC
Symbol
Parameter
V
CC
(V)
TA = +25°C
TA =
–40°C to +85°C
Unit
Conditions
Typ Guaranteed Limits
V
IH
Minimum High Level
3.0 1.5 2.1 2.1 V
OUT
= 0.1 V
Input Voltage
4.5 2.25 3.15 3.15 V or VCC – 0.1 V
5.5 2.75 3.85 3.85
V
IL
Maximum Low Level
3.0 1.5 0.9 0.9 V
OUT
= 0.1 V
Input Voltage
4.5 2.25 1.35 1.35 V or VCC – 0.1 V
5.5 2.75 1.65 1.65
V
OH
Minimum High Level
3.0 2.99 2.9 2.9 I
OUT
= –50 µA
Output Voltage
4.5 4.49 4.4 4.4 V
5.5 5.49 5.4 5.4
*VIN = VIL or V
IH
3.0 2.56 2.46
–12 mA
4.5 3.86 3.76
V
I
OH
–24 mA
5.5 4.86 4.76 –24 mA
V
OL
Maximum Low Level
3.0 0.002 0.1 0.1 I
OUT
= 50 µA
Output Voltage
4.5 0.001 0.1 0.1 V
5.5 0.001 0.1 0.1
*VIN = VIL or V
IH
3.0 0.36 0.44
12 mA
4.5 0.36 0.44
V
I
OL
24 mA
5.5 0.36 0.44 24 mA
I
IN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
µA
VI = VCC, GND
I
OLD
†Minimum Dynamic
5.5 75 mA V
OLD
= 1.65 V Max
I
OHD
Output Current
5.5 –75 mA V
OHD
= 3.85 V Min
I
CC
Maximum Quiescent
Supply Current
5.5
8.080µA
VIN = VCC or GND
* All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
5-5
FACT DATA
AC CHARACTERISTICS (For Figures and Waveforms — See Section 3)
74AC161 74AC161
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Min Typ Max Min Max
Maximum Count
3.3 70 111 60
f
max
Frequency 5.0 110 167 95
MHz
3-3
Propagation Delay
3.3 2.0 7.0 12.0 1.5 13.5
t
PLH
CP to Qn (PE Input HIGH or LOW) 5.0 1.5 5.0 9.0 1.0 9.5
ns
3-6
Propagation Delay
3.3 1.5 7.0 12.0 1.5 13.0
t
PHL
CP to Qn (PE Input HIGH or LOW) 5.0 1.5 5.0 9.5 1.5 10.0
ns
3-6
Propagation Delay
3.3 3.0 9.0 15.0 2.5 16.5
t
PLH
CP to TC 5.0 2.0 6.0 10.5 1.5 11.5
ns
3-6
Propagation Delay
3.3 3.5 8.5 14.0 2.5 15.5
t
PHL
CP to TC 5.0 2.0 6.5 11.0 2.0 11.5
ns
3-6
Propagation Delay
3.3 2.0 5.5 9.5 1.5 11.0
t
PLH
CET to TC 5.0 1.5 3.5 6.5 1.0 7.5
ns
3-6
Propagation Delay
3.3 2.5 6.5 11.0 2.0 12.5
t
PHL
CET to TC 5.0 2.0 5.0 8.5 1.5 9.5
ns
3-6
Propagation Delay
3.3 2.0 6.0 12.0 1.5 13.5
t
PHL
MR to Q
n
5.0 1.5 5.5 9.5 1.5 10.0
ns
3-6
Propagation Delay
3.3 3.5 10.0 15.0 3.0 17.5
t
PHL
MR to TC 5.0 2.5 8.5 13.0 2.5 13.5
ns
3-6
* Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC CHARACTERISTICS (For Figures and Waveforms — See Section 3)
74AC163 74AC163
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Min Typ Max Min Max
Maximum Count
3.3 70 95 60
f
max
Frequency 5.0 110 140 95
MHz
3-3
Propagation Delay
3.3 2.0 7.5 12.5 1.5 13.5
t
PLH
CP to Qn (PE Input HIGH or LOW) 5.0 1.5 5.5 9.0 1.0 9.5
ns
3-6
Propagation Delay
3.3 1.5 8.5 12.0 1.5 13.0
t
PHL
CP to Qn (PE Input HIGH or LOW) 5.0 1.5 6.0 9.5 1.5 10.0
ns
3-6
Propagation Delay
3.3 3.0 9.5 15.0 2.5 16.5
t
PLH
CP to TC 5.0 2.0 7.0 10.5 1.5 11.5
ns
3-6
Propagation Delay
3.3 3.5 11.0 14.0 2.5 15.5
t
PHL
CP to TC 5.0 2.0 8.0 11.0 2.0 11.5
ns
3-6
Propagation Delay
3.3 2.0 7.5 9.5 1.5 11.0
t
PLH
CET to TC 5.0 1.5 5.5 6.5 1.0 7.5
ns
3-6
Propagation Delay
3.3 2.5 8.5 11.0 2.0 12.5
t
PHL
CET to TC 5.0 2.0 6.0 8.5 1.5 9.5
ns
3-6
* Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
5-6
FACT DATA
AC OPERATING REQUIREMENTS
74AC161 74AC161
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Typ Guaranteed Minimum
Setup Time, HIGH or LOW 3.3 6.0 13.5 16.0
t
s
Pn to CP 5.0 3.5 8.5 10.5
ns
3-9
Hold Time, HIGH or LOW 3.3 –7.0 –1.0 –0.5
t
h
Pn to CP 5.0 –4.0 0 0
ns
3-9
Setup Time, HIGH or LOW 3.3 6.5 11.5 14.0
t
s
PE to CP 5.0 4.0 7.5 8.5
ns
3-9
Hold Time, HIGH or LOW 3.3 –6.0 0 0
t
h
PE to CP 5.0 –3.5 0.5 1.0
ns
3-9
Setup Time, HIGH or LOW 3.3 3.0 6.0 7.0
t
s
CEP or CET to CP 5.0 2.0 4.5 5.0
ns
3-9
Hold Time, HIGH or LOW 3.3 –3.5 0 0
t
h
CEP or CET to CP 5.0 –2.0 0 0.5
ns
3-9
Clock Pulse Width (Load) 3.3 2.0 3.5 4.0
t
w
HIGH or LOW 5.0 2.0 2.5 3.0
ns
3-6
Clock Pulse Width (Count) 3.3 2.0 4.0 4.5
t
w
HIGH or LOW 5.0 2.0 3.0 3.5
ns
3-6
3.3 3.0 5.5 7.5
t
w
MR Pulse Width, LOW
5.0 2.5 4.5 6.0
ns
3-6
Recovery TIme 3.3 –2.0 –0.5 0
t
rec
MR to CP 5.0 –1.0 0 0.5
ns
3-9
* Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
5-7
FACT DATA
AC OPERATING REQUIREMENTS
74AC163 74AC163
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Typ Guaranteed Minimum
Setup Time, HIGH or LOW 3.3 5.5 13.5 16.0
t
s
Pn to CP 5.0 4.0 8.5 10.5
ns
3-9
Hold Time, HIGH or LOW 3.3 –7.0 –1.0 –0.5
t
h
Pn to CP 5.0 –5.0 0 0
ns
3-9
Setup Time, HIGH or LOW 3.3 5.5 14 16.5
t
s
SR to CP 5.0 4.0 9.5 11.0
ns
3-9
Hold Time, HIGH or LOW 3.3 –7.5 –1.0 –0.5
t
h
SR to CP 5.0 –5.5 –0.5 0
ns
3-9
Setup Time, HIGH or LOW 3.3 5.5 11.5 14.0
t
s
PE to CP 5.0 4.0 7.5 8.5
ns
3-9
Hold Time, HIGH or LOW 3.3 –7.5 –1.0 –0.5
t
h
PE to CP 5.0 –5.0 –0.5 0
ns
3-9
Setup Time, HIGH or LOW 3.3 3.5 6.0 7.0
t
s
CEP or CET to CP 5.0 2.5 4.5 5.0
ns
3-9
Hold Time, HIGH or LOW 3.3 –4.5 0 0
t
h
CEP or CET to CP 5.0 –3.0 0 0.5
ns
3-9
Clock Pulse Width (Load) 3.3 3.0 3.5 4.0
t
w
HIGH or LOW 5.0 2.0 2.5 3.0
ns
3-6
Clock Pulse Width (Count) 3.3 3.0 4.0 4.5
t
w
HIGH or LOW 5.0 2.0 3.0 3.5
ns
3-6
* Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
5-8
FACT DATA
DC CHARACTERISTICS
74ACT 74ACT
Symbol
Parameter
V
CC
(V)
TA = +25°C
TA =
–40°C to +85°C
Unit
Conditions
Typ Guaranteed Limits
V
IH
Minimum High Level
4.5 1.5 2.0 2.0
V
OUT
= 0.1 V
Input Voltage
5.5 1.5 2.0 2.0
V
or VCC – 0.1 V
V
IL
Maximum Low Level
4.5 1.5 0.8 0.8
V
OUT
= 0.1 V
Input Voltage
5.5 1.5 0.8 0.8
V
or VCC – 0.1 V
V
OH
Minimum High Level
4.5 4.49 4.4 4.4
I
OUT
= –50 µA
Output Voltage
5.5 5.49 5.4 5.4
V
*VIN = VIL or V
IH
4.5 3.86 3.76 V
–24 mA
5.5 4.86 4.76
I
OH
–24 mA
V
OL
Maximum Low Level
4.5 0.001 0.1 0.1
I
OUT
= 50 µA
Output Voltage
5.5 0.001 0.1 0.1
V
*VIN = VIL or V
IH
4.5 0.36 0.44 V
24 mA
5.5 0.36 0.44
I
OL
24 mA
I
IN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
µA
VI = VCC, GND
∆I
CCT
Additional Max. ICC/Input 5.5 0.6 1.5 mA VI = VCC – 2.1 V
I
OLD
†Minimum Dynamic
5.5 75 mA V
OLD
= 1.65 V Max
I
OHD
Output Current
5.5 –75 mA V
OHD
= 3.85 V Min
I
CC
Maximum Quiescent
Supply Current
5.5
8.080µA
VIN = VCC or GND
* All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
5-9
FACT DATA
AC CHARACTERISTICS (For Figures and Waveforms — See Section 3)
74ACT161 74ACT161
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Min Typ Max Min Max
Maximum Count
f
max
Frequency
5.0
115
125
100
MHz
3-3
Propagation Delay
t
PLH
CP to Qn (PE
Input HIGH or LOW)
5.0
1.5
8.0
9.5
1.5
10.5ns3-6
Propagation Delay
t
PHL
CP or Qn (PE
Input HIGH or LOW)
5.0
1.5
8.0
10.5
1.5
11.5ns3-6
Propagation Delay
t
PLH
CP to TC
5.0
2.0
11.0
11.0
1.5
12.5ns3-6
Propagation Delay
t
PHL
CP to TC
5.0
1.5
11.0
12.5
1.5
13.5ns3-6
Propagation Delay
t
PLH
CET to TC
5.0
1.5
7.5
8.5
1.5
10.0ns3-6
Propagation Delay
t
PHL
CET to TC
5.0
1.5
8.0
9.5
1.5
10.5ns3-6
Propagation Delay
t
PHL
MR
to Q
n
5.0
1.5
8.0
10.0
1.5
11.0ns3-6
Propagation Delay
t
PHL
MR
to TC
5.0
2.5
10.0
13.5
2.0
14.5ns3-6
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC CHARACTERISTICS (For Figures and Waveforms — See Section 3)
74ACT163 74ACT163
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Min Typ Max Min Max
Maximum Count
f
max
Frequency
5.0
120
140
105
MHz
3-3
Propagation Delay
t
PLH
CP to Qn (PE
Input HIGH or LOW)
5.0
1.5
5.5
10.0
1.5
11.0ns3-6
Propagation Delay
t
PHL
CP to Qn (PE
Input HIGH or LOW)
5.0
1.5
6.0
11.0
1.5
12.0ns3-6
Propagation Delay
t
PLH
CP to TC
5.0
2.5
7.0
11.5
2.0
13.5ns3-6
Propagation Delay
t
PHL
CP to TC
5.0
3.0
8.0
13.5
2.0
15.0ns3-6
Propagation Delay
t
PLH
CET to TC
5.0
2.0
5.5
9.0
1.5
10.5ns3-6
Propagation Delay
t
PHL
CET to TC
5.0
2.0
6.0
10.0
2.0
11.0ns3-6
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
5-10
FACT DATA
AC OPERATING REQUIREMENTS
74ACT161 74ACT161
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Typ Guaranteed Minimum
Setup Time, HIGH or LOW
t
s
Pn to CP
5.0
7.0
9.5
11.5
ns
3-9
Hold Time, HIGH or LOW
t
h
Pn to CP
5.0
–3.000ns3-9
Setup Time, HIGH or LOW
t
s
PE
to CP
5.0
6.0
8.5
9.5
ns
3-9
Hold Time, HIGH or LOW
t
h
PE
to CP
5.0
–3.5
– 0.5
– 0.5
ns
3-9
Setup Time, HIGH or LOW
t
s
CEP or CET to CP
5.0
4.0
5.5
6.5
ns
3-9
Hold Time, HIGH or LOW
t
h
CEP or CET to CP
5.0
–2.000ns3-9
Clock Pulse Width (Load)
t
w
HIGH or LOW
5.0
2.0
3.0
3.5
ns
3-6
Clock Pulse Width (Count)
t
w
HIGH or LOW
5.0
2.0
3.0
3.5
ns
3-6
t
w
MR Pulse Width, LOW
5.0
3.0
3.0
7.5
ns
3-6
Recovery Time
t
rec
MR
to CP
5.000
0.5
ns
3-9
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
5-11
FACT DATA
AC OPERATING REQUIREMENTS
74ACT163 74ACT163
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Typ Guaranteed Minimum
Setup Time, HIGH or LOW
t
s
Pn to CP
5.0
4.0
10.0
12.0
ns
3-9
Hold Time, HIGH or LOW
t
h
Pn to CP
5.0
–5.0
0.5
0.5
ns
3-9
Setup Time, HIGH or LOW
t
s
SR
to CP
5.0
4.0
10.0
11.5
ns
3-9
Hold Time, HIGH or LOW
t
h
SR
to CP
5.0
–5.5
–0.5
–0.5
ns
3-9
Setup Time, HIGH or LOW
t
s
PE
to CP
5.0
4.0
8.5
10.5
ns
3-9
Hold Time, HIGH or LOW
t
h
PE
to CP
5.0
–5.5
–0.5
0ns3-9
Setup Time, HIGH or LOW
t
s
CEP or CET to CP
5.0
2.5
5.5
6.5
ns
3-9
Hold Time, HIGH or LOW
t
h
CEP or CET to CP
5.0
–3.000.5
ns
3-9
Clock Pulse Width
t
w
HIGH or LOW
5.0
2.0
3.5
3.5
ns
3-6
Clock Pulse Width (Count)
t
w
HIGH or LOW
5.0
2.0
3.5
3.5
ns
3-6
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol Parameter
Value
Typ
Unit Test Conditions
C
IN
Input Capacitance 4.5 pF VCC = 5.0 V
C
PD
Power Dissipation Capacitance 45 pF VCC = 5.0 V
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
5-12
FACT DATA
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
_ _ _ _
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
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MC74AC161/D
*MC74AC161/D*
◊
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