MOTOROLA MC74AC112, MC74ACT112 Technical data

MC74AC112D

MC74AC112

MC74ACT112

Dual JK Negative	DUAL JK NEGATIVE
Edge Triggered Flip Flop	EDGE-TRIGGERED
	FLIP-FLOP

The MC74AC112/74ACT112 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.

Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
• Outputs Source/Sink 24 mA									N SUFFIX
• ′ACT112 Has TTL Compatible Inputs									CASE 648-08
									PLASTIC
	CONNECTION DIAGRAM
VCC	CD1	CD2	CP2	K2	J2	SD2	Q2
16	15	14	13	12	11	10	9
		C				S			D SUFFIX
	K				J				CASE 751B-05
		D Q				D Q
	CP				CP				PLASTIC
	J	Q			K	C Q
		S				D
		D
1	2	3	4	5	6	7	8		LOGIC SYMBOL
CP1	K1	J1	SD1	Q1	Q1	Q2	GND	4	10

MODE SELECT Ð TRUTH TABLE

Operating Mode			Inputs				Outputs
		SD	CD		J	K	Q	Q
Set		L	H		X	X	H	L
Reset (Clear)		H	L		X	X	L	H
*Undetermined		L	L		X	X	H	H
Toggle		H	H		h	h	q	q
Load ª0º (Reset)		H	H		l	h	L	H
Load ª1º (Set)		H	H		h	l	H	L
Hold		H	H		l	l	q	q

*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously.

H, h = HIGH Voltage Level

L, l = LOW Voltage Level X = Don't Care

l, h (q) = Lower case letters indicate the state of the referenced input

(or output) one set-up time prior to the HIGH to LOW clock transition.

3			SD			5	11			SD			9
		J		Q					J		Q
1		CP				6	13		CP				7
2		K		Q			12		K		Q
			CD							CD
			15		VCC = PIN 16					14

GND = PIN 8

FACT DATA

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MC74AC112 MC74ACT112

LOGIC DIAGRAM (one half shown)

Q

Q

CD	SD
J	J
CP

MAXIMUM RATINGS*

Symbol	Parameter	Value	Unit
VCC	DC Supply Voltage (Referenced to GND)	±0.5 to +7.0	V
Vin	DC Input Voltage (Referenced to GND)	±0.5 to VCC +0.5	V
Vout	DC Output Voltage (Referenced to GND)	±0.5 to VCC +0.5	V
Iin	DC Input Current, per Pin	±20	mA
Iout	DC Output Sink/Source Current, per Pin	±50	mA
ICC	DC VCC or GND Current per Output Pin	±50	mA
Tstg	Storage Temperature	±65 to +150	°C

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

RECOMMENDED OPERATING CONDITIONS

	Symbol	Parameter		Min	Typ	Max	Unit
	VCC	Supply Voltage	′AC	2.0	5.0	6.0	V
			′ACT	4.5	5.0	5.5
	Vin, Vout	DC Input Voltage, Output Voltage (Ref. to GND)		0		VCC	V
		Input Rise and Fall Time (Note 1)	VCC @ 3.0 V		150
	tr, tf		VCC @ 4.5 V		40		ns/V
		′AC Devices except Schmitt Inputs
			VCC @ 5.5 V		25
	tr, tf	Input Rise and Fall Time (Note 2)	VCC @ 4.5 V		10		ns/V
		′ACT Devices except Schmitt Inputs	VCC @ 5.5 V		8.0
	TJ	Junction Temperature (PDIP)				140	°C
	TA	Operating Ambient Temperature Range		±40	25	85	°C
	IOH	Output Current Ð High				±24	mA
	IOL	Output Current Ð Low				24	mA

1.Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.

2.Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.

FACT DATA

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