MOTOROLA MC68HC912DG128 Technical data
查询68HC912DG128CPV8供应商
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MC68HC912DG128
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Technical Data
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M68HC12
Microcontrollers
MOTOROLA.COM/SEMICONDUCTORS
MC68HC912DG128/D
Rev. 3, 10/2002
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MC68HC912DG128
Technical Data — Rev 3.0
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Motorola reserves the righ t to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of i ts products for any partic ular purpose, nor does Moto rola assume any
liability arising out of the application or use of any prod uct or circuit, and s pecifically
disclaims any an d all liability, including withou t limitation consequential or inc idental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can an d do vary in different applications and actua l performance may
vary over time. A ll operating parameters, i ncluding "Typicals" must be validated for
each customer application by customer’s technical experts. Motorola does not convey
any license under i ts patent rights nor the rig hts of others. Motorola prod ucts are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other applicat ion in wh ich the failure of the Mo torola pr oduct could cr eate a
situation where personal injury or death may oc cur. Should Buyer purchase o r use
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Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc. © Motorola, Inc., 2002
MC68HC912DG128 — Rev 3.0 Technical Data
MOTOROLA 3
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Technical Data MC68HC912DG128 — Rev 3.0
4 MOTOROLA
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Technical Data — MC68HC912DG128
List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
List of Paragraphs
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List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Section 1. General Description . . . . . . . . . . . . . . . . . . . .23
Section 2. Central Processing Unit . . . . . . . . . . . . . . . . .29
Section 3. Pinout and Signal Descriptions . . . . . . . . . . .37
Section 4. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Section 5. Operating Modes. . . . . . . . . . . . . . . . . . . . . . .75
Section 6. Bus Control and Input/Output . . . . . . . . . . . .95
Section 7. Flash Memory . . . . . . . . . . . . . . . . . . . . . . . .107
Section 8. EEPROM Memory . . . . . . . . . . . . . . . . . . . . .125
Section 9. Resets and Interrupts. . . . . . . . . . . . . . . . . .133
Section 10. I/O Ports with Key Wake-up . . . . . . . . . . . .147
Section 11. Clock Functio ns . . . . . . . . . . . . . . . . . . . . .155
Section 12. Pulse Width Modulator . . . . . . . . . . . . . . . .191
Section 13. Enhanced Capture Timer . . . . . . . . . . . . . .207
Section 14. Multiple Serial Interface . . . . . . . . . . . . . . .249
Section 15. Inter-IC Bus . . . . . . . . . . . . . . . . . . . . . . . . .273
Section 16. Analog-to-Digital Converter . . . . . . . . . . . .297
MC68HC912DG128 — Rev 3.0 Technical Data
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Section 17. MSCAN Controller. . . . . . . . . . . . . . . . . . . .311
Section 18. Development Support. . . . . . . . . . . . . . . . .355
Section 19. Electrical Specificatio ns. . . . . . . . . . . . . . .385
Section 20. Appendix: CGM Practical Aspects . . . . . .407
Section 21. Appendix: MC68HC912DG128A Flash . . .419
Section 22. Appendix: MC68HC912DG128A EEPROM 427
Section 23. Revision History . . . . . . . . . . . . . . . . . . . . .439
Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441
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Technical Data MC68HC912DG128 — Rev 3.0
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Technical Data — MC68HC912DG128
Table of Contents
List of Paragraphs
Table of Contents
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List of Figures
List of Tables
Section 1. General Description
1.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5 MC68HC912DG128 Block Diagram. . . . . . . . . . . . . . . . . . . . .28
Section 2. Central Processing Unit
2.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.4 Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.6 Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.7 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
MC68HC912DG128 — Rev 3.0 Technical Data
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Section 3. Pinout and Signal Descriptions
3.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.2 Pin Assignments in 112-pin QFP . . . . . . . . . . . . . . . . . . . . . . .37
3.3 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.4 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
3.5 Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Section 4. Registers
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4.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.2 Register Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Section 5. Operating Modes
5.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5.4 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
5.5 Internal Resource Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . .81
5.6 Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Section 6. Bus Control and Input/Output
6.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.3 Detecting Access Type from External Signals . . . . . . . . . . . . .95
6.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Section 7. Flash Memory
7.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 07
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7.3 Future Flash EEPROM Support. . . . . . . . . . . . . . . . . . . . . . .108
7.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
7.5 Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . .109
7.6 Flash EEPROM Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
7.7 Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .110
7.8 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
7.9 Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . .118
7.10 Erasing the Flash EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . .120
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7.11 Program/Erase Protection Interlocks . . . . . . . . . . . . . . . . . . .122
7.12 Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
7.13 Test Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Section 8. EEPROM Memory
8.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 25
8.3 Future EEPROM Support. . . . . . . . . . . . . . . . . . . . . . . . . . . .126
8.4 EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .127
8.5 EEPROM Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . .128
Section 9. Resets and Interrupts
9.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 33
9.3 Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
9.4 Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9.5 Interrupt Control and Priority Registers . . . . . . . . . . . . . . . . .137
9.6 Interrupt test registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
9.7 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
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9.8 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
9.9 Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
9.10 Important User Information. . . . . . . . . . . . . . . . . . . . . . . . . . .145
Section 10. I/O Ports with Key Wake-up
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 47
10.3 Key Wake-up and Port Registers . . . . . . . . . . . . . . . . . . . . . .148
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10.4 Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Section 11. Clock Functions
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 55
11.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.4 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . .157
11.5 Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . .159
11.6 Limp-Home and Fast STOP Recovery modes. . . . . . . . . . . .161
11.7 System Clock Frequency formulas. . . . . . . . . . . . . . . . . . . . .179
11.8 Clock Divider Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
11.9 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . .184
11.10 Real-Time Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
11.11 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
11.12 Clock Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Section 12. Pulse Width Modulator
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 91
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12.3 PWM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . .195
12.4 PWM Boundary Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
Table of Contents
Section 13. Enhanced Capture Timer
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 07
13.3 Enhanced Capture Timer Modes of Operation. . . . . . . . . . . .214
13.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
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13.5 Timer and Modulus Counter Operation in Different Modes . .247
Section 14. Multiple Serial Interface
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 49
14.3 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
14.4 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . .250
14.5 Serial Peripheral Interface (SPI). . . . . . . . . . . . . . . . . . . . . . .262
14.6 Port S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
Section 15. Inter-IC Bus
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 73
15.3 IIC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
15.4 IIC System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 76
15.5 IIC Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
15.6 IIC Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
15.7 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . .290
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Section 16. Analog-to-Digital Converter
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 97
16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
16.4 ATD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
16.5 ATD Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
Section 17. MSCAN Controller
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17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 11
17.3 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
17.4 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
17.5 Identifier Acceptance Filter. . . . . . . . . . . . . . . . . . . . . . . . . . .318
17.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
17.7 Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . .324
17.8 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
17.9 Timer Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
17.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 29
17.11 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 32
17.12 Programmer’s Model of Message Storage. . . . . . . . . . . . . . .332
17.13 Programmer’s Model of Control Registers . . . . . . . . . . . . . . .338
Section 18. Development Support
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 55
18.3 Instruction Queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
18.4 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .357
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18.5 Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
18.6 Instruction Tagging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
Table of Contents
Section 19. Electrical Specifications
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 85
19.3 Tables of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
Section 20. Appendix: CGM Practical Aspects
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20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 07
20.3 A Few Hints For The CGM Crystal Oscillator Applica t ion. . . .407
20.4 Practical Aspects For The PLL Usage . . . . . . . . . . . . . . . . . .410
20.5 Printed Circuit Board Guidelines. . . . . . . . . . . . . . . . . . . . . . .415
Section 21. Appendix: MC68HC912DG128A Flash
21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 19
21.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
21.4 Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . .420
21.5 Flash EEPROM Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
21.6 Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .421
21.7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423
21.8 Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . .424
21.9 Erasing the Flash EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . .425
21.10 Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
MC68HC912DG128 — Rev 3.0 Technical Data
MOTOROLA Table of Contents 13
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Section 22. Appendix: MC68HC912DG128A EEPROM
22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 27
22.3 EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .428
22.4 EEPROM Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . .430
22.5 Program/Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .436
22.6 Shadow Word Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436
22.7 Programming EEDIVH and EEDIVL Registers. . . . . . . . . . . .437
Section 23. Revision History
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Figure Title Page
2-1 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3-1 MC68HC912DG128 Pin Assignments in 112-pin QFP. . . . . . .38
3-2 112-pin QFP Mechanical Dimensions (case no987) . . . . . . . .39
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3-3 PLL Loop FIlter Connections . . . . . . . . . . . . . . . . . . . . . . . . . .41
3-4 Common Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . .43
3-5 External Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . .43
5-1 Memory Map after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
5-2 Memory Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
6-1 Access Type vsBus Control Pins . . . . . . . . . . . . . . . . . . . . . . .96
7-1 Program Sequence Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
7-2 Erase Sequence Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
10-1 STOP Key Wake-up Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .153
11-1 Internal Clock Relationships. . . . . . . . . . . . . . . . . . . . . . . . . .157
11-2 PLL Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
11-3 Clock Loss during Normal Operation . . . . . . . . . . . . . . . . . . .162
11-4 No Clock at Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . .164
11-5 STOP Exit and Fast STOP Recovery. . . . . . . . . . . . . . . . . . .167
11-6 Clock Generation Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
11-7 Clock Chain for SCI0, SCI1, RTI, COP. . . . . . . . . . . . . . . . . .181
11-8 Clock Chain for ECT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
11-9 Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM. . . . . .183
12-1 Block Diagram of PWM Left-Aligned Output Channel . . . . . .192
12-2 Block Diagram of PWM Cen ter-Aligned Output Channe l . . . .193
12-3 PWM Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
13-1 Timer Block Diagram in Latch Mode. . . . . . . . . . . . . . . . . . . .209
13-2 Timer Block Diagram in Queue Mode. . . . . . . . . . . . . . . . . . .210
13-3 8-Bit Pulse Accumulators Block Diagram. . . . . . . . . . . . . . . .211
13-4 16-Bit Pulse Accumulators Block Diagram. . . . . . . . . . . . . . .212
List of Figures
MC68HC912DG128 — Rev 3.0 Technical Data
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13-5 Block Diagram for Port7 with Output compare / Pulse
13-6 C3F-C0F Interrupt Flag Setting . . . . . . . . . . . . . . . . . . . . . . .213
14-1 Multiple Serial Interface Block Diagram . . . . . . . . . . . . . . . . .250
14-2 Serial Communications Interface Block Diagram. . . . . . . . . .251
14-3 Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . .263
14-4 SPI Clock Format 0 (CPHA = 0). . . . . . . . . . . . . . . . . . . . . . .264
14-5 SPI Clock Format 1 (CPHA = 1). . . . . . . . . . . . . . . . . . . . . . .265
14-6 Normal Mode and Bidirectional Mode. . . . . . . . . . . . . . . . . . .266
15-1 IIC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
15-2 IIC Transmission Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
15-3 IIC Clock Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . .280
15-4 Flow-Chart of Typical IIC Interrupt Routine . . . . . . . . . . . . . .295
16-1 Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . .298
17-1 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
17-2 User Model for Message Buffer Organization. . . . . . . . . . . . .316
17-3 32-bit Maskable Identifier Acceptance Filters. . . . . . . . . . . . .320
17-4 16-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . .320
17-5 8-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . . .321
17-6 SLEEP Request / Acknowledge Cycle. . . . . . . . . . . . . . . . . .327
17-7 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
17-8 Segments within the Bit Time. . . . . . . . . . . . . . . . . . . . . . . . .331
17-9 CAN Standard Compliant Bit Time Segment Settings . . . . . .331
17-10 msCAN12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
17-11 Message Buffer Organization. . . . . . . . . . . . . . . . . . . . . . . . .333
17-12 Receive/Transmit Message Buffer Extended Identifier. . . . . .334
17-13 Standard Identifier Mapping . . . . . . . . . . . . . . . . . . . . . . . . . .335
17-14 Identifier Acceptance Registers (1st bank). . . . . . . . . . . . . . .351
17-15 Identifier Acceptance Registers (2nd bank) . . . . . . . . . . . . . .351
17-16 Identifier Mask Registers (1st bank). . . . . . . . . . . . . . . . . . . .352
17-17 Identifier Mask Registers (2nd bank) . . . . . . . . . . . . . . . . . . .352
18-1 BDM Host to Target Serial Bit Timing. . . . . . . . . . . . . . . . . . .359
18-2 BDM Target to Host Serial Bit Timing (Logic 1) . . . . . . . . . . .359
18-3 BDM Target to Host Serial Bit Timing (Logic 0) . . . . . . . . . . .360
19-1 VFP Conditioning Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
19-2 VFP Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
19-3 Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
19-4 POR and External Reset Timing Diagram . . . . . . . . . . . . . . .396
Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
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19-5 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .397
19-6 WAIT Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .398
19-7 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
19-8 Port Read Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .400
19-9 Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .400
19-10 Multiplexed Expansion Bus Timing Diagram . . . . . . . . . . . . .402
19-11 SPI Timing Diagram (1 of 2). . . . . . . . . . . . . . . . . . . . . . . . . .404
19-11 A) SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . .405
19-11 B) SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . .405
19-12 SPI Timing Diagram (2 of 2). . . . . . . . . . . . . . . . . . . . . . . . . .405
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List of Figures
A) SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . .4 04
B) SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . . . .4 04
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Technical Data — MC68HC912DG128
Table Title Page
1-1 Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . .27
1-2 Development Tools Ordering Information. . . . . . . . . . . . . . . . . 27
2-1 M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . .32
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2-2 M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . .33
2-3 Summary of Indexed Operations . . . . . . . . . . . . . . . . . . . . . . .34
3-1 Power and Ground Connection Summary . . . . . . . . . . . . . . . .42
3-2 Signal Description Summary . . . . . . . . . . . . . . . . . . . . . . . . . .49
3-3 Port Description Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3-4 Port Pull-Up, Pull-Down and Reduced Drive Summary . . . . . .60
4-1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5-1 Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5-2 Mapping Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5-3 Program space Page Index . . . . . . . . . . . . . . . . . . . . . . . . . . .86
5-4 Flash Register space Page Index. . . . . . . . . . . . . . . . . . . . . . .86
5-5 Test mode program space Page Index. . . . . . . . . . . . . . . . . . .87
5-6 RFSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .90
5-7 EXSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .91
7-1 Effects of ENPE, LAT and ERAS on Array Reads . . . . . . . . .114
8-1 2K byte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . .129
8-2 Erase Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
9-1 Interrupt Vector Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9-2 Stacking Order on Entry to Interrupts. . . . . . . . . . . . . . . . . . .1 44
11-1 Summary of STOP Mode Exit Conditions. . . . . . . . . . . . . . . .172
11-2 Summary of Pseudo STOP Mode Exit Conditions . . . . . . . . .173
11-3 Clock Monitor Time-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
11-4 Real Time Interrupt Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . .186
11-5 COP Watchdog Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
12-1 Clock A and Clock B Prescaler. . . . . . . . . . . . . . . . . . . . . . . .196
12-2 PWM Left-Aligned Boundary Conditions . . . . . . . . . . . . . . . .206
List of Tables
MC68HC912DG128 — Rev 3.0 Technical Data
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12-3 PWM Center-Aligned Boundary Conditions . . . . . . . . . . . . . .206
13-1 Compare Result Output Action. . . . . . . . . . . . . . . . . . . . . . . .222
13-2 Edge Detector Circuit Configuration. . . . . . . . . . . . . . . . . . . .223
13-3 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
14-1 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
14-2 Loop Mode Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
14-3 SS Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
14-4 SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
15-1 IIC Tap and Prescale Values . . . . . . . . . . . . . . . . . . . . . . . . .282
15-2 IIC Divider and SDA Hold values . . . . . . . . . . . . . . . . . . . . . .283
16-1 ATD Response to Background Debug Enable . . . . . . . . . . . .301
16-2 Final Sample Time Selection . . . . . . . . . . . . . . . . . . . . . . . . .302
16-3 Clock Prescaler Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
16-4 Multichannel Mode Result Register Assignment . . . . . . . . . .305
17-1 msCAN12 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . .324
17-2 msCAN12 vsCPU operating modes . . . . . . . . . . . . . . . . . . . .325
17-3 Data length codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
17-4 Synchronization jump width . . . . . . . . . . . . . . . . . . . . . . . . . .341
17-5 Baud rate prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341
17-6 Time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
17-7 Time segment values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
17-8 Identifier Acceptance Mode Settings . . . . . . . . . . . . . . . . . . .349
17-9 Identifier Acceptance Hit Indication . . . . . . . . . . . . . . . . . . . .349
18-1 IPIPE Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
18-2 Hardware Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
18-3 BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . .363
18-4 BDM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
18-5 TTAGO Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
18-6 TTAGO Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
18-7 Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
18-8 REGN Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
18-9 Breakpoint Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
18-10 Breakpoint Address Range Control . . . . . . . . . . . . . . . . . . . .379
18-11 Breakpoint Read/Write Control. . . . . . . . . . . . . . . . . . . . . . . .380
18-12 Tag Pin Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
19-1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
19-2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 86
19-3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .387
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19-4 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389
19-5 ATD DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .389
19-6 Analog Converter Characteristics (Operating) . . . . . . . . . . . .390
19-7 ATD AC Characteristics (Operating). . . . . . . . . . . . . . . . . . . .391
19-8 ATD Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 91
19-9 EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
19-10 Flash EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . .392
19-11 Pulse Width Modulator Characteristics. . . . . . . . . . . . . . . . . .394
19-12 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
19-13 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
19-14 Multiplexed Expansion Bus Timing. . . . . . . . . . . . . . . . . . . . .401
19-15 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
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19-16 CGM Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
19-17 Key Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 06
19-18 msCAN12 Wake-up Time from Sleep Mode. . . . . . . . . . . . . .406
20-1 Suggested 8MHz Synthesis PLL Filter Elements
20-2 Suggested 8MHz Synthesis PLL Filter Elements
22-1 EEDIV Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431
22-2 2K byte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . .433
22-3 Erase Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .434
22-4 Shadow word mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436
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(Tracking Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413
(Acquisition Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
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MC68HC912DG128 — Rev 3.0 Technical Data
MOTOROLA List of Tables 21
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Technical Data — MC68HC912DG128
1.1 Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Section 1. General Description
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1.2 Introduction
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1.4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5 MC68HC912DG128 Block Diagram. . . . . . . . . . . . . . . . . . . . .28
The MC68HC912DG1 28 microcontroller unit (MCU) is a 16-bit device
composed of standard on-chip peripherals including a 16-bit central
processing un it (CPU12), 128K bytes of flash EEPROM, 8K bytes of
RAM, 2K bytes of EEPROM, two asynchronous seri al comm un ic atio n
interfaces (SCI), a serial peripheral interface (SPI), an inter-IC interface
(I2C), an enhanced capture timer (ECT), two 8- channel,10-bit an alog-todigital converters (ATD), a four-channel pulse-width modulator (PWM),
and two CAN 2.0 A, B software compatible mo dules (MSCAN12).
System resource mapping, clock generation, interrupt control and bus
interfacing are managed by the lite integration module (LIM). The
MC68HC912DG12 8 has full 16- bit data pa ths throug hout, howeve r, the
external bus can operate in an 8-bit narrow mode so single 8-bit wide
memory can be interfaced for l ower cost systems. The inclusion of a PLL
circuit allows pow er consumption and perf ormance to be adjusted to suit
operational requirements. In addition to the I/ O ports available in each
module, 16 I/O po rt pins are availab le with Key-Wake- Up capability from
STOP or WAIT mode.
MC68HC912DG128 — Rev 3.0 Technical Data
MOTOROLA General Description 23
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General Description
1.3 Features
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• 16-bit CPU12
• Multiplexed bus
– Upward compatible with M68HC11 instruction set
– Interrupt stacking and programmer’s model identical to
M68HC11
– 20-bit ALU
– Instruction queue
– Enhanced indexed addressing
– Sin gle chi p or expan ded
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– 16 address/16 data wide or 16 address/8 data narrow mode
• Memory
– 128K byte flash EEPROM, made of four 32K byte modules
with 8K bytes protected BOOT section in each module
– 2K byte EEPROM
– 8K byte RAM, made of two 4K byte modules with Vstby in each
module.
• Analog-to-digital converters
– 2 times x 8-channels, 10-bit resolution
Technical Data MC68HC912DG128 — Rev 3.0
24 General Description MOTOROLA
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• 1M bit per second, CAN 2.0 A, B software compatible modules,
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• Enhanced capture timer (ECT)
General Description
Features
two on the MC68HC912DG128, each with:
– Two re ceiv e an d thr ee transm i t buff er s
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or
8x8bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low- pass fi lter wake- up fun cti on
– Loop-back for self test operation
– Programmable link to a timer input capture channel, for time-
stamping and network synchronization.
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– 16-bit main counter with 7-bit prescaler
– 8 pr og ra m mabl e i npu t ca ptu re or output compare channel s; 4
of the 8 input captures with buffer
– Inpu t capture filters an d buffers, th ree successi ve captures o n
four channels, or two captures on four cha nne l s with a
capture/compare selectable on the remaining four
– Four 8-bit or two 16-bit pulse accumulators
– 16-bit modulus down-counter with 4-bit prescaler
– Four user-selectable delay counters for signal filtering
• 4 PWM channels with programmable period and duty cycle
– 8-bit 4-channel or 16-bit 2-channel
– Separate control for each pulse width and duty cycle
– Center- or left-aligned outputs
– Programmable clock select logic with a wide range of
frequencies
MC68HC912DG128 — Rev 3.0 Technical Data
MOTOROLA General Description 25
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General Description
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Freescale Semiconductor, Inc.
• Serial interfaces
• LIM (lite integration module)
– Two asynchronous serial communications interfaces (SCI)
– Inter IC bus interface (I2C)
– Synchronous serial peripheral interface (SPI)
– WCR (windowed COP watchdog, real time interrupt, clock
monitor)
– ROC (reset and clocks)
– MEBI (multiplexed externa l bus interface)
– MBI (internal bus interface and memory map)
cale Semiconductor,
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– INT (interrupt control)
• Two 8-bit ports with key wake-up interrupt
• Clock generation
– Phase-locked loop clock frequency multiplier
– Limp home mode in absence of external clock
– Slow mode divider
– Low power 0.5 to 16 MHz crystal oscillator reference clock
• 112-Pin TQFP package
– Up to 66 general-purpose I/O lines, plus up to 18 input-only
lines
• 8MHz operation at 5V
• Development support
– Single-wire background deb ug™ mode (BDM)
– On-chip hardware breakpoints
Technical Data MC68HC912DG128 — Rev 3.0
26 General Description MOTOROLA
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1.4 Ordering Information
Table 1-1. Device Ordering Information
General Description
Ordering Information
Package
0 to +70
112-Pin TQFP
Single Tray
60 Pcs
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* Important: M temperature operation is available only for single chip modes
–40 to +85
–40 to +105°C V 68HC91 2DG128VPV8
–40 to +125
Temperature
Voltage Frequency Order Number
Range Designator
°C
°C C 68HC912DG128CPV8
4.5V–5.5V 8 MHz
°C M* 68HC912DG128MPV8
Table 1-2. Development Tools Ordering Information
Description Name Order Numb er
MCUez Free from World Wide Web
Serial Debug Interface SDI
Evaluation board EVB
M68SDIL (3–5V), M68DIL12 (SDIL + MCUez +
SDBUG12)
M68EVB912DG128 (EVB only)
M68KIT912DG128 (EVB + SDIL12)
NOTE: SDBUG12 is a P & E Micro Product. It can be obtained from P & E from
their web site (http://www.pemicro.com) for approximately $100.
cale Semiconductor,
Third party tools: http://www.mcu.motsps.com/dev_tools/3rd/in dex .htm
68HC912DG128PV8
Frees
MC68HC912DG128 — Rev 3.0 Technical Data
MOTOROLA General Description 27
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Freescale Semiconductor, Inc.
General Description
1.5 MC68HC912DG128 Block Diagram
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cale Semiconductor,
Frees
VRH1
ATD1
VRL1
VDDA
VSSA
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
DDRT
DDRS
DDRP
DDRK
DDRIB
TxCAN0
RxCAN0
TxCAN1
RxCAN1
VDD ×2
VSS
PORT AD1
PT0
PT1
PT2
PT3
PT4
PT5
PORT T
PT6
PT7
PS0
PS1
PS2
PS3
PS4
PORT S
PS5
PS6
PS7
PP0
PP1
PP2
PP3
PORT P
PK0
PK1
PK2
PK3
PORT K
PK7
PIB7
PIB6
PIB5
PORTIB
PIB4
×2
Power for internal circuitry
VDDX ×2
×2
VSSX
Power for I/O drivers
VRH1
VRL1
VDDA
VSSA
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
PAD16
PAD17
PORT AD0
SDI/MISO
SDO/MOSI
IIC
DDRH
DDRJ
VRH0
VRL0
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
RxD0
TxD0
RxD1
TxD1
SCK
PW0
PW1
PW2
PW3
PIX0
PIX1
PIX2
I/O
ECS
SCL
SDA
PORTH
PORTJ
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
SS
I/O
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
VRH0
ATD0
VFP
VSTBY
BKGD
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
RESET
128K byte flash EEPROM
8K byte RAM
2K byte EEPROM
CPU12
Single-wire
background
debug module
Clock
PLL
Generation
module
Periodic interrupt
COP watchdog
Clock monitor
Breakpoints
VDDA
VSSA
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
Enhanced
capture
timer
SCI0
SCI1
VRL0
SPI
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
XIRQ
IRQ
R/W
LSTRB
ECLK
MODA
PORT E
MODB
DBE/CAL
Lite
integration
module
(LIM)
PWM
PPAGE
Multiplexed Address/Data Bus
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
KWU
KWJ7
KWJ6
KWJ5
KWJ4
KWJ3
KWJ2
KWJ1
KWJ0
CAN0
CAN1
Wide
bus
DDRA
PORT A
PA4
PA7
PA6
PA5
5
4
3
2
1
1
1
1
R
R
R
R
D
D
D
D
D
D
D
D
A
A
A
A
DATA15
DATA14
DATA13
DATA12
DATA7
DATA6
DATA5
DATA4
Narrow bus
DDRB
PORT B
PB4
PB3
PB2
PB1
PB7
PB6
PA3
PA2
PA1
PA0
0
1
1
1
9
8
R
R
R
R
D
D
D
D
D
D
D
D
A
A
A
A
DATA11
DATA9
DATA8
DATA10
DATA3
DATA2
DATA1
DATA0
PB5
7
6
5
R
R
R
D
D
D
D
D
D
A
A
A
DATA7
DATA6
DATA5
PB0
4
3
2
1
0
R
R
R
R
R
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
DATA4
DATA3
DATA2
DATA1
DATA0
Technical Data MC68HC912DG128 — Rev 3.0
28 General Description MOTOROLA
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Technical Data — MC68HC912DG128
Section 2. Central Processing Unit
2.1 Contents
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
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2.2 Introduction
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Frees
2.4 Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.6 Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.7 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
The CPU12 is a hi gh-speed, 16-bit processing uni t. It has full 16-b it data
paths and wider internal registers (up to 20 bits) for high-speed extended
math instructions. The instruction set is a proper superset of the
M68HC11instruction set. The CPU12 allows instructions with odd byte
counts, including many single-byte instructions. This provides efficient
use of ROM space. An in struction queue buffers program informatio n so
the CPU always ha s immediate access to at least three bytes of machine
code at the start of every instruction. The CPU12 also offers an
extensive set of indexed addressing cap ab ilities.
2.3 Programming Model
CPU12 registers are a n inte gral pa rt of t he CPU a nd ar e not ad dressed
as if they were memory locations.
MC68HC912DG128 — Rev 3.0 Technical Data
MOTOROLA Central Processing Unit 29
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Central Processing Unit
7
15
15
15
15
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15
AB
70
D
IX
IY
SP
PC
NSXHI ZVC
0
8-BIT ACCUMULATORS A & B
OR
0
16-BIT DOUBLE ACCUMULATOR D
0
INDEX REGISTER X
0
INDEX REGISTER Y
0
STACK POINTER
0
PROGRAM COUNTER
CONDITION CODE REGISTER
Figure 2-1. Programming Model
Accumulators A and B are genera l-purpose 8-bit a ccumulators used to
hold operands and results of arithmetic calculations or data
manipulations. Some instructions treat the combination of these two 8bit accumulators as a 16-bit double accumulator (accumulator D).
Index registers X and Y are used for indexed addressing mode. In the
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indexed addressing mode, the contents of a 16-bit index register are
added to 5-bit, 9-bit, or 16-bit constants or the content of an accumulator
to form the effective addr ess of the operand to be used in the i nstruction.
Frees
Stack pointer (SP) points to the last stack location used. The CPU12
supports an automatic program stack that is used to save system
context during su br ou tine calls and interrupts, and can also be u s ed fo r
temporary storage of data. The stack pointer can also be used in all
indexed addressing modes.
Program counter is a 16-bit register that holds the address of the next
instruction to be executed. The program counter can be used in all
indexed addr essing modes except autoinc rement/decrement.
Technical Data MC68HC912DG128 — Rev 3.0
30 Central Processing Unit MOTOROLA
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