MOTOROLA MC68HC908JB8, MC68HC08JB8, MC68HC08JT8 Technical data
Freescale Semiconductor, Inc.
MC68HC908JB8
MC68HC08JB8
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M68HC08
Microcontrollers
MC68HC08JT8
Technical Data
MC68HC908JB8/D
Rev. 2.1, 12/2003
MOTOROLA.COM/SEMICONDUCTORS
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For More Information On This Product,
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Freescale Semiconductor, Inc.
MC68HC908JB8
MC68HC08JB8
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MC68HC08JT8
Technical Data
To provide the most up-to-date information, the revision of our
documents on the World Wide Web will be the most current. Your printed
copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://motorola.com/semiconductors/
The following revision history table summarizes changes contained in
this document. For your convenience, the page number designators
have been linked to the appropriate location.
Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
This product incorporates SuperFlash® technology licensed from SST. © Motorola, Inc., 2003
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1 Technical Data
MOTOROLA 3
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Revision History
Freescale Semiconductor, Inc.
Revision History
Date
December
2003
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February,
2002
Revision
Level
2.1
2
Description
4.9 ROM-Resident Routines — Removed block erase
references for ROM-resident routines.
9.8.8 USB Control Register 3 — Clarified bit descriptions for
OSTALL0 and ISTALL0.
9.8.11 USB Status Register 1 — Clarified bit descriptions for
TXACK, TXNAK, and TXSTL.
Section 19. Mechanical Specifications — Replaced incorrect
44-pin QFP drawing, case 824E to case 824A.
Corrected PTD6 and PTD7: not direct LED drive pins. 28, 210, 217
Removed incorrect RX1E text from USB control register 1. 146
Corrected Figure 9-30 for USB module. 159
Corrected timer discrepancies throughout Section 11. Timer
Interface Module (TIM).
Added Table 12-1 . Port Control Register Bits Summary. 201
Changed pullup resistor limits for D– and I/O ports in
18.6 DC Electrical Characteristics.
Added mechanical drawing for 20-pin SOIC package. 266
Added Appendix A. MC68HC08JB8 — ROM part. 269
Added Appendix B. MC68HC08JT8 — low-voltage ROM part. 277
cale Semiconductor,
Page
Number(s)
61
149, 150
153
263
177
256
Frees
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1
4 MOTOROLA
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Technical Data – MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 27
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Section 3. Random-Access Memory (RAM) . . . . . . . . . . 51
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Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . .53
Section 5. Configuration Register (CONFIG) . . . . . . . . .65
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 69
Section 7. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . .89
Section 8. System Integration Module (SIM) . . . . . . . . .93
Section 9. Universal Serial Bus Module (USB). . . . . . . 117
Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 163
Section 11. Timer Interface Module (TIM) . . . . . . . . . . .177
Section 12. Input/Output Ports (I/O) . . . . . . . . . . . . . . . 199
Section 13. External Interrupt (IRQ) . . . . . . . . . . . . . . .219
Section 14. Keyboard Interrupt Module (KBI). . . . . . . . 227
Section 15. Computer Operating Properly (COP) . . . .237
Section 16. Low Voltage Inhibit (LVI) . . . . . . . . . . . . . .243
Section 17. Break Module (BREAK) . . . . . . . . . . . . . . .245
Section 18. Electrical Specifications. . . . . . . . . . . . . . . 253
Section 19. Mechanical Specifications . . . . . . . . . . . . .263
Section 20. Ordering Information . . . . . . . . . . . . . . . . . 267
Appendix A. MC68HC08JB8. . . . . . . . . . . . . . . . . . . . . . 269
Appendix B. MC68HC08JT8 . . . . . . . . . . . . . . . . . . . . . .277
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1 Technical Data
MOTOROLA List of Sections 5
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List of Sections
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Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1
6 List of Sections MOTOROLA
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Technical Data – MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Table of Contents
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
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1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
1.5.1 Power Supply Pins (VDD, VSS) . . . . . . . . . . . . . . . . . . . . . . . 34
1.5.2 Voltage Regulator Out (V
1.5.3 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .35
1.5.4 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.5.5 External Interrupt Pins (IRQ, PTE4/D–) . . . . . . . . . . . . . . . .35
1.5.6 Port A Input/Output (I/O) Pins (PTA7/KBA7–PTA0/KBA0). .36
1.5.7 Port B (I/O) Pins (PTB7–PTB0) . . . . . . . . . . . . . . . . . . . . . . 36
1.5.8 Port C I/O Pins (PTC7–PTC0) . . . . . . . . . . . . . . . . . . . . . . . 36
1.5.9 Port D I/O Pins (PTD7–PTD0) . . . . . . . . . . . . . . . . . . . . . . . 36
1.5.10 Port E I/O Pins (PTE4/D–, PTE3/D+, PTE2/TCH1,
PTE1/TCH0, PTE0/TCLK). . . . . . . . . . . . . . . . . . . . . . . . 36
) . . . . . . . . . . . . . . . . . . . . . . .34
REG
Section 2. Memory Map
2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.3 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
2.4 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1 Technical Data
MOTOROLA Table of Contents 7
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Table of Contents
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Section 3. Random-Access Memory (RAM)
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Section 4. FLASH Memory
4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
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4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.5 FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .56
4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .57
4.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4.8 FLASH Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
4.8.1 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . .60
4.9 ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.9.1 Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4.9.2 ERASE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.9.3 PROGRAM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.9.4 VERIFY Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Section 5. Configuration Register (CONFIG)
5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1
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Section 6. Central Processor Unit (CPU)
6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .76
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6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Section 7. Oscillator (OSC)
7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.3 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .90
7.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . 91
7.4.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . 91
7.4.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . 91
7.4.4 External Clock Source (OSCXCLK) . . . . . . . . . . . . . . . . . . . 91
7.4.5 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.6 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . .92
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1 Technical Data
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Section 8. System Integration Module (SIM)
8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .96
8.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
8.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . 97
8.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . .97
8.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .97
8.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 99
8.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
8.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . .101
8.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . 102
8.4.2.6 Universal Serial Bus Reset . . . . . . . . . . . . . . . . . . . . . .102
8.4.2.7 Registers Values After Different Resets. . . . . . . . . . . . . 102
8.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
8.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 103
8.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 104
8.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . .104
8.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
8.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
8.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.6.2 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 109
8.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
8.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 110
8.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1
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8.8.1 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
8.8.2 Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
8.8.3 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . 116
Table of Contents
Section 9. Universal Serial Bus Module (USB)
9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
9.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
9.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
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9.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
9.5.1 USB Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.5.1.1 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
9.5.1.2 Packet Identifier Field . . . . . . . . . . . . . . . . . . . . . . . . . .127
9.5.1.3 Address Field (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . .128
9.5.1.4 Endpoint Field (ENDP). . . . . . . . . . . . . . . . . . . . . . . . . .128
9.5.1.5 Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . .128
9.5.1.6 End-of-Packet (EOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.5.2 Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
9.5.3 Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
9.5.4 Resume After Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.5.4.1 Host Initiated Resume . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.5.4.2 USB Reset Signalling. . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.5.4.3 Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.5.5 Low-Speed Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
9.6 Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
9.7 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.7.1 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7.2 USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.7.2.1 Output Driver Characteristics. . . . . . . . . . . . . . . . . . . . .134
9.7.2.2 Low Speed (1.5 Mbps) Driver Characteristics . . . . . . . .134
9.7.2.3 Receiver Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9.7.2.4 Data Source Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.7.2.5 Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . .136
9.7.3 USB Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1 Technical Data
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9.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.8.1 USB Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
9.8.2 USB Interrupt Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 139
9.8.3 USB Interrupt Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.8.4 USB Interrupt Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 144
9.8.5 USB Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.8.6 USB Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.8.7 USB Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9.8.8 USB Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.8.9 USB Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
9.8.10 USB Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
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9.8.11 USB Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
9.8.12 USB Endpoint 0 Data Registers . . . . . . . . . . . . . . . . . . . . . 154
9.8.13 USB Endpoint 1 Data Registers . . . . . . . . . . . . . . . . . . . . . 155
9.8.14 USB Endpoint 2 Data Registers . . . . . . . . . . . . . . . . . . . . . 156
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9.9 USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
9.9.1 USB End-of-Transaction Interrupt . . . . . . . . . . . . . . . . . . . 157
9.9.1.1 Receive Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . . 158
9.9.1.2 Transmit Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . .160
9.9.1.3 Transmit Endpoint 1. . . . . . . . . . . . . . . . . . . . . . . . . . . .161
9.9.1.4 Transmit Endpoint 2. . . . . . . . . . . . . . . . . . . . . . . . . . . .162
9.9.1.5 Receive Endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.9.2 Resume Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.9.3 End-of-Packet Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .162
Section 10. Monitor ROM (MON)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
10.4.2 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
10.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
10.4.4 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
10.4.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
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10.4.6 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
10.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Table of Contents
Section 11. Timer Interface Module (TIM)
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
11.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
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11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
11.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
11.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
11.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
11.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .182
11.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 183
11.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .183
11.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .184
11.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 185
11.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
11.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
11.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
11.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
11.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
11.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .188
11.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
11.9.1 TIM Clock Pin (PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . .189
11.9.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1) . . . . . . . 189
11.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
11.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 190
11.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
11.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .193
11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . . 194
11.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1 Technical Data
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Section 12. Input/Output Ports (I/O)
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
12.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
12.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . 203
12.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
12.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
12.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . 205
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12.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
12.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
12.5.2 Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . 208
12.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
12.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
12.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
12.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
12.7.2 Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . . 215
12.8 Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
12.8.1 Port Option Control Register . . . . . . . . . . . . . . . . . . . . . . .217
Section 13. External Interrupt (IRQ)
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
13.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
13.6 PTE4/D– Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
13.7 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .223
13.8 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .224
13.9 IRQ Option Control Register. . . . . . . . . . . . . . . . . . . . . . . . . .225
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Section 14. Keyboard Interrupt Module (KBI)
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
14.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
14.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
14.6 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
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14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
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14.8 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .233
14.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
14.9.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 233
14.9.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . .235
Section 15. Computer Operating Properly (COP)
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
15.4.1 OSCXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
15.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
15.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
15.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
15.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
15.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 240
15.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
15.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1 Technical Data
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15.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
15.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
15.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
15.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .242
Section 16. Low Voltage Inhibit (LVI)
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
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16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
16.4 LVI Control Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . .244
16.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
16.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
16.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
Section 17. Break Module (BREAK)
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
17.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 248
17.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 248
17.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 248
17.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .248
17.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
17.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
17.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
17.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
17.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . 249
17.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 250
17.6.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
17.6.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . 252
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Section 18. Electrical Specifications
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
18.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .254
18.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .255
18.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
18.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .256
18.7 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
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18.8 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
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18.9 USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 258
18.10 USB Low-Speed Source Electrical Characteristics . . . . . . . .259
18.11 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
18.12 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . .260
18.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
Section 19. Mechanical Specifications
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
19.3 44-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . .264
19.4 28-Pin Small Outline Integrated Circuit (SOIC) . . . . . . . . . . .265
19.5 20-Pin Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . .265
19.6 20-Pin Small Outline Integrated Circuit (SOIC) . . . . . . . . . . .266
Section 20. Ordering Information
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
20.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1 Technical Data
MOTOROLA Table of Contents 17
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Table of Contents
Appendix A. MC68HC08JB8
A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
A.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
A.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
A.4 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
A.5 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
A.6 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
A.7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
A.7.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .274
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A.7.2 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
A.8 MC68HC08JB8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . .275
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Appendix B. MC68HC08JT8
B.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
B.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
B.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
B.4 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
B.5 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
B.6 Reserved Register Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
B.7 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
B.8 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
B.9 Universal Serial Bus Module. . . . . . . . . . . . . . . . . . . . . . . . . .282
B.10 Low-Voltage Inhibit Module . . . . . . . . . . . . . . . . . . . . . . . . . .282
B.11 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
B.11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 282
B.11.2 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . .283
B.11.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .283
B.11.4 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
B.11.5 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
B.12 MC68HC08JT8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . .284
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1
18 Table of Contents MOTOROLA
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Technical Data – MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
List of Figures
Figure Title Page
1-1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1-2 44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .32
1-3 28-pin SOIC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . .33
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1-4 20-pin PDIP and SOIC Pin Assignments . . . . . . . . . . . . . . . . .33
1-5 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1-6 Regulator Supply Capacitor Configuration . . . . . . . . . . . . . . . .35
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2-1 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2-2 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .42
4-1 FLASH Memory Register Summary . . . . . . . . . . . . . . . . . . . . .54
4-2 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . .55
4-3 FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . .59
4-4 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . . 60
4-5 FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . . .60
5-1 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . .66
6-1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6-3 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6-6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .74
7-1 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .90
8-1 SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8-2 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8-3 SIM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1 Technical Data
MOTOROLA List of Figures 19
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Figure Title Page
8-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8-6 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
8-8 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
8-9 Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8-10 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
8-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . .107
8-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . .109
8-13 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
8-14 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . .111
8-15 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . .111
8-16 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8-17 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . .113
8-18 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . .113
8-19 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . .115
8-20 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . .116
9-1 USB I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .120
9-2 USB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
9-3 Supported Transaction Types Per Endpoint. . . . . . . . . . . . . .125
9-4 Supported USB Packet Types . . . . . . . . . . . . . . . . . . . . . . . .126
9-5 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9-6 SOP, Sync Signaling, and Voltage Levels . . . . . . . . . . . . . . .127
9-7 EOP Transaction Voltage Levels . . . . . . . . . . . . . . . . . . . . . .129
9-8 EOP Width Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9-9 External Low-Speed Device Configuration . . . . . . . . . . . . . . .132
9-10 Regulator Electrical Connections . . . . . . . . . . . . . . . . . . . . . .133
9-11 Receiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
9-12 Differential Input Sensitivity Range. . . . . . . . . . . . . . . . . . . . .135
9-13 Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
9-14 Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . .136
9-15 USB Address Register (UADDR) . . . . . . . . . . . . . . . . . . . . . .138
9-16 USB Interrupt Register 0 (UIR0) . . . . . . . . . . . . . . . . . . . . . . .139
9-17 USB Interrupt Register 1 (UIR1) . . . . . . . . . . . . . . . . . . . . . . .141
9-18 USB Interrupt Register 2 (UIR2) . . . . . . . . . . . . . . . . . . . . . . .144
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1
20 List of Figures MOTOROLA
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Figure Title Page
9-19 USB Control Register 0 (UCR0) . . . . . . . . . . . . . . . . . . . . . . .145
9-20 USB Control Register 1 (UCR1) . . . . . . . . . . . . . . . . . . . . . . .146
9-21 USB Control Register 2 (UCR2) . . . . . . . . . . . . . . . . . . . . . . .147
9-22 USB Control Register 3 (UCR3) . . . . . . . . . . . . . . . . . . . . . . .149
9-23 USB Control Register 4 (UCR4) . . . . . . . . . . . . . . . . . . . . . . .151
9-24 USB Status Register 0 (USR0). . . . . . . . . . . . . . . . . . . . . . . .152
9-25 USB Status Register 1 (USR1). . . . . . . . . . . . . . . . . . . . . . . .153
9-26 USB Endpoint 0 Data Registers (UE0D0–UE0D7). . . . . . . . .154
9-27 USB Endpoint 1 Data Registers (UE1D0–UE1D7). . . . . . . . .155
9-28 USB Endpoint 2 Data Registers (UE2D0–UE2D7). . . . . . . . .156
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9-29 OUT Token Data Flow for Receive Endpoint 0. . . . . . . . . . . .158
9-30 SETUP Token Data Flow for Receive Endpoint 0 . . . . . . . . .159
9-31 IN Token Data Flow for Transmit Endpoint 0 . . . . . . . . . . . . .160
9-32 IN Token Data Flow for Transmit Endpoint 1 . . . . . . . . . . . . .161
List of Figures
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10-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
10-2 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . .168
10-3 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
10-4 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .170
10-5 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
10-6 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
10-7 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .175
11-1 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
11-2 TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .180
11-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .184
11-4 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . .190
11-5 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . .192
11-6 TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . .193
11-7 TIM Channel Status and Control Registers (TSC0:TSC1) . . .194
11-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
11-9 TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . .198
12-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .200
12-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .202
12-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .203
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1 Technical Data
MOTOROLA List of Figures 21
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12-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
12-5 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .204
12-6 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .205
12-7 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
12-8 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 207
12-9 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . .208
12-10 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
12-11 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . 210
12-12 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . .211
12-13 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
12-14 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .213
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12-15 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . 215
12-16 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
12-17 Port Option Control Register (POCR). . . . . . . . . . . . . . . . . . . 217
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13-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .221
13-2 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .221
13-3 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .224
13-4 IRQ Option Control Register (IOCR) . . . . . . . . . . . . . . . . . . .225
14-1 Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . . . .229
14-2 Keyboard Status and Control Register (KBSCR) . . . . . . . . . .234
14-3 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . .235
15-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
15-2 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . .240
15-3 COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . .241
16-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .244
16-2 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . .244
17-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .247
17-2 Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .247
17-3 Break Status and Control Register (BRKSCR) . . . . . . . . . . . .249
17-4 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . .250
17-5 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . . 250
17-6 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . .251
17-7 Break Flag Control Register High (BFCR) . . . . . . . . . . . . . . .252
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1
22 List of Figures MOTOROLA
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19-1 44-Pin QFP (Case #824E) . . . . . . . . . . . . . . . . . . . . . . . . . . .264
19-2 28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . .265
19-3 20-Pin PDIP (Case #738) . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
19-4 20-Pin SOIC (Case #751D) . . . . . . . . . . . . . . . . . . . . . . . . . .266
A-1 MC68HC08JB8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 271
A-2 MC68HC08JB8 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . .272
B-1 MC68HC08JT8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 279
B-2 MC68HC08JT8 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . .280
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B-3 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
List of Figures
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MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1 Technical Data
MOTOROLA List of Figures 23
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List of Figures
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Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1
24 List of Figures MOTOROLA
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List of Tables
Table Title Page
1-1 Summary of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
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4-1 ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4-2 ROM-Resident Routine Variables. . . . . . . . . . . . . . . . . . . . . . .62
4-3 ERASE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4-4 PROGRAM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4-5 VERIFY Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
6-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6-2 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8-1 SIM Module Signal Name Conventions . . . . . . . . . . . . . . . . . .95
8-2 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8-3 Registers not Affected by Normal Reset. . . . . . . . . . . . . . . . .103
8-4 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
9-1 USB Module Pin Name Conventions . . . . . . . . . . . . . . . . . . .120
9-2 Supported Packet Identifiers. . . . . . . . . . . . . . . . . . . . . . . . . .127
10-1 Mode Entry Requirements and Options . . . . . . . . . . . . . . . . .166
10-2 Monitor Mode Vector Differences . . . . . . . . . . . . . . . . . . . . . . 169
10-3 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .169
10-4 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 172
10-5 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .172
10-6 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .173
10-7 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .173
10-8 READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . . 174
10-9 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . .174
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1 Technical Data
MOTOROLA List of Tables 25
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11-1 TIM Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . .178
11-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
11-3 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . .196
12-1 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .201
12-2 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
12-3 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
12-4 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
12-5 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
12-6 Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
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14-1 KBI Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . .228
14-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
20-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
A-1 Summary of MC68HC08JB8 and MC68HC908JB8
Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
A-2 MC68HC08JB8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . 275
B-1 Summary of MC68HC08JT8 and MC68HC908JB8
Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
B-2 MC68HC08JT8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . 284
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1
26 List of Tables MOTOROLA
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Technical Data – MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 1. General Description
1.1 Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
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1.2 Introduction
1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
1.5.1 Power Supply Pins (VDD, VSS) . . . . . . . . . . . . . . . . . . . . . . . 34
1.5.2 Voltage Regulator Out (V
1.5.3 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .35
1.5.4 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.5.5 External Interrupt Pins (IRQ, PTE4/D–) . . . . . . . . . . . . . . . .35
1.5.6 Port A Input/Output (I/O) Pins (PTA7/KBA7–PTA0/KBA0). .36
1.5.7 Port B (I/O) Pins (PTB7–PTB0) . . . . . . . . . . . . . . . . . . . . . . 36
1.5.8 Port C I/O Pins (PTC7–PTC0) . . . . . . . . . . . . . . . . . . . . . . . 36
1.5.9 Port D I/O Pins (PTD7–PTD0) . . . . . . . . . . . . . . . . . . . . . . . 36
1.5.10 Port E I/O Pins (PTE4/D–, PTE3/D+, PTE2/TCH1,
PTE1/TCH0, PTE0/TCLK). . . . . . . . . . . . . . . . . . . . . . . . 36
The MC68HC908JB8 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
) . . . . . . . . . . . . . . . . . . . . . . .34
REG
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1 Technical Data
MOTOROLA General Description 27
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General Description
1.3 Features
Features of the MC68HC908JB8 include:
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• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and
• 3-MHz internal bus frequency
• 8,192 bytes of on-chip FLASH memory
• 256 bytes of on-chip random-access memory (RAM)
M68HC05 Families
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• FLASH program memory security
• On-chip programming firmware for use with host PC computer
• Up to 37 general-purpose 3.3V input/output (I/O) pins, including:
– 13 or 10 shared-function I/O pins, depending on package
– 24, 8, or 2 dedicated I/O pins, depending on package
– 8 keyboard interrupts on port A, on all packages
– 10mA sink capability for normal LED on 4 pins
– 25mA sink capability for infrared LED on 2 pins
– 10mA sink capability for PS/2 connection on 2 pins
(with USB module disabled)
• 16-bit, 2-channel timer interface module (TIM) with selectable
input capture, output compare, PWM capability on each channel,
and external clock input option (TCLK)
• Full Universal Serial Bus Specification 1.1 low-speed functions:
– 1.5 Mbps data rate
1
– On-chip 3.3V regulator
– Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer
– Endpoint 1 with 8-byte transmit buffer
– Endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1
28 General Description MOTOROLA
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• System protection features:
• Low-power design (fully static with stop and wait modes)
• Master reset pin with internal pullup and power-on reset
• External interrupt pin with programmable internal pullup (IRQ)
• 44-pin quad flat pack (QFP), 28-pin small outline integrated circuit
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General Description
Features
– Optional computer operating properly (COP) reset
– Optional low-voltage detection with reset
– Illegal opcode detection with reset
– Illegal address detection with reset
package (SOIC), 20-pin small outline integrated circuit package
(SOIC), and 20-pin plastic dual in-line package (DIP)
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• Specific features of MC68HC908JB8 in 44-pin are:
– Port B is 8 bits: PTB0–PTB7
– Port C is 8 bits: PTC0–PTC7
– Port D is 8 bits: PTD0–PTD7
– Port E is 5 bits: PTE0–PTE4;
2-channel TIM module with TCLK input option
• Specific features of MC68HC908JB8 in 28-pin are:
– Port B is not available
– Port C is only one bit: PTC0
– Port D is only 7 bits: PTD0–PTD6
– Port E is 5 bits: PTE0–PTE4;
2-channel TIM module with TCLK input option
• Specific features of MC68HC908JB8 in 20-pin are:
– Port B is not available
– Port C is only one bit: PTC0
– Port D is only one bit: PTD0/1; internal PTD0 and PTD1 pads
are bonded together to a single pin, PTD0/1
– Port E is only 3 bits: PTE1, PTE3, and PTE4;
1-channel TIM module without TCLK input option
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1 Technical Data
MOTOROLA General Description 29
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General Description
Features of the CPU08 include the following:
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• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
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1.4 MCU Block Diagram
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
Figure 1-1 shows the structure of the MC68HC908JB8.
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.1
30 General Description MOTOROLA
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