Motorola MC68L11FC0FU4, MC68L11FC0PU3, MC68L11FC0PU4, MC68L11F1CFN3, MC68L11F1CPU3 Datasheet

MOTOROLA

Order this document

by MC68HC11FTS/D

SEMICONDUCTOR

TECHNICAL DATA

MC68HC11F1

MC68HC11FC0

Technical Summary

8-Bit Microcontroller

1 Introduction

The MC68HC11F1 is a high-performance member of the M68HC11 family of microcontroller units
(MCUs). High-speed expanded systems required the development of this chip with its extra input/output
(I/O) ports, an increase in static RAM (one Kbyte), internal chip-select functions, and a non-multiplexed
bus which reduces the need for external interface logic. The timer, serial I/O, and analog-to-digital (A/
D) converter enable functions similar to those found in the MC68HC11E9.

The MC68HC11FC0 is a low cost, high-speed derivative of the MC68HC11F1. It does not have
EEPROM or an analog-to-digital converter. The MC68HC11FC0 can operate at bus speeds as high as
six MHz.

This document provides a brief overview of the structure, features, control registers, packaging infor­mation and availability of the MC68HC11F1 and MC68HC11FC0. For detailed information on
M68HC11 subsystems, programming and the instruction set, refer to the
(M68HC11RM/AD).

M68HC11 Reference Manual

1.1 Features

• MC68HC11 CPU

• 512 Bytes of On-Chip Electrically Erasable Programmable ROM (EEPROM) with Block Protect
(MC68HC11F1 only)

• 1024 Bytes of On-Chip RAM (All Saved During Standby)

• Enhanced 16-Bit Timer System

— 3 Input Capture (IC) Functions
— 4 Output Compare (OC) Functions
— 4th IC or 5th OC (Software Selectable)

• On-Board Chip-Selects with Clock Stretching

• Real-Time Interrupt Circuit

• 8-Bit Pulse Accumulator

• Synchronous Serial Peripheral Interface (SPI)

• Asynchronous Nonreturn to Zero (NRZ) Serial Communication Interface (SCI)

• Power saving STOP and WAIT Modes

• Eight-Channel 8-Bit A/D Converter (MC68HC11F1 only)

• Computer Operating Properly (COP) Watchdog System and Clock Monitor

• Bus Speeds of up to 6 MHz for the MC68HC11FC0 and up to 5 MHz for the MC68HC11F1

• 68-Pin PLCC (MC68HC11F1 only), 64-Pin QFP (MC68HC11FC0 only), and 80-pin TQFP pack­age options

This document contains information on a new product. Specifications and information herein are subject to change without notice.

© MOTOROLA INC., 1997

M

1.2 Ordering Information

The following devices all have 1024 bytes of RAM. In addition, the MC68HC11F1 devices have 512
bytes of EEPROM. None of the devices contain on-chip ROM.

Table 1 MC68HC11F1 Standard Device Ordering Information

Package Temperature Frequency MC Order Number

80-Pin Thin Quad Flat Pack

(TQFP)

(14 mm X 14 mm,

1.4 mm thick)

68-Pin PLCC

0 ° to +70 °

-40 ° to +85 ° C

– 40 ° to + 105 ° C

– 40 ° to + 125 ° C

0 ° to +70 °

– 40 ° to + 85 ° C

– 40 ° to + 105 ° C

– 40 ° to + 125 ° C

5 MHz MC68HC11F1PU5
2 MHz MC68HC11F1CPU2
3 MHz MC68HC11F1CPU3
4 MHz MC68HC11F1CPU4
5 MHz MC68HC11F1CPU5
2 MHz MC68HC11F1VPU2
3 MHz MC68HC11F1VPU3
4 MHz MC68HC11F1VPU4
2 MHz MC68HC11F1MPU2
3 MHz MC68HC11F1MPU3
4 MHz MC68HC11F1MPU4
5 MHz MC68HC11F1FN5
2 MHz MC68HC11F1CFN2
3 MHz MC68HC11F1CFN3
4 MHz MC68HC11F1CFN4
5 MHz MC68HC11F1CFN5
2 MHz MC68HC11F1VFN2
3 MHz MC68HC11F1VFN3
4 MHz MC68HC11F1VFN4
2 MHz MC68HC11F1MFN2
3 MHz MC68HC11F1MFN3
4 MHz MC68HC11F1MFN4

Table 2 MC68HC11F1 Extended Voltage (3.0 to 5.5 V) Device Ordering Information

Package Temperature Frequency MC Order Number

68-Pin Plastic Leaded Chip

Carrier (PLCC)

80-Pin Thin Quad Flat Pack

(TQFP)

0 ° to +70 ° C 3 MHz MC68L11F1FN3

–40 ° to +85 ° C 3 MHz MC68L11F1CFN3

0 ° to +70 ° C 3 MHz MC68L11F1PU3

–40 ° to +85 ° C 3 MHz MC68L11F1CPU3

MOTOROLA MC68HC11F1/FC0
2 MC68HC11FTS/D

Table 3 MC68HC11FC0 Standard Device Ordering Information

Package Temperature Frequency MC Order Number

64-Pin Quad Flat Pack

(QFP)

80-Pin Thin Quad Flat Pack

(TQFP)

–40 ° to +85 ° C

0 ° to 70 ° C 6 MHz MC68HC11FC0FU6

–40 ° to +85 ° C

0 ° to 70 ° C 6 MHz MC68HC11FC0PU6

4 MHz MC68HC11FC0CFU4
5 MHz MC68HC11FC0CFU5

4 MHz MC68HC11FC0CPU4
5 MHz MC68HC11FC0CPU5

Table 4 MC68HC11FC0 Extended Voltage (3.0 to 5.5 V) Device Ordering Information

Package Temperature Frequency MC Order Number

64-Pin Quad Flat Pack

(QFP)

–0 ° to +70 ° C

80-Pin Thin Quad Flat Pack

(TQFP)

3 MHz MC68L11FC0FU3
4 MHz MC68L11FC0FU4
3 MHz MC68L11FC0PU3
4 MHz MC68L11FC0PU4

MC68HC11F1/FC0 MOTOROLA
MC68HC11FTS/D 3

1

8

14

18

25

29

33

38

42

49

53

57

64

TABLE OF CONTENTS

Section Page

1 Introduction

1.1 Features ......................................................................................................................................1

1.2 Ordering Information ...................................................................................................................2

1.3 Block Diagrams ..........................................................................................................................6

2 Pin Assignments and Signal Descriptions

2.1 MC68HC11F1 Pin Assignments ..................................................................................................8

2.2 MC68HC11FC0 Pin Assignments .............................................................................................10

2.3 Pin Descriptions ........................................................................................................................12

3 Control Registers

3.1 MC68HC11F1 Control Registers ...............................................................................................14

3.2 MC68HC11FC0 Control Registers ............................................................................................16

4 Operating Modes and System Initialization

4.1 Operating Modes .......................................................................................................................18

4.2 Memory Maps ............................................................................................................................19

4.3 System Initialization Registers ..................................................................................................20

5 Resets and Interrupts

5.1 Interrupt Sources .......................................................................................................................25

5.2 Reset and Interrupt Registers ...................................................................................................26

6 Electrically Erasable Programmable ROM

6.1 EEPROM Operation ..................................................................................................................29

6.2 EEPROM Registers ...................................................................................................................29

6.3 EEPROM Programming and Erasure ........................................................................................31

6.4 CONFIG Register Programming ...............................................................................................32

7 Parallel Input/Output

7.1 Port A ........................................................................................................................................33

7.2 Port B ........................................................................................................................................33

7.3 Port C ........................................................................................................................................33

7.4 Port D ........................................................................................................................................33

7.5 Port E ........................................................................................................................................33

7.6 Port F .........................................................................................................................................33

7.7 Port G ........................................................................................................................................34

7.8 Parallel I/O Registers ................................................................................................................34

8 Chip-Selects

8.1 Chip-Select Operation ...............................................................................................................38

8.2 Chip-Select Registers ................................................................................................................38

9 Serial Communications Interface (SCI)

9.1 SCI Block Diagrams ..................................................................................................................42

9.2 SCI Registers ............................................................................................................................44

10 Serial Peripheral Interface

10.1 SPI Block Diagram ....................................................................................................................49

10.2 SPI Registers ............................................................................................................................50

11 Analog-to-Digital Converter

11.1 Input Pins ..................................................................................................................................54

11.2 Conversion Sequence ...............................................................................................................54

11.3 A/D Registers ............................................................................................................................55

12 Main Timer

12.1 Timer Operation ........................................................................................................................57

12.2 Timer Registers .........................................................................................................................59

13 Pulse Accumulator

13.1 Pulse Accumulator Block Diagram ............................................................................................64

13.2 Pulse Accumulator Registers ....................................................................................................64

MOTOROLA MC68HC11F1/FC0
4 MC68HC11FTS/D

REGISTER INDEX

Register Address Page

ADCTL ................A/D Control/Status.........................................................$1030

BAUD.................. Baud Rate......................................................................$102B

BPROT................ Block Protect..................................................................$1035

CFORC ............... Timer Force Compare....................................................$100B

CONFIG.............. EEPROM Mapping, COP, EEPROM Enables...............$103F

COPRST............. Arm/Reset COP Timer Circuitry.....................................$103A

CSCTL ................ Chip-Select Control........................................................$105D

CSGADR............. General-Purpose Chip-Select Address Register........... $105E

CSGSIZ............... General-Purpose Chip-Select Size Register ................$105F

CSSTRH ............. Clock Stretching.............................................................$105C

DDRA.................. Port A Data Register......................................................$1001

DDRC.................. Data Direction Register for Port C.................................$1007

DDRD.................. Data Direction Register for Port D.................................$1009

DDRG.................. Data Direction Register for Port G.................................$1003

HPRIO................. Highest Priority Interrupt and Miscellaneous ................$103C

INIT ..................... RAM and I/O Mapping...................................................$103D

OC1D.................. Output Compare 1 Data ................................................$100D

OC1M.................. Output Compare 1 Mask ...............................................$100C

OPT2................... System Configuration Option Register 2 .......................$1038

OPTION .............. System Configuration Options.......................................$1039

PACNT................ Pulse Accumulator Count ..............................................$1027

PACTL................. Pulse Accumulator Control ...........................................$1026

PORTA................ Port A Data....................................................................$1000

PORTB................ Port B Data....................................................................$1004 ..........................35

PORTC................ Port C Data....................................................................$1006 ..........................35

PORTD................ Port D Data....................................................................$1008 ..........................36

PORTE................ Port E Data....................................................................$100A ..........................36

PORTF................ Port F Data ....................................................................$1005 ..........................35

PORTG ............... Port G Data....................................................................$1002 ..........................34

PPROG............... EEPROM Programming Control....................................$103B ..........................30

SCCR1................ SCI Control 1 ................................................................$102C ..........................46

SCCR2................ SCI Control 2 ................................................................$102D ..........................46

SCDR.................. Serial Communications Data Register...........................$102F ..........................48

SCSR.................. SCI Status......................................................................$102E ..........................47

SPCR.................. Serial Peripheral Control ...............................................$1028 ..........................50

SPDR.................. SPI Data .......................................................................$102A ..........................51

SPSR .................. Serial Peripheral Status.................................................$1029 ..........................51

TCNT................... Timer Count ..................................................................$100E, $100F ..............59

TCTL1................. Timer Control 1..............................................................$1020 ..........................60

TCTL2................. Timer Control 2..............................................................$1021 ..........................61

TEST1................. Factory Test ..................................................................$103E ..........................24

TFLG1................. Timer Interrupt Flag 1 ...................................................$1023 ..........................61

TFLG2................. Timer Interrupt Flag 2 ...................................................$1025 ................... 62, 65

TI4O5.................. Timer Input Capture 4/Output Compare 5 ....................$101E, $101F ..............60

TIC1–TIC3........... Timer Input Capture ......................................................$1010–$1015 ..............60

TMSK1................ Timer Interrupt Mask 1 ..................................................$1022 ..........................61

TMSK2................ Timer Interrupt Mask 2 ..................................................$1024 ................... 62, 64

TOC1–TOC4....... Timer Output Compare .................................................$1016–$101D ..............60

..........................55

..........................44

..........................29

..........................59

............. 24

..........................27

..........................39

.........................40

..........................40

..........................38

..........................34

..........................35

..........................36

..........................35

................... 20

................... 21

..........................59

..........................59

............. 22

............. 23

..........................66

................... 63

,

,

28

30

,

27

,

22

,

,

36

52

,

,

26

56

,

65

..........................34

MC68HC11F1/FC0 MOTOROLA
MC68HC11FTS/D 5

1.3 Block Diagrams

PA7

PA6
PA5
PA4
PA3
PA2
PA1
PA0

PORT A

DDRA

VDDV

POWER

SS

PAI/0C1

OC2/OC1
OC3/OC1
OC4/OC1
IC4/OC5/OC1
IC3
IC2
IC1

E

4XOUT

CLOCK

LOGIC

PULSE

ACCUMULATOR

XTAL EXTAL

OSCILLATOR

TIMER

SYSTEM

IRQ XIRQ RESET

INTERRUPT

LOGIC

COP

PERIODIC INTERRUPT

MODA/

LIR

MODE

CONTROL

CONVERTER

A/D

MODB/

V

STBY

AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0

PORT E

V

RH

V

RL

PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0

ADDR15

ADDR14

PB7

PB6

512 BYTES EEPROM

1024 BYTES STATIC RAM

CPU

CORE

ADDR13

ADDR12

PORT B

PB5

PB4

ADDRESS BUS

ADDR10

ADDR9

ADDR8

ADDR11

PB0

PB3

PB2

PB1

ADDR6

ADDR7

PORT F

PF0

PF1

ADDR4

ADDR5

PF3

PF2

ADDR2

ADDR3

PF5

PF4

PF6

ADDR0

ADDR1

PF7

DATA BUS

DATA6

DATA7

PC0

PC1

DATA5

PORT C

DDRC

PC2

Figure 1 MC68HC11F1 Block Diagram

DATA4

PC4

PC3

DATA2

DATA3

PC5

DATA1

PC7

PC6

DATA0

R/W

CSPROG

CSGEN

CHIP

SELECTS

SCI

SPI

CSIO1
CSIO2

RxD

TxD

MISO
MOSI

SCK

PG7
PG6
PG5
PG4
PG3

DDRG

PORT G

PG2
PG1
PG0

PD0
PD1

PD2

DDRD

PORT D

PD3
PD4

SS

PD5

MOTOROLA MC68HC11F1/FC0
6 MC68HC11FTS/D

VDDV

POWER

MODB /

MODA /

E 4XOUT XTAL EXTAL

DS

SS

OSCILLATOR

CLOCK

LOGIC

IRQ XIRQ RESET

INTERRUPT

LOGIC

LIR

MODE

CONTROL

V

STBY

PA7

PA6
PA5
PA4
PA3
PA2
PA1
PA0

PE6
PE5
PE4
PE3
PE2
PE1

PORT A

PORT E

DDRA

ADDR15

ADDR14

PORT B

PB7

PB6

PAI/0C1

OC2/OC1
OC3/OC1
OC4/OC1
IC4/OC5/OC1
IC3
IC2
IC1

ADDR13

ADDR12

PB5

PB4

PB3

ADDRESS BUS

ADDR10

ADDR9

ADDR8

ADDR11

PB0

PB2

PB1

PULSE

ACCUMULATOR

1024 BYTES STATIC RAM

CPU

CORE

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

PORT F

PF0

PF1

PF2

PF3

PF4

PF5

TIMER

SYSTEM

PERIODIC INTERRUPT

ADDR0

ADDR1

DATA7

PC0

PF7

PF6

COP

DATA BUS

DATA4

DATA5

DATA6

PORT C

DDRC

PC3

PC2

PC1

DATA3

PC5

PC4

DATA1

DATA2

PC6

DATA0

PC7

R/W

CSPROG

CSGEN

CHIP

SELECTS

SCI

SPI

CSIO1
CSIO2

RxD

TxD

MISO
MOSI

SCK

PG7
PG6
PG5
PG4

DDRG

PORT G

PG3
PG2
PG1
PG0

WAIT

PD0
PD1

PD2

DDRD

PORT D

PD3
PD4

SS

PD5

Figure 2 MC68HC11FC0 Block Diagram

MC68HC11F1/FC0 MOTOROLA
MC68HC11FTS/D 7

2 Pin Assignments and Signal Descriptions

2.1 MC68HC11F1 Pin Assignments

STBY

PC1/DATA1
PC2/DATA2
PC3/DATA3
PC4/DATA4
PC5/DATA5
PC6/DATA6
PC7/DATA7

RESET

XIRQ

IRQ

PG7/CSPROG

PG6/CSGEN

PG5/CSIO1
PG4/CSIO2

PG3
PG2
PG1

PC0/DATA0

4XOUT

XTAL

EXTAL

R/WEMODA/LIR

9

8

7

6

5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

27

28

29

30

31

PG0

PD1/TxD

PD0/RxD

PD2/MISO32PD3/MOSI

MODB/V

4

3

2

MC68HC11F1

33

34

DD

V

PD5/SS

PD4/SCK

VSSVRHVRLPE7/AN7

68

1

35

36

PA7/PAI/OC1

PA6/OC2/OC1

PE3/AN3

67

66

65

37

38

39

PA5/OC3/OC1

PA4/OC4/OC1

PA3/OC5/IC4/OC1

PE6/AN6

64

40

41

PA2/IC142PA1/IC2

PE2/AN2

PE5/AN5

63

62

PA0/IC3

PE1/AN1

61

60

PE4/AN4

59

PE0/AN0

58

PF0/ADDR0

57

PF1/ADDR1

56

PF2/ADDR2

55

PF3/ADDR3
PF4/ADDR4

54

PF5/ADDR5

53
52

PF6/ADDR6

51

PF7/ADDR7
PB0/ADDR8

50
49

PB1/ADDR9

48

PB2/ADDR10

47

PB3/ADDR11

46

PB4/ADDR12

45

PB5/ADDR13

44

PB6/ADDR14

43

PB7/ADDR15

Figure 3 MC68HC11F1 68-Pin PLCC Pin Assignments

MOTOROLA MC68HC11F1/FC0
8 MC68HC11FTS/D

NC

NC

PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
PB2/ADDR10

PB1/ADDR9
PB0/ADDR8

PF7/ADDR7
PF6/ADDR6
PF5/ADDR5
PF4/ADDR4
PF3/ADDR3
PF2/ADDR2
PF1/ADDR1
PF0/ADDR0

PE0/AN0
PE4/AN4

NC

NC

NC

PB7/ADDR15

PA0/IC3

PA1/IC2

PA2/IC1

PA3/OC5/IC4/OC1

PA4/OC4/OC1

PA5/OC3/OC1

PA6/OC2/OC1

PA7/PAI/OC1

VDDPD5/SS

PD4/SCK

PD3/MOSI

PD2/MISO

PD1/TXD

PD0/RXD

PG0

NC

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

22

24

NC 21

NC

PE2AN2 25

PE1/AN123PE5/AN5

PE6/AN6 26

MC68HC11F1

29

RL

V

PE3/AN3 27

PE7/AN7 28

30

31

32

STBY

MODA/LIR 33

MODB/V

E34

R/W 35

SS

RH

V

V

38

NC

XTAL 37

EXTAL 36

4XOUT 39

60

NC

59

PG1

58

PG2

57

PG3

56

PG4/CSIO2

55

PG5/CSIO1

54

PG6/CSGEN

53

PG7/CSPROG

IRQ

52
51

XIRQ

50

RESET

49

PC7/DATA7

48

PC6/DATA6

47

PC5/DATA5

46

PC4/DATA4

45

PC3/DATA3

44

PC2/DATA2

43

PC1/DATA1

42

NC

41

NC

40

PC0/DATA0

Figure 4 Pin Assignments for the MC68HC11F1 80-Pin QFP

MC68HC11F1/FC0 MOTOROLA
MC68HC11FTS/D 9

2.2 MC68HC11FC0 Pin Assignments

PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
PB2/ADDR10

PB1/ADDR9
PB0/ADDR8
PF7/ADDR7
PF6/ADDR6
PF5/ADDR5
PF4/ADDR4
PF3/ADDR3
PF2/ADDR2
PF1/ADDR1
PF0/ADDR0

V

SS

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

PA1/IC2

PA0/IC3

PB7/ADDR15

62

64

63

19

18

17

PE2

PE5

PE1

PA2/IC1

PA4/OC4/OC1

PA3/IC4/OC5/OC1

59

60

61

MC68HC11FC0

22

21

20

DD

PE3

PE6

V

PA6/OC2/OC1

PA5/OC3/OC1

56

57

58

25

24

23

SS

V

WAIT

MODA/LIR

PD5/SS

VDDPA7/PAI/OC1

54

55

27

26

DS

STBY

MODB/V

PD3/MOSI

PD4/SCK

52

53

29

28

E

R/W

PD1/TxD

PD2/MISO

51

50

31

30

XTAL

EXTAL

PD0/RxD

49

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

32

PC0/DATA0

PG2
PG3
PG4/CSIO2
PG5/CSIO1
PG6/CSGEN

PG7/CSPROG

IRQ
XIRQ

RESET
PC7/DATA7
PC6/DATA6
PC5/DATA5
PC4/DATA4
PC3/DATA3
PC2/DATA2
PC1/DATA1

Figure 5 MC68HC11FC0 64-Pin QFP Pin Assignments

MOTOROLA MC68HC11F1/FC0
10 MC68HC11FTS/D

NC 1

NC
PB6/ADDR14
PB5/ADDR13
PB4/ADDR12 5
PB3/ADDR11 6
PB2/ADDR10 7

PB1/ADDR9 8
PB0/ADDR8 9
PF7/ADDR7 10
PF6/ADDR6 11
PF5/ADDR5 12
PF4/ADDR4 13
PF3/ADDR3 14
PF2/ADDR2 15
PF1/ADDR1 16
PF0/ADDR0 17

V

SS

PE4 19

NC

D

D

X

X

PD2/MISO

PD3/MOSI

PD4/SCK

NC

80

79

PA1/IC2

PA0/IC3

PB7/ADDR15

76

77

78

PA4/OC4/OC1

PA3/IC4/OC5/OC1

PA2/IC1

73

74

75

PA6/OC2/OC1

PA5/OC3/OC1

70

71

72

PD5/SS

VDDPA7/PAI/OC1

68

69

67

PD1/T

65

66

64

2
3
4

MC68HC11FC0

18

20

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

NC

NC

PE1

PE5

PE2

PE6

PE3

WAIT

SS

V

DD

V

MODA/LIR

DS

STBY

MODB/V

E

R/W

XTAL

EXTAL

PD0/R

63

38

NC

PG0

62

39

4XOUT

NC

61

NC

60

PG1

59
58

PG2

57

PG3

56

PG4/CSIO0

55

PG5/CSIO1

54

PG6/CSGEN

53

PG7/CSPR

52

IRQ
XIRQ

51
50

RESET

49

PC7/DATA7

48

PC6/DATA6

47

PC5/DATA5

46

PC4/DATA4

45

PC3/DATA3

44

PC2/DATA2

43

PC1/DATA1

42

NC

NC

41

40

PC0/DATA0

OG

Figure 6 MC68HC11FC0 80-Pin TQFP Pin Assignments

MC68HC11F1/FC0 MOTOROLA
MC68HC11FTS/D 11

2.3 Pin Descriptions VDD and V

SS

VDD is the positive power input to the MCU, and VSS is ground.

RESET

This active-low input initializes the MCU to a known startup state. It also acts as an open-drain
output to indicate that an internal failure has been detected in either the clock monitor or the COP
watchdog circuits.

XTAL and EXTAL

These two pins provide the interface for either a crystal or a CMOS-compatible clock to drive the
internal clock circuitry. The frequency applied to these pins is four times the desired bus
frequency (E clock).

E

This pin provides an output for the E clock, the basic timing reference signal for the bus circuitry.
The address bus is active when E is low, and the data bus is active when E is high.

DS

The data strobe output is the inverted E clock. DS is present on the MC68HC11FC0 only.

WAIT

This input is used to stretch the bus cycle to accomodate slower devices. The MCU samples the
logic level at this pin on the rising edge of E clock. If it is high, the MCU holds the E clock high for
the next four EXTAL clock cycles. If it is low, the E clock responds normally, going low two
EXTAL cycles later. The WAIT pin is present on the MC68HC11FC0 only.

4XOUT

This pin provides a buffered oscillator signal to drive another M68HC11 MCU. The 4XOUT pin is
not present on the 64-pin QFP MC68HC11FC0 package.

IRQ

This active-low input provides a means of generating asynchronous, maskable interrupt requests
for the CPU.

XIRQ

This interrupt request input can be made non-maskable by clearing the X bit in the MCU’s
condition code register.

MODA/LIR and MODB/VSTBY

The logic level applied to the MODA and MODB pins at reset determines the MCU’s opreating
mode (see Table 7 in 4 Operating Modes and System Initialization). After reset, MODA
functions as LIR, an open-drain output that indicates the start of an instruction cycle. MODB
functions as V

, providing a backup battery to maintain the contents of RAM when VDD falls.

STBY

R/W

In expanded and test modes, R/W indicates the direction of transfers on the external data bus.

VRH and V

RL

These pins provide the reference voltage for the analog-to-digital converter. Use bypass
capacitors to minimize noise on these signals. Any noise on VRH and VRL will directly affect A/D

accuracy. These pins are not present on the MC68HC11FC0.

MOTOROLA MC68HC11F1/FC0
12 MC68HC11FTS/D

Port Signals

On the MC68HC11F1, 54 pins are arranged into six 8-bit ports (ports A, B, C, E, F, and G) and
one 6-bit port (port D). On the MC68HC11FC0, either 52 or 49 pins are available, depending on
the package. General-purpose I/O port signals are discussed briefly in the following pragraphs.
For additional information, refer to 7 Parallel Input/Output.

Port A Pins

Port A is an 8-bit general-purpose I/O port (PA[7:0]) with a data register (PORTA) and a data
direction register (DDRA). Port A pins share functions with the 16-bit timer system. Out of reset,
PA[7:0] are general-purpose high-impedance inputs.

Port B Pins

Port B is an 8-bit output-only port. In single-chip modes, port B pins are general-purpose output
pins (PB[7:0]). In expanded modes, port B pins act as the high-order address lines ADDR[15:8].

Port C Pins

Port C is an 8-bit general-purpose I/O port with a data register (PORTC) and a data direction
register (DDRC). In single-chip modes, port C pins are general-purpose I/O pins PC[7:0]. In
expanded modes, port C pins are configured as data bus pins DATA[7:0].

Port D Pins

Port D is a 6-bit general-purpose I/O port with a data register (PORTD) and a data direction
register (DDRD). The six port D lines PD[5:0] can be used for general-purpose I/O or for the serial
communications interface (SCI) or serial peripheral interface (SPI) subsystems.

Port E Pins

Port E is an 8-bit input-only port that is also used as the analog input port for the analog-to-digital
converter. Port E pins that are not used for the A/D system can be used as general-purpose
inputs. However, PORTE should not be read during the sample portion of an A/D conversion
sequence.

NOTE

The A/D system is not available on the MC68HC11FC0. PE7 and PE0 are not
available on the 80-pin MC68HC11FC0. PE7, PE4, and PE0 are not available on
the 64-pin MC68HC11FC0.

Port F Pins

Port F is an 8-bit output-only port. In single-chip mode, port F pins are general-purpose output
pins PF[7:0]. In expanded mode, port F pins act as the low-order address outputs ADDR[7:0].

Port G Pins

Port G is an 8-bit general-purpose I/O port. When enabled, four chip select signals are alternate
functions of PG[7:4].

NOTE

PG[1:0] are not available on the 64-pin MC68HC11FC0.

MC68HC11F1/FC0 MOTOROLA
MC68HC11FTS/D 13

3 Control Registers

The MC68HC11F1 and MC68HC11FC0 control registers determine most of the system’s operating
characteristics. They occupy a 96-byte relocatable memory block. Their names and bit mnemonics are
summarized in the following table. Addresses shown are the default locations out of reset.

3.1 MC68HC11F1 Control Registers

Table 5 MC68HC11F1 Register and Control Bit Assignments

Bit 7 654321Bit 0

$1000 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORTA
$1001 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA
$1002 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PORTG
$1003 DDG7 DDG6 DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 DDRG
$1004 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTB
$1005 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PORTF
$1006 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORTC
$1007 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC
$1008 0 0 PD5 PD4 PD3 PD2 PD1 PD0 PORTD
$1009 0 0 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD
$100A PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORTE

$100B FOC1 FOC2 FOC3 FOC4 FOC5 0 0 0 CFORC
$100C OC1M7 OC1M6 OC1M5 OC1M4 OC1M3 0 0 0 OC1M
$100D OC1D7 OC1D6 OC1D5 OC1D4 OC1D3 0 0 0 OC1D
$100E Bit 15 14 13 12 11 10 9 Bit 8 TCNT (High)

$100F Bit 7 654321Bit 0 TCNT (Low)

$1010 Bit 15 14 13 12 11 10 9 Bit 8 TIC1 (High)

$1011 Bit 7 654321Bit 0 TIC1 (Low)

$1012 Bit 15 14 13 12 11 10 9 Bit 8 TIC2 (High)

$1013 Bit 7 654321Bit 0 TIC2 (Low)

$1014 Bit 15 14 13 12 11 10 9 Bit 8 TIC3 (High)

$1015 Bit 7 654321Bit 0 TIC3 (Low)

$1016 Bit 15 14 13 12 11 10 9 Bit 8 TOC1 (High)

$1017 Bit 7 654321Bit 0 TOC1 (Low)

$1018 Bit 15 14 13 12 11 10 9 Bit 8 TOC2 (High)

$1019 Bit 7 654321Bit 0 TOC2 (Low)
$101A Bit 15 14 13 12 11 10 9 Bit 8 TOC3 (High)

$101B Bit 7 654321Bit 0 TOC3 (Low)
$101C Bit 15 14 13 12 11 10 9 Bit 8 TOC4 (High)

$101D Bit 7 654321Bit 0 TOC4 (Low)
$101E Bit 15 14 13 12 11 10 9 Bit 8 TI4/O5 (High)

$101F Bit 7 654321Bit 0 TI4/O5 (Low)

$1020 OM2 OL2 OM3 OL3 OM4 OL4 OM5 OL5 TCTL1

$1021 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A TCTL2

MOTOROLA MC68HC11F1/FC0
14 MC68HC11FTS/D

Table 5 MC68HC11F1 Register and Control Bit Assignments (Continued)

Bit 7 654321Bit 0

$1022 OC1I OC2I OC3I OC4I I4/O5I IC1I IC2I IC3I TMSK1

$1023 OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F TFLG1

$1024 TOI RTII PAOVI PAII 0 0 PR1 PR0 TMSK2

$1025 TOF RTIF PAOVF PAIF 0000TFLG2

$1026 0 PAEN PAMOD PEDGE 0 I4/05 RTR1 RTR0 PACTL

$1027 Bit 7 654321Bit 0 PACNT

$1028 SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0 SPCR

$1029 SPIF WCOL 0 MODF 0000SPSR
$102A Bit 7 654321Bit 0 SPDR
$102B TCLR SCP2 SCP1 SCP0 RCKB SCR2 SCR1 SCR0 BAUD
$102C R8 T8 0 M WAKE 0 0 0 SCCR1
$102D TIE TCIE RIE ILIE TE RE RWU SBK SCCR2
$102E TDRE TC RDRF IDLE OR NF FE 0 SCSR
$102F Bit 7 654321Bit 0 SCDR

$1030 CCF 0 SCAN MULT CD CC CB CA ADCTL

$1031 Bit 7 654321Bit 0 ADR1

$1032 Bit 7 654321Bit 0 ADR2

$1033 Bit 7 654321Bit 0 ADR3

$1034 Bit 7 654321Bit 0 ADR4

$1035 0 0 0 PTCON BPRT3 BPRT2 BPRT1 BPRT0 BPROT

$1036

$1037

$1038 GWOM CWOM CLK4X LIRDV 0 SPRBYP 0 0 OPT2

$1039 0 0 IRQE DLY CME FCME CR1 CR0 OPTION
$103A Bit 7 654321Bit 0 COPRST
$103B ODD EVEN 0 BYTE ROW ERASE EELAT EEPGM PPROG
$103C RBOOT SMOD MDA IRV PSEL3 PSEL2 PSEL1 PSEL0 HPRIO
$103D RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0 INIT
$103E TILOP 0 OCCR CBYP DISR FCM FCOP 0 TEST1
$103F EE3 EE2 EE1 EE0 1 NOCOP 1 EEON CONFIG

$1040

to

$105B

Reserved
Reserved

Reserved

Reserved
$105C I01SA I01SB I02SA I02SB GSTHA GSTGB PSTHA PSTHB CSSTRH
$105D I01EN I01PL I02EN I02PL GCSPR PCSEN PSIZA PSIZB CSCTL
$105E GA15 GA14 GA13 GA12 GA11 GA10 0 0 CSGADR
$105F I01AV I02AV 0 GNPOL GAVLD GSIZA GSIZB GSIZC CSGSIZ

MC68HC11F1/FC0 MOTOROLA
MC68HC11FTS/D 15

3.2 MC68HC11FC0 Control Registers

Table 6 MC68HC11FC0 Register and Control Bit Assignments

Bit 7 654321Bit 0

$1000 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORTA
$1001 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA
$1002 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PORTG
$1003 DDG7 DDG6 DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 DDRG
$1004 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTB
$1005 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PORTF
$1006 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORTC
$1007 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC
$1008 0 0 PD5 PD4 PD3 PD2 PD1 PD0 PORTD

$1009 0 0 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD
$100A PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORTE
$100B FOC1 FOC2 FOC3 FOC4 FOC5 0 0 0 CFORC
$100C OC1M7 OC1M6 OC1M5 OC1M4 OC1M3 0 0 0 OC1M
$100D OC1D7 OC1D6 OC1D5 OC1D4 OC1D3 0 0 0 OC1D
$100E Bit 15 14 13 12 11 10 9 Bit 8 TCNT (High)

$100F Bit 7 654321Bit 0 TCNT (Low)

$1010 Bit 15 14 13 12 11 10 9 Bit 8 TIC1 (High)

$1011 Bit 7 654321Bit 0 TIC1 (Low)

$1012 Bit 15 14 13 12 11 10 9 Bit 8 TIC2 (High)

$1013 Bit 7 654321Bit 0 TIC2 (Low)

$1014 Bit 15 14 13 12 11 10 9 Bit 8 TIC3 (High)

$1015 Bit 7 654321Bit 0 TIC3 (Low)

$1016 Bit 15 14 13 12 11 10 9 Bit 8 TOC1 (High)

$1017 Bit 7 654321Bit 0 TOC1 (Low)

$1018 Bit 15 14 13 12 11 10 9 Bit 8 TOC2 (High)

$1019 Bit 7 654321Bit 0 TOC2 (Low)
$101A Bit 15 14 13 12 11 10 9 Bit 8 TOC3 (High)

$101B Bit 7 654321Bit 0 TOC3 (Low)
$101C Bit 15 14 13 12 11 10 9 Bit 8 TOC4 (High)

$101D Bit 7 654321Bit 0 TOC4 (Low)
$101E Bit 15 14 13 12 11 10 9 Bit 8 TI4/O5 (High)

$101F Bit 7 654321Bit 0 TI4/O5 (Low)

$1020 OM2 OL2 OM3 OL3 OM4 OL4 OM5 OL5 TCTL1

$1021 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A TCTL2

$1022 OC1I OC2I OC3I OC4I I4/O5I IC1I IC2I IC3I TMSK1

$1023 OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F TFLG1

$1024 TOI RTII PAOVI PAII 0 0 PR1 PR0 TMSK2

$1025 TOF RTIF PAOVF PAIF 0000TFLG2

MOTOROLA MC68HC11F1/FC0
16 MC68HC11FTS/D

Table 6 MC68HC11FC0 Register and Control Bit Assignments (Continued)

Bit 7 654321Bit 0
$1026 0 PAEN PAMOD PEDGE 0 I4/05 RTR1 RTR0 PACTL
$1027 Bit 7 654321Bit 0 PACNT
$1028 SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0 SPCR
$1029 SPIF WCOL 0 MODF 0000SPSR

$102A Bit 7 654321Bit 0 SPDR
$102B TCLR SCP2 SCP1 SCP0 RCKB SCR2 SCR1 SCR0 BAUD
$102C R8 T8 0 M WAKE 0 0 0 SCCR1
$102D TIE TCIE RIE ILIE TE RE RWU SBK SCCR2
$102E TDRE TC RDRF IDLE OR NF FE 0 SCSR
$102F Bit 7 654321Bit 0 SCDR

$1030

to

$1037
$1038 GWOM CWOM CLK4X LIRDV 0 SPRBYP 0 0 OPT2
$1039 0 0 IRQE DLY CME FCME CR1 CR0 OPTION

$103A Bit 7 654321Bit 0 COPRST
$103B
$103C RBOOT SMOD MDA IRV PSEL3 PSEL2 PSEL1 PSEL0 HPRIO
$103D RAM5 RAM4 RAM3 RAM2 RAM1 RAM0 REG1 REG0 INIT
$103E TILOP 0 OCCR CBYP DISR FCM FCOP 0 TEST1
$103F 00000NOCOP 0 0 CONFIG

$1040

to

$105B
$105C I01SA I01SB I02SA I02SB GSTHA GSTGB PSTHA PSTHB CSSTRH
$105D I01EN I01PL I02EN I02PL GCSPR PCSEN PSIZA PSIZB CSCTL
$105E GA15 GA14 GA13 GA12 GA11 GA10 0 0 CSGADR
$105F I01AV I02AV 0 GNPOL GAVLD GSIZA GSIZB GSIZC CSGSIZ

Reserved

Reserved

Reserved

Reserved

Reserved

MC68HC11F1/FC0 MOTOROLA
MC68HC11FTS/D 17

4 Operating Modes and System Initialization

The 16-bit address bus can access 64 Kbytes of memory. Because the MC68HC11F1 and
MC68HC11FC0 are intended to operate principally in expanded mode, there is no internal ROM and
the address bus is non-multiplexed. Both devices include 1 Kbyte of static RAM, a 96-byte control reg­ister block, and 256 bytes of bootstrap ROM. The MC68HC11F1 also includes 512 bytes of EEPROM.

RAM and registers can be remapped on both the MC68HC11F1 and the MC68HC11FC0. On both the
MC68HC11F1 and the MC68HC11FC0, out of reset RAM resides at $0000 to $03FF and registers re­side at $1000 to $105F. On the MC68HC11F1, RAM and registers can both be remapped to any 4­Kbyte boundary. On the MC68HC11FC0, RAM can be remapped to any 1-Kbyte boundary, and regis­ters can be remapped to any 4-Kbyte boundary in the first 16 Kbytes of address space.

RAM and control register locations are defined by the INIT register, which can be written only once with­in the first 64 E-clock cycles after a reset in normal modes. It becomes a read-only register thereafter.
If RAM and the control register block are mapped to the same boundary, the register block has priority
of the first 96 bytes.

x

In expanded and special test modes in the MC68HC11F1, EEPROM is located from $
where x represents the value of the four high-order bits of the CONFIG register. EEPROM is enabled
by the EEON bit of the CONFIG register. In single-chip and bootstrap modes, the EEPROM is located
from $FE00 to $FFFF.

4.1 Operating Modes

Bootstrap ROM resides at addresses $BF00–$BFFF, and is only available when the MCU operates in
special bootstrap operating mode. Operating modes are determined by the logic levels applied to the
MODB and MODA pins at reset.

E00 to $xFFF,

In single-chip mode, the MCU functions as a self-contained microcontroller and has no external address
or data bus. Ports B, C and F are available for general-purpose I/O (GPIO). Ports B and F are outputs
only; each of the port C pins can be configured as input or output.

CAUTION

The MC68HC11FC0 must not be configured to boot in single-chip mode because
it has no internal ROM or EEPROM. Operation of the device in single-chip mode
will result in erratic behavior.

In expanded mode, the MCU can access external memory. Ports B and F provide the address bus, and
port C is the data bus.

Special bootstrap mode is a variation of single chip mode that provides access to the internal bootstrap
ROM. In this mode, the user can download a program into on-chip RAM through the serial communica­tion interface (SCI).

Special test mode, a variation of expanded mode, is primarily used during Motorola’s internal production
testing, but can support emulation and debugging during program development.

Table 7 shows a summary of operating modes, mode select pins, and control bits in the HPRIO register.

Table 7 Hardware Mode Select Summary

Input Pins

MODB MODA RBOOT SMOD MDA

1 0 Single Chip 0 0 0
1 1 Expanded 0 0 1
0 0 Special Bootstrap 1 1 0
0 1 Special Test 0 1 1

Mode Description

Control Bits in HPRIO (Latched at Reset)

MOTOROLA MC68HC11F1/FC0
18 MC68HC11FTS/D

4.2 Memory Maps

$0000 —

$03FF —

$1000 —
$105F —

$BF00 —

$BFFF —

$FE00 —
$FFC0 —

$FFFF —

SINGLE

CHIP

—

—

—
—

—

—

—
—

EXTERNAL

EXTERNAL

EXPANDED

—

—

—
—

—

—

—
—

BOOTSTRAP

SPECIAL

—

—

—
—

—

—

—
—

EXTERNAL

EXTERNAL

SPECIAL

TEST

x000

x3FF

y000

y05F

256 BYTES

BOOTSTRAP

ROM

RESERVED

512

BYTES

EEPROM

1024 BYTES RAM

96-BYTE REGISTER FILE

4

5

1

$BFC0

SPECIAL

MODE

INTERRUPT

VECTORS

$BFFF

$FFC0

NORMAL

MODE

INTERRUPT

VECTORS

$FFFF

2

3

MODA = 0
MODB = 1

MODA = 1
MODB = 1

MODA = 0
MODB = 0

MODA = 1
MODB = 0

NOTES:

1. RAM can be remapped to any 4-Kbyte boundary ($x000). “x” represents the value contained in RAM[3:0] in the
INIT register.

2. The register block can be remapped to any 4-Kbyte boundary ($y000). “y” represents the value contained in
REG[3:0] in the INIT register.

3. Special test mode vectors are externally addressed.

4. In special test mode the address locations $zD00—$zDFF are not externally addressable. “z” represents the val­ue of bits EE[3:0] in the CONFIG register.

5. EEPROM can be remapped to any 4-Kbyte boundary ($z000). “z” represents the value contained in EE[3:0] in
the CONFIG register.

Figure 7 MC68HC11F1 Memory Map

MC68HC11F1/FC0 MOTOROLA
MC68HC11FTS/D 19

$0000 —

$03FF —

—

—

—

—

—

1024 BYTES RAM

—

1

$1000 —
$105F —

$BF00 —

$BFFF —

$FE00 —
$FFC0 —

$FFFF —

SINGLE

CHIP

—
—

—

—

—
—

EXTERNAL

EXTERNAL

EXPANDED

—
—

—

—

—
—

BOOTSTRAP

SPECIAL

—
—

—

—

—
—

EXTERNAL

EXTERNAL

SPECIAL

TEST

256 BYTES

BOOTSTRAP

ROM

96-BYTE REGISTER FILE

$BFC0

SPECIAL

MODE

INTERRUPT

VECTORS

$BFFF

$FFC0

NORMAL

MODE

INTERRUPT

VECTORS

$FFFF

2

MODA = 0
MODB = 1

MODA = 1
MODB = 1

MODA = 0
MODB = 0

MODA = 1
MODB = 0

NOTES:

1. RAM can be remapped to any 1-Kbyte boundary, depending on the value contained in the RAM field in the INIT
register.

2. The register block can be remapped to $0000, $2000, or $3000, depending on the value contained in REG[1:0]
in the INIT register.

Figure 8 MC68HC11FC0 Memory Map

4.3 System Initialization Registers

HPRIO — Highest Priority Interrupt and Miscellaneous $x03C

Bit 7 654321Bit 0

RBOOT SMOD MDA IRV PSEL3 PSEL2 PSEL1 PSEL0

RESET: 0 0 0 0 0 1 0 1 Single-Chip

0 0 1 0 0 1 0 1 Expanded
1 1 0 1 0 1 0 1 Bootstrap
0 1 1 1 0 1 0 1 Special Test

MOTOROLA MC68HC11F1/FC0
20 MC68HC11FTS/D

RBOOT — Read Bootstrap ROM

RBOOT is valid only when SMOD is set to one (special bootstrap or special test mode). RBOOT can
only be written in special modes but can be read anytime.

0 = Boot loader ROM disabled and not in memory map
1 = Boot loader ROM enabled and in memory map at $BF00–$BFFF

SMOD and MDA — Special Mode Select and Mode Select A

The initial value of SMOD is the
of reset. The initial value of MDA

inverse

equals

of the logic level present on the MODB pin at the rising edge

the logic level present on the MODA pin at the rising edge of
reset. These two bits can be read at any time. They can be written at any time in special modes. Neither
bit can be written in normal modes. SMOD cannot be set once it has been cleared. Refer to Table 8.

Table 8 Hardware Mode Select Summary

Input Pins

MODB MODA RBOOT SMOD MDA

1 0 Single Chip 0 0 0
1 1 Expanded 0 0 1
0 0 Special Bootstrap 1 1 0
0 1 Special Test 0 1 1

Mode Description

Control Bits in HPRIO (Latched at Reset)

IRV — Internal Read Visibility

This bit can be read at any time. It can be written at any time in special modes, but only once in normal
modes. In single-chip and bootstrap modes, IRV has no meaning or effect.

0 = Internal reads not visible
1 = Data from internal reads is driven on the external data bus

PSEL[3:0] — See 5.2 Reset and Interrupt Registers, page 27.
INIT — RAM and I/O Mapping (MC68HC11FC0 only) $x03D

Bit 7 6 5 4 3 2 1 Bit 0

RAM5 RAM4 RAM3 RAM2 RAM1 RAM0 REG1 REG0

RESET: 0 0 0 0 0 0 0 1

The INIT register can be written only once in first 64 cycles out of reset in normal modes, or at any time
in special modes.

NOTE

The register diagram above applies to the MC68HC11FC0 only. A diagram and bit
descriptions of the INIT register in the MC68HC11F1 are provided elsewhere in
this section.

RAM[5:0] — Internal RAM Map Position

These bits determine the upper six bits of the RAM address and allow mapping of the RAM to any one­Kbyte boundary.

REG[1:0] — Register Block Map Position

These bits determine the location of the register block, as shown in Table 9.

Table 9 Register Block Location

REG[1:0] Register Block Address

0 0 $0000 – $005F
0 1 $1000 – $105F
1 0 $2000 – $205F
1 1 $3000 – $305F

MC68HC11F1/FC0 MOTOROLA
MC68HC11FTS/D 21