Motorola MC68HC705B5CFN, MC68HC705B5FN, MC68HC705B5MFN, MC68HC705B5VFN, MC68HC705B32FU Datasheet
...
HC05
MC68HC05B6/D
Rev. 3
MC68HC05B4
MC68HC705B5
MC68HC05B6
MC68HC05B8
MC68HC05B16
MC68HC705B16
MC68HC05B32
MC68HC705B32
TECHNICAL
DATA
MC68HC05B6
!MOTOROLA
TECHNICAL DATA
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INTRODUCTION
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
INPUT/OUTPUT PORTS
PROGRAMMABLE TIMER
SERIAL COMMUNICATIONS INTERFACE
PULSE LENGTH D/A CONVERTERS
ANALOG TO DIGITAL CONVERTER
RESETS AND INTERRUPTS
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
ORDERING INFORMATION
APPENDICES
HIGH SPEED OPERATION
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INTRODUCTION
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
INPUT/OUTPUT PORTS
PROGRAMMABLE TIMER
SERIAL COMMUNICATIONS INTERFACE
PULSE LENGTH D/A CONVERTERS
ANALOG TO DIGITAL CONVERTER
RESETS AND INTERRUPTS
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
ORDERING INFORMATION
MC68HC05B4
HIGH SPEED OPERATION
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All products are sold on Motorola’s Terms & Conditions of Supply. In ordering a product covered by this document the
Customer agrees to be bound by those Terms & Conditions and nothing contained in this document constitutes or forms part
of a contract (with the exception of the contents of this Notice). A copy of Motorola’s Terms & Conditions of Supply is available
on request.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All
operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts.
Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed,
intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and !are registered trademarks
of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office.
This document supersedes any earlier documentation relating to the products referred to herein. The information contained
in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn.
© MOTOROLA LTD., 1995
All Trade Marks recognised. This document contains information on new products. Specifications and information herein are
subject to change without notice.
MC68HC05B6
High-density Complementary
Metal Oxide Semiconductor
(HCMOS) Microcomputer Unit
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CAUTION
This document includes descriptions of the various
self-check and bootstrap mechanisms that are
currently implemented as firmware in the non-user
ROM areas of the MC68HC05B6 and related devices.
As these firmware routines are intended primarily to
help Motorola’s engineers test the devices, they may
be changed or removed at any time.
For this reason, Motorola recommends that the
self-check and bootstrap routines are not called from
from the user software. Customers who do call these
routines from the user software do so at their own risk.
MC68HC05B6 MOTOROLA
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TABLE OF CONTENTS
Paragraph
Number
Page
NumberTitle
1
INTRODUCTION
1.1 Features................................................................................................................ 1-2
1.2 Mask options for the MC68HC05B6..................................................................... 1-2
2
MODES OF OPERATION AND PIN DESCRIPTIONS
2.1 Modes of operation...............................................................................................2-1
2.1.1 Single chip mode ............................................................................................ 2-1
2.1.2 Self-check mode............................................................................................. 2-1
2.2 Serial RAM loader ................................................................................................ 2-4
2.3 ‘Jump to any address’........................................................................................... 2-4
2.4 Low power modes................................................................................................. 2-7
2.4.1 STOP.............................................................................................................. 2-7
2.4.2 WAIT............................................................................................................... 2-9
2.4.2.1 Power consumption during WAIT mode.................................................... 2-9
2.4.3 SLOW mode.................................................................................................... 2-10
2.4.3.1 Miscellaneous register ............................................................................. 2-10
2.5 Pin descriptions ................................................................................................... 2-11
2.5.1 VDD and VSS................................................................................................. 2-11
2.5.2
IRQ ................................................................................................................. 2-11
2.5.3
RESET............................................................................................................ 2-11
2.5.4 TCAP1 ............................................................................................................ 2-11
2.5.5 TCAP2 ............................................................................................................ 2-12
2.5.6 TCMP1............................................................................................................2-12
2.5.7 TCMP2............................................................................................................2-12
2.5.8 OSC1, OSC2 .................................................................................................. 2-12
2.5.8.1 Crystal....................................................................................................... 2-12
2.5.8.2 Ceramic resonator..................................................................................... 2-12
2.5.8.3 External clock............................................................................................ 2-13
2.5.9 RDI (Receive data in)...................................................................................... 2-14
2.5.10 TDO (Transmit data out).................................................................................. 2-14
2.5.11 SCLK............................................................................................................... 2-14
MOTOROLA
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MC68HC05B6
Table of Contents (continued)
Paragraph
Number
Page
NumberTitle
2.5.12 PLMA...............................................................................................................2-14
2.5.13 PLMB...............................................................................................................2-14
2.5.14 VPP1................................................................................................................2-14
2.5.15 VRH.................................................................................................................2-14
2.5.16 VRL..................................................................................................................2-14
2.5.17 PA0 – PA7/PB0 – PB7/PC0 – PC7...................................................................2-14
2.5.18 PD0/AN0–PD7/AN7.........................................................................................2-14
3
MEMORY AND REGISTERS
3.1 Registers ...............................................................................................................3-1
3.2 RAM.......................................................................................................................3-1
3.3 ROM......................................................................................................................3-1
3.4 Self-check ROM ....................................................................................................3-2
3.5 EEPROM...............................................................................................................3-3
3.5.1 EEPROM control register ................................................................................3-3
3.5.2 EEPROM read operation.................................................................................3-5
3.5.3 EEPROM erase operation ...............................................................................3-5
3.5.4 EEPROM programming operation...................................................................3-6
3.5.5 Options register (OPTR)..................................................................................3-6
3.6 EEPROM during STOP mode...............................................................................3-7
3.7 EEPROM during WAIT mode................................................................................3-7
3.8 Miscellaneous register .........................................................................................3-9
4
INPUT/OUTPUT PORTS
4.1 Input/output programming .....................................................................................4-1
4.2 Ports A and B ........................................................................................................4-2
4.3 Port C ....................................................................................................................4-3
4.4 Port D ....................................................................................................................4-3
4.5 Port registers.........................................................................................................4-4
4.5.1 Port data registers A and B (PORTA and PORTB)..........................................4-4
4.5.2 Port data register C (PORTC)..........................................................................4-4
4.5.3 Port data register D (PORTD)..........................................................................4-5
4.5.3.1 A/D status/control register..........................................................................4-5
4.5.4 Data direction registers (DDRA, DDRB and DDRC)........................................4-5
4.6 Other port considerations......................................................................................4-6
MC68HC05B6 MOTOROLA
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Table of Contents (continued)
Paragraph
Number
Page
NumberTitle
5
PROGRAMMABLE TIMER
5.1 Counter................................................................................................................. 5-1
5.1.1 Counter register and alternate counter register ............................................ 5-3
5.2 Timer control and status....................................................................................... 5-4
5.2.1 Timer control register (TCR) ........................................................................... 5-4
5.2.2 Timer status register (TSR)............................................................................. 5-6
5.3 Input capture......................................................................................................... 5-7
5.3.1 Input capture register 1 (ICR1) ....................................................................... 5-7
5.3.2 Input capture register 2 (ICR2) ....................................................................... 5-8
5.4 Output compare.................................................................................................... 5-9
5.4.1 Output compare register 1 (OCR1)................................................................. 5-9
5.4.2 Output compare register 2 (OCR2)................................................................. 5-10
5.4.3 Software force compare.................................................................................. 5-11
5.5 Pulse Length Modulation (PLM) ........................................................................... 5-11
5.5.1 Pulse length modulation registers A and B (PLMA/PLMB) .......................... 5-11
5.6 Timer during STOP mode..................................................................................... 5-12
5.7 Timer during WAIT mode...................................................................................... 5-12
5.8 Timer state diagrams............................................................................................ 5-12
6
SERIAL COMMUNICATIONS INTERFACE
6.1 SCI two-wire system features............................................................................... 6-1
6.2 SCI receiver features............................................................................................ 6-3
6.3 SCI transmitter features........................................................................................ 6-3
6.4 Functional description........................................................................................... 6-3
6.5 Data format........................................................................................................... 6-5
6.6 Receiver wake-up operation................................................................................. 6-5
6.6.1 Idle line wake-up............................................................................................. 6-6
6.6.2 Address mark wake-up ................................................................................... 6-6
6.7 Receive data in (RDI) ........................................................................................... 6-6
6.8 Start bit detection.................................................................................................. 6-6
6.9 Transmit data out (TDO)....................................................................................... 6-8
6.10 SCI synchronous transmission............................................................................. 6-9
6.11 SCI registers......................................................................................................... 6-10
6.11.1 Serial communications data register (SCDR) ............................................... 6-10
6.11.2 Serial communications control register 1 (SCCR1) ...................................... 6-10
6.11.3 Serial communications control register 2 (SCCR2) ........................................ 6-14
6.11.4 Serial communications status register (SCSR) ............................................. 6-16
MOTOROLA
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MC68HC05B6
Table of Contents (continued)
Paragraph
Number
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6.11.5 Baud rate register (BAUD)...............................................................................6-18
6.12 Baud rate selection................................................................................................6-19
6.13 SCI during STOP mode.........................................................................................6-21
6.14 SCI during WAIT mode..........................................................................................6-21
7
PULSE LENGTH D/A CONVERTERS
7.1 Miscellaneous register ..........................................................................................7-3
7.2 PLM clock selection...............................................................................................7-4
7.3 PLM during STOP mode .......................................................................................7-4
7.4 PLM during WAIT mode........................................................................................7-4
8
ANALOG TO DIGITAL CONVERTER
8.1 A/D converter operation.........................................................................................8-1
8.2 A/D registers..........................................................................................................8-3
8.2.1 Port D data register (PORTD)..........................................................................8-3
8.2.2 A/D result data register (ADDATA)...................................................................8-3
8.2.3 A/D status/control register (ADSTAT)...............................................................8-4
8.3 A/D converter during STOP mode.........................................................................8-5
8.4 A/D converter during WAIT mode..........................................................................8-6
8.5 Port D analog input................................................................................................8-6
9
RESETS AND INTERRUPTS
9.1 Resets ...................................................................................................................9-1
9.1.1 Power-on reset.................................................................................................9-2
9.1.2 Miscellaneous register ...................................................................................9-2
9.1.3
RESET pin.......................................................................................................9-3
9.1.4 Computer operating properly (COP) watchdog reset.......................................9-3
9.1.4.1 COP watchdog during STOP mode...........................................................9-4
9.1.4.2 COP watchdog during WAIT mode............................................................9-4
9.1.5 Functions affected by reset..............................................................................9-5
9.2 Interrupts ...............................................................................................................9-6
9.2.1 Interrupt priorities.............................................................................................9-6
9.2.2 Nonmaskable software interrupt (SWI)............................................................9-6
9.2.3 Maskable hardware interrupts..........................................................................9-7
MC68HC05B6 MOTOROLA
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Table of Contents (continued)
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9.2.3.1 External interrupt (
IRQ)............................................................................. 9-7
9.2.3.2 Miscellaneous register ............................................................................. 9-9
9.2.3.3 Timer interrupts......................................................................................... 9-10
9.2.3.4 Serial communications interface (SCI) interrupts...................................... 9-10
9.2.4 Hardware controlled interrupt sequence......................................................... 9-11
10
CPU CORE AND INSTRUCTION SET
10.1 Registers............................................................................................................. 10-1
10.1.1 Accumulator (A) ............................................................................................ 10-2
10.1.2 Index register (X)........................................................................................... 10-2
10.1.3 Program counter (PC)................................................................................... 10-2
10.1.4 Stack pointer (SP)......................................................................................... 10-2
10.1.5 Condition code register (CCR)...................................................................... 10-2
10.2 Instruction set ..................................................................................................... 10-3
10.2.1 Register/memory Instructions ....................................................................... 10-4
10.2.2 Branch instructions ....................................................................................... 10-4
10.2.3 Bit manipulation instructions ......................................................................... 10-4
10.2.4 Read/modify/write instructions...................................................................... 10-4
10.2.5 Control instructions ....................................................................................... 10-4
10.2.6 Tables............................................................................................................ 10-4
10.3 Addressing modes.............................................................................................. 10-11
10.3.1 Inherent......................................................................................................... 10-11
10.3.2 Immediate..................................................................................................... 10-11
10.3.3 Direct............................................................................................................. 10-11
10.3.4 Extended....................................................................................................... 10-12
10.3.5 Indexed, no offset.......................................................................................... 10-12
10.3.6 Indexed, 8-bit offset....................................................................................... 10-12
10.3.7 Indexed, 16-bit offset..................................................................................... 10-12
10.3.8 Relative......................................................................................................... 10-13
10.3.9 Bit set/clear................................................................................................... 10-13
10.3.10 Bit test and branch........................................................................................ 10-13
MOTOROLA
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MC68HC05B6
Table of Contents (continued)
Paragraph
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Page
NumberTitle
11
ELECTRICAL SPECIFICATIONS
11.1 Maximum ratings ................................................................................................11-1
11.2 Thermal characteristics and power considerations .............................................11-2
11.3 DC electrical characteristics ..............................................................................11-3
11.3.1 I
DD
trends for 5V operation ...............................................................11-4
11.3.2 I
DD
trends for 3.3V operation ..............................................................11-7
11.4 A/D converter characteristics ...........................................................................11-9
11.5 Control timing ..............................................................................................11-11
12
MECHANICAL DATA
12.1 MC68HC05B6 pin configurations........................................................................12-1
12.1.1 52-pin plastic leaded chip carrier (PLCC) .....................................................12-1
12.1.2 64-pin quad flat pack (QFP) ..........................................................................12-2
12.1.3 56-pin shrink dual in line package (SDIP) ....................................................12-3
12.2 MC68HC05B6 mechanical dimensions...............................................................12-4
12.2.1 52-pin plastic leaded chip carrier (PLCC) .....................................................12-4
12.2.2 64-pin quad flat pack (QFP) .........................................................................12-5
12.2.3 56-pin shrink dual in line package (SDIP)......................................................12-6
13
ORDERING INFORMATION
13.1 EPROMS.............................................................................................................13-2
13.2 Verification media................................................................................................13-2
13.3 ROM verification units (RVU)...............................................................................13-2
MC68HC05B6 MOTOROLA
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Table of Contents (continued)
Paragraph
Number
Page
NumberTitle
A
MC68HC05B4
B
MC68HC05B8
C
MC68HC705B5
C.1 EPROM.................................................................................................................C-5
C.1.1 EPROM programming operation.....................................................................C-5
C.2 EPROM registers..................................................................................................C-6
C.2.1 EPROM control register ...............................................................................C-6
C.3 Options register (OPTR) ......................................................................................C-7
C.4 Bootstrap mode ....................................................................................................C-8
C.4.1 Erased EPROM verification ............................................................................C-11
C.4.2 EPROM parallel bootstrap load.......................................................................C-11
C.4.3 EPROM (RAM) serial bootstrap load and execute..........................................C-13
C.4.4 RAM parallel bootstrap load and execute .......................................................C-14
C.4.5 Bootstrap loader timing diagrams ............................................................C-17
C.5 DC electrical characteristics .................................................................................C-19
C.6 Control timing........................................................................................................C-19
D
MC68HC05B16
D.1 Self-check routines..............................................................................................D-1
E
MC68HC705B16
E.1 EPROM................................................................................................................. E-5
E.1.1 EPROM read operation...................................................................................E-5
E.1.2 EPROM program operation.............................................................................E-5
E.1.3 EPROM/EEPROM/ECLK control register .....................................................E-6
E.1.4 Mask option register ......................................................................................E-8
E.1.5 EEPROM options register (OPTR) ................................................................E-9
E.2 Bootstrap mode ....................................................................................................E-10
E.2.1 Erased EPROM verification ............................................................................E-13
MOTOROLA
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MC68HC05B6
Table of Contents (continued)
Paragraph
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Page
NumberTitle
E.2.2 EPROM/EEPROM parallel bootstrap.............................................................. E-13
E.2.3 EEPROM/EPROM/RAM serial bootstrap........................................................ E-16
E.2.4 RAM parallel bootstrap ...................................................................................E-19
E.2.4.1 Jump to start of RAM ($0050)................................................................... E-20
E.2.5 Maximum ratings ............................................................................................ E-21
E.2.6 Thermal characteristics and power considerations......................................... E-22
E.2.7 DC electrical characteristics ....................................................................... E-23
E.2.8 A/D converter characteristics .....................................................................E-26
E.3 Control timing ................................................................................................ E-28
F
MC68HC05B32
G
MC68HC705B32
G.1 EPROM ................................................................................................................G-5
G.1.1 EPROM read operation...................................................................................G-5
G.1.2 EPROM program operation ............................................................................G-5
G.1.3 EPROM/EEPROM control register ...............................................................G-6
G.1.4 Mask option register .....................................................................................G-8
G.1.5 Options register (OPTR) ...............................................................................G-9
G.2 Bootstrap mode....................................................................................................G-10
G.2.1 Erased EPROM verification............................................................................G-13
G.2.2 EPROM/EEPROM parallel bootstrap..............................................................G-13
G.2.3 Serial RAM loader...........................................................................................G-16
G.2.3.1 Jump to start of RAM ($0051)...................................................................G-16
G.2.4 Maximum ratings ............................................................................................G-19
G.2.5 Thermal characteristics and power considerations.........................................G-20
G.2.6 DC electrical characteristics ......................................................................G-21
G.2.7 A/D converter characteristics ....................................................................G-24
G.2.8 Control timing ..........................................................................................G-26
H
HIGH SPEED OPERATION
H.1 DC electrical characteristics ............................................................................... H-2
H.2 A/D converter characteristics ..............................................................................H-3
H.3 Control timing for 5V operation .......................................................................H-4
MC68HC05B6 MOTOROLA
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LIST OF FIGURES
Figure
Number
Page
NumberTitle
1-1 MC68HC05B6 block diagram.................................................................................1-3
2-1 MC68HC05B6 self-check schematic diagram........................................................2-3
2-2 MC68HC05B6 ‘load program in RAM and execute’ schematic diagram ................2-5
2-3 MC68HC05B6 ‘jump to any address’ schematic diagram......................................2-6
2-4 STOP and WAIT flowcharts....................................................................................2-8
2-5 Slow mode divider block diagram...........................................................................2-10
2-6 Oscillator connections ............................................................................................2-13
3-1 Memory map of the MC68HC05B6 ........................................................................3-2
4-1 Standard I/O port structure.....................................................................................4-2
4-2 ECLK timing diagram..............................................................................................4-3
4-3 Port logic levels.......................................................................................................4-6
5-1 16-bit programmable timer block diagram ..............................................................5-2
5-2 Timer state timing diagram for reset.......................................................................5-13
5-3 Timer state timing diagram for input capture..........................................................5-13
5-4 Timer state timing diagram for output compare......................................................5-14
5-5 Timer state timing diagram for timer overflow.........................................................5-14
6-1 Serial communications interface block diagram......................................................6-2
6-2 SCI rate generator division.....................................................................................6-4
6-3 Data format.............................................................................................................6-5
6-4 SCI examples of start bit sampling technique ........................................................6-7
6-5 SCI sampling technique used on all bits.................................................................6-7
6-6 Artificial start following a framing error ...................................................................6-8
6-7 SCI start bit following a break.................................................................................6-8
6-8 SCI example of synchronous and asynchronous transmission..............................6-9
6-9 SCI data clock timing diagram (M=0) .....................................................................6-12
6-10 SCI data clock timing diagram (M=1) .....................................................................6-13
7-1 PLM system block diagram.....................................................................................7-1
7-2 PLM output waveform examples.............................................................................7-2
7-3 PLM clock selection................................................................................................7-4
8-1 A/D converter block diagram..................................................................................8-2
8-2 Electrical model of an A/D input pin........................................................................8-6
9-1 Reset timing diagram..............................................................................................9-1
9-2 Watchdog system block diagram............................................................................9-3
9-3 Interrupt flow chart..................................................................................................9-8
MOTOROLA
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MC68HC05B6
LIST OF FIGURES (continued)
Figure
Number
Page
NumberTitle
10-1 Programming model.............................................................................................10-1
10-2 Stacking order......................................................................................................10-1
11-1 Equivalent test load..............................................................................................11-2
11-2 Run I
DD
vs internal operating frequency (4.5V, 5.5V) ..........................................11-4
11-3 Run I
DD
(SM = 1) vs internal operating frequency (4.5V, 5.5V) ...........................11-4
11-4 Wait I
DD
vs internal operating frequency (4.5V, 5.5V)..........................................11-4
11-5 Wait I
DD
(SM = 1) vs internal operating frequency (4.5V, 5.5V)...........................11-5
11-6 Increase in I
DD
vs frequency for A/D, SCI systems active, VDD = 5.5V...............11-5
11-7 I
DD
vs mode vs internal operating frequency, VDD = 5.5V ...................................11-5
11-8 Run I
DD
vs internal operating frequency (3V, 3.6V).............................................11-7
11-9 Run I
DD
(SM = 1) vs internal operating frequency (3V,3.6V) ...............................11-7
11-10 Wait I
DD
vs internal operating frequency (3V, 3.6V).............................................11-7
11-11 Wait I
DD
(SM = 1) vs internal operating frequency (3V, 3.6V)..............................11-8
11-12 Increase in I
DD
vs frequency for A/D, SCI systems active, VDD = 3.6V................11-8
11-13 I
DD
vs mode vs internal operating frequency, VDD = 3.6V ...................................11-8
11-14 Timer relationship.................................................................................................11-13
12-1 52-pin PLCC pinout..............................................................................................12-1
12-2 64-pin QFP pinout................................................................................................12-2
12-3 56-pin SDIP pinout...............................................................................................12-3
12-4 52-pin PLCC mechanical dimensions ..................................................................12-4
12-5 64-pin QFP mechanical dimensions.....................................................................12-5
12-6 56-pin SDIP mechanical dimensions....................................................................12-6
A-1 MC68HC05B4 block diagram.................................................................................A-2
A-2 Memory map of the MC68HC05B4........................................................................A-3
B-1 MC68HC05B8 block diagram.................................................................................B-2
B-2 Memory map of the MC68HC05B8........................................................................B-3
C-1 MC68HC705B5 block diagram.............................................................................. C-2
C-2 Memory map of the MC68HC705B5..................................................................... C-3
C-3 Modes of operation flow chart (1 of 2)................................................................... C-9
C-4 Modes of operation flow chart (2 of 2)................................................................... C-10
C-5 Timing diagram with handshake............................................................................ C-11
C-6 EPROM(RAM) parallel bootstrap schematic diagram........................................... C-12
C-7 EPROM (RAM) serial bootstrap schematic diagram............................................. C-15
C-8 RAM parallel bootstrap schematic diagram........................................................... C-16
C-9 EPROM parallel bootstrap loader timing diagram................................................. C-17
C-10 RAM parallel loader timing diagram..................................................................... C-18
D-1 MC68HC05B16 block diagram.............................................................................. D-2
D-2 Memory map of the MC68HC05B16..................................................................... D-3
E-1 MC68HC705B16 block diagram.............................................................................E-2
E-2 Memory map of the MC68HC705B16....................................................................E-3
MC68HC05B6 MOTOROLA
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LIST OF FIGURES (continued)
Figure
Number
Page
NumberTitle
E-3 Modes of operation flow chart (1 of 2)................................................................... E-11
E-4 Modes of operation flow chart (2 of 2)................................................................... E-12
E-5 Timing diagram with handshake............................................................................ E-13
E-6 Parallel EPROM loader timing diagram................................................................. E-14
E-7 EPROM Parallel bootstrap schematic diagram......................................................E-15
E-8 RAM/EPROM/EEPROM serial bootstrap schematic diagram............................... E-17
E-9 Parallel RAM loader timing diagram...................................................................... E-19
E-10 RAM parallel bootstrap schematic diagram........................................................... E-20
E-11 Equivalent test load ............................................................................................... E-22
E-12 Timer relationship.................................................................................................. E-30
F-1 MC68HC05B32 block diagram...............................................................................F-2
F-2 Memory map of the MC68HC05B32......................................................................F-3
G-1 MC68HC705B32 block diagram............................................................................G-2
G-2 Memory map of the MC68HC705B32...................................................................G-3
G-3 Modes of operation flow chart (1 of 2)...................................................................G-11
G-4 Modes of operation flow chart (2 of 2)...................................................................G-12
G-5 Timing diagram with handshake............................................................................G-14
G-6 Parallel EPROM loader timing diagram.................................................................G-14
G-7 EPROM parallel bootstrap schematic diagram......................................................G-15
G-8 RAM load and execute schematic diagram...........................................................G-17
G-9 Parallel RAM loader timing diagram......................................................................G-18
G-10 Equivalent test load...............................................................................................G-20
G-11 Timer relationship..................................................................................................G-28
H-1 Timer relationship.................................................................................................. H-4
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MOTOROLA
xii
MC68HC05B6
MC68HC05B6 MOTOROLA
xiii
LIST OF TABLES
Table
Number
Page
NumberTitle
1-1 Data sheet appendices...........................................................................................1-1
2-1 Mode of operation selection ...................................................................................2-1
2-2 MC68HC05B6 self-check results............................................................................2-2
3-1 EEPROM control bits description...........................................................................3-4
3-2 Register outline.......................................................................................................3-8
3-3
IRQ sensitivity.........................................................................................................3-9
4-1 I/O pin states ..........................................................................................................4-2
6-1 Method of receiver wake-up...................................................................................6-11
6-2 SCI clock on SCLK pin...........................................................................................6-13
6-3 First prescaler stage...............................................................................................6-18
6-4 Second prescaler stage (transmitter) .....................................................................6-18
6-5 Second prescaler stage (receiver)..........................................................................6-19
6-6 SCI baud rate selection..........................................................................................6-20
8-1 A/D clock selection.................................................................................................8-4
8-2 A/D channel assignment.........................................................................................8-5
9-1 Effect of
RESET, POR, STOP and WAIT................................................................9-5
9-2 Interrupt priorities ...................................................................................................9-7
9-3
IRQ sensitivity.........................................................................................................9-9
10-1 MUL instruction.....................................................................................................10-5
10-2 Register/memory instructions...............................................................................10-5
10-3 Branch instructions...............................................................................................10-6
10-4 Bit manipulation instructions.................................................................................10-6
10-5 Read/modify/write instructions .............................................................................10-7
10-6 Control instructions...............................................................................................10-7
10-7 Instruction set (1 of 2)...........................................................................................10-8
10-8 Instruction set (2 of 2)...........................................................................................10-9
10-9 M68HC05 opcode map.........................................................................................10-10
11-1 Maximum ratings..................................................................................................11-1
11-2 Package thermal characteristics...........................................................................11-2
11-3 DC electrical characteristics for 5V operation.......................................................11-3
11-4 DC electrical characteristics for 3.3V operation....................................................11-6
11-5 A/D characteristics for 5V operation.....................................................................11-9
11-6 A/D characteristics for 3.3V operation..................................................................11-10
11-7 Control timing for 5V operation.............................................................................11-11
11-8 Control timing for 3.3V operation..........................................................................11-12
MOTOROLA
xiv
MC68HC05B6
LIST OF TABLES (continued)
Table
Number
Page
NumberTitle
13-1 MC order numbers ...............................................................................................13-1
13-2 EPROMs for pattern generation...........................................................................13-2
A-1 Register outline ......................................................................................................A-4
B-1 Register outline ......................................................................................................B-4
C-1 Register outline ..................................................................................................... C-4
C-2 Mode of operation selection.................................................................................. C-8
C-3 Bootstrap vector targets in RAM............................................................................C-14
C-4 Additional DC electrical characteristics for MC68HC705B5.................................. C-19
C-5 Additional control timing for MC68HC705B5......................................................... C-19
D-1 Register outline ..................................................................................................... D-4
E-1 Register outline ......................................................................................................E-4
E-2 EPROM control bits description .............................................................................E-6
E-3 EEPROM control bits description...........................................................................E-7
E-4 Mode of operation selection ...................................................................................E-10
E-5 Bootstrap vector targets in RAM.............................................................................E-18
E-6 Maximum ratings....................................................................................................E-21
E-7 Package thermal characteristics.............................................................................E-22
E-8 DC electrical characteristics for 5V operation ........................................................E-23
E-9 DC electrical characteristics for 3.3V operation .....................................................E-25
E-10 A/D characteristics for 5V operation.......................................................................E-26
E-11 A/D characteristics for 3.3V operation....................................................................E-27
E-12 Control timing for 5V operation...............................................................................E-28
E-13 Control timing for 3.3V operation............................................................................E-29
F-1 Register outline......................................................................................................F-4
G-1 Register outline.....................................................................................................G-4
G-2 EPROM control bits description ............................................................................G-6
G-3 EEPROM control bits description..........................................................................G-7
G-4 Mode of operation selection.................................................................................. G-10
G-5 Bootstrap vector targets in RAM............................................................................G-16
G-6 Maximum ratings...................................................................................................G-19
G-7 Package thermal characteristics............................................................................G-20
G-8 DC electrical characteristics for 5V operation .......................................................G-21
G-9 DC electrical characteristics for 3.3V operation ....................................................G-23
G-10 A/D characteristics for 5V operation...................................................................... G-24
G-11 A/D characteristics for 3.3V operation................................................................... G-25
G-12 Control timing for 5V operation.............................................................................. G-26
G-13 Control timing for operation at 3.3V....................................................................... G-27
H-1 Ordering information.............................................................................................. H-1
H-2 DC electrical characteristics for 5V operation .......................................................H-2
H-3 A/D characteristics for 5V operation...................................................................... H-3
MC68HC05B6 MOTOROLA
1-1
INTRODUCTION
1
1
INTRODUCTION
The MC68HC05B6 microcomputer (MCU) is a member of Motorola’s MC68HC05 family of
low-cost single chip microcomputers. This 8-bit MCU contains an on-chip oscillator, CPU, RAM,
ROM, EEPROM, A/D converter, pulse length modulated outputs, I/O, serial communications
interface, programmable timer system and watchdog. The fully static design allows operation at
frequencies down to dc to further reduce the already low power consumption to a few micro-amps.
This data sheet is structured such that devices similar to the MC68HC05B6 are described in a set
of appendices (see Table 1-1).
Table 1-1 Data sheet appendices
Device Appendix Differences from MC68HC05B6
MC68HC05B4 A 4K bytes ROM; no EEPROM
MC68HC05B8 B 7.25K bytes ROM
MC68HC705B5 C
6K bytes EPROM; self-check replaced by bootstrap
firmware; no EEPROM
MC68HC05B16 D 16K bytes ROM; increased RAM and self-check ROM
MC68HC705B16 E
16K bytes EPROM; increased RAM; self-check replaced
by bootstrap firmware; modified power-on reset routine
MC68HC05B32 F 32K bytes ROM; no page zero ROM; increased RAM
MC68HC705B32 G
32K bytes EPROM; no page zero ROM; increased RAM;
self-check mode replaced by bootstrap firmware
MOTOROLA
1-2
MC68HC05B6INTRODUCTION
1
1.1 Features
Hardware features
• Fully static design featuring the industry standard M68HC05 family CPU core
• On chip crystal oscillator with divide by 2 or a software selectable divide by 32 option (SLOW
mode)
• 2.1 MHz internal operating frequency at 5V; 1.0 MHz at 3V
• 176 bytes of RAM
• 5936 bytes of user ROM plus 14 bytes of user vectors
• 256 bytes of byte erasable EEPROM with internal charge pump and security bit
• Write/erase protect bit for 224 of the 256 bytes EEPROM
• Self test/bootstrap mode
• Power saving STOP, WAIT and SLOW modes
• Three 8-bit parallel I/O ports and one 8-bit input-only port
• Software option available to output the internal E-clock to port pin PC2
• 16-bit timer with 2 input captures and 2 output compares
• Computer operating properly (COP) watchdog timer
• Serial communications interface system (SCI) with independent transmitter/receiver baud rate
selection; receiver wake-up function for use in multi-receiver systems
• 8 channel A/D converter
• 2 pulse length modulation systems which can be used as D/A converters
• One interrupt request input plus 4 on-board hardware interrupt sources
• Available in 52-pin plastic leaded chip carrier (PLCC), 64-pin quad flat pack (QFP) and 56-pin
shrink dual in line (SDIP) packages
• Complete development system support available using the MMDS05 de velopment station with
the M68HC05BEM emulation module or the M68HC05BEVS evaluation system
1.2 Mask options for the MC68HC05B6
The MC68HC05B6 has three mask options that are programmed during manufacture and must
be specified on the order form.
• Power-on-reset delay (t
PORL
) = 16 or 4064 cycles
MC68HC05B6 MOTOROLA
1-3
INTRODUCTION
1
• Automatic watchdog enable/disable following a power-on or external reset
• Watchdog enable/disable during WAIT mode
Warning: It is recommended that an external clock is alw ays used if t
PORL
is set to 16 cycles. This
will prevent any problems arising with oscillator stability when the device is put into
STOP mode.
Figure 1-1 MC68HC05B6 block diagram
Port A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Port B
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Port C
PC0
PC1
PC2/ECLK
PC3
PC4
PC5
PC6
PC7
16-bit
programmable
timer
Port D
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
Oscillator
176 bytes
RAM
COP watchdog
RESET
IRQ
VDD
VSS
OSC1
OSC2
M68HC05
CPU
SCI
A/D converter
PLM
TCAP1
TCAP2
TCMP1
TCMP2
VRH
VRL
RDI
SCLK
TDO
VPP1
256 bytes
EEPROM
Charge pump
2 / 32
PLMA D/A
PLMB D/A
8-bit
432 bytes
User ROM
5950 bytes
self check ROM
(including 14 bytes
User vectors)
MOTOROLA
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MC68HC05B6INTRODUCTION
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1
MC68HC05B6 MOTOROLA
2-1
MODES OF OPERATION AND PIN DESCRIPTIONS
2
2
MODES OF OPERATION AND PIN
DESCRIPTIONS
2.1 Modes of operation
The MC68HC05B6 MCU has two modes of operation, namely single chip and self check modes.
Table 2-1 shows the conditions required to enter each mode on the rising edge of
RESET.
2.1.1 Single chip mode
This is the normal operating mode of the MC68HC05B6. In this mode the device functions as a
self-contained microcomputer (MCU) with all on-board peripherals, including the three 8-bit I/O
ports and the 8-bit input-only port, available to the user. All address and data activity occurs within
the MCU.
2.1.2 Self-check mode
The self-check function available on the MC68HC05B6 provides an internal capability to
determine if the device is functional. Self-check is performed using the circuit shown in Figure 2-1.
Port C pins PC0–PC3 are monitored for the self-check results (light emitting diodes are shown but
other devices could be used), and are interpreted as described in Table 2-2. The self-check mode
Table 2-1 Mode of operation selection
IRQ pin TCAP1 pin PD3 PD4 Mode
VSS to VDDVSS to V
DD
X X Single chip
2V
DD
V
DD
0 X Self-check
2V
DD
V
DD
1 0 Serial RAM loader
2V
DD
V
DD
1 1 Jump to any address
MOTOROLA
2-2
MC68HC05B6MODES OF OPERATION AND PIN DESCRIPTIONS
2
is entered by applying 2 x VDD dc (via a 4.7k resistor) to the IRQ pin and 5V dc input (via a 4.7k
resistor) to the TCAP1 pin and then depressing the reset switch to execute a reset. After reset, the
following tests are performed automatically and once completed they continually repeat. A good
device will exhibit flashing LEDs; a bad device will be indicated by the LEDs holding at one value.
I/0 — Functionally exercises ports A, B, C and D
RAM — Counter test for each RAM byte
ROM — Exclusive OR with odd ones parity result
Timer — Tracks counter registers and checks ICF1, ICF2, OCF1,
OCF2 and TOF flags
SCI — Transmission test; check for RDRF, TDRE, TC and FE
flags
A/D — Check A/D functionality on internal channels: VRL, VRH
and (VRL + VRH)/2
EEPROM — This test is optional; it executes a write/erase test of the
256 bytes EEPROM (available only for the MC68HC05B6
version), and then deactivates the security bit.
PLM — Checks the PLM basic functionality
Interrupts — Tests external timer and SCI interrupts
Watchdog — Tests the watchdog
Table 2-2 MC68HC05B6 self-check results
PC3 PC2 PC1 PC0 Remarks
1 0 0 1 Bad port
0 1 1 0 Bad port
1 0 1 0 Bad RAM
1 0 1 1 Bad ROM
1 1 0 0 Bad Timer
1 1 0 1 Bad SCI
1 1 1 0 Bad A/D
0 0 0 0 Bad EEPROM (or other if B4)
0 0 0 1 Bad PLM
0 0 1 0 Bad interrupts
0 0 1 1 Bad watchdog
Flashing Good device
All others Bad device, bad port etc.
‘0’ indicates LED on; ‘1’ indicates LED off
MC68HC05B6 MOTOROLA
2-3
MODES OF OPERATION AND PIN DESCRIPTIONS
2
Figure 2-1 MC68HC05B6 self-check schematic diagram
6
40
51
OSC1
OSC2
IRQ
TCAP2
TCMP2
TCAP1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
VRLVSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
TCMP1
SCLK
PLMB
PLMA
TDO
RDI
VPP1
NC
RESET
NC VRH VDD
18
50
52
20
21
2
3
4
5
9
11
12
13
14
24
25
26
27
28
29
30
31
16
17
19
23
1
22
32
33
34
35
36
37
38
39
42
43
44
45
46
47
48
49
41 7
0.01 F
10 nF 47 F
10 M
4 MHz
22 pF
4k7
4k7
680
22 pF
4k7
4k7
680
680
680
BC239
P1
GND
+5V
2xV
DD
RESET
EEPROM tested
EEPROM not tested
15 8 10
Note:
For the MC68HC05B4, switches on PB5 and PB6 have no effect
All resistors are 10 k, unless otherwise stated.
MC68HC05B6 (52-pin package)
MOTOROLA
2-4
MC68HC05B6MODES OF OPERATION AND PIN DESCRIPTIONS
2
2.2 Serial RAM loader
The ‘load program in RAM and execute’ mode is entered if the following conditions are satisfied
when the reset pin is released to V
DD
. The format used is identical to the format used for the
MC68HC805C4. The SEC bit in the options register must be inactive, i.e. set to ‘1’.
–
IRQ at 2xV
DD
– TCAP1 at V
DD
– PD3 at VDD for at least 30 machine cycles after reset
– PD4 at V
SS
for at least 30 machine cycles after reset
In the ‘load program in RAM and execute’ routine, user programs are loaded into MCU RAM via
the SCI port and then executed. Data is loaded sequentially, starting at RAM location $0050, until
the last byte is loaded. Program control is then transferred to the RAM program starting at location
$0051. The first byte loaded is the count of the total number of bytes in the program plus the count
byte. The program starts at the second byte in RAM. During the firmware initialization stage, the
SCI is configured for the NRZ data format (idle line, start bit, eight data bits and stop bit). The baud
rate is 9600 with a 4 MHz crystal. A program to convert ASCII S-records to the format required by
the RAM loader is available from Motorola.
If immediate execution is not desired after loading the RAM program, it is possible to hold off
execution. This is accomplished b y setting the byte count to a v alue that is greater than the o verall
length of the loaded data. When the last byte is loaded, the firmware will halt operation expecting
additional data to arrive. At this point, the reset switch is placed in the reset position which will
reset the MCU, but keep the RAM program intact. All routines can now be entered from this state,
including the one which will execute the program in RAM (see Section 2.3).
To load a program in the EEPROM, the ‘load program in RAM and execute’ function is also used.
In this instance the process involves two distinct steps. Firstly, the RAM is loaded with a program
which will control the loading of the EEPROM, and when the RAM contents are executed, the
MCU is instructed to load the EEPROM.
The erased state of the EEPROM is $FF.
Figure 2-2 shows the schematic diagram of the circuit required for the serial RAM loader.
2.3 ‘Jump to any address’
The ‘jump to any address’ mode is entered when the reset pin is released to VDD, if the following
conditions are satisfied:
–
IRQ at 2xV
DD
– TCAP1 at V
DD
– PD3 at VDD for at least 30 machine cycles after reset
– PD4 at V
DD
for at least 30 machine cycles after reset
MC68HC05B6 MOTOROLA
2-5
MODES OF OPERATION AND PIN DESCRIPTIONS
2
This function allows execution of programs previously loaded in RAM or EEPROM using the
methods outlined in Section 2.2.
To execute the ‘jump to any address’ function, data input at port A has to be $CC and data input at
port B and port C should represent the MSB and LSB respectively, of the address to jump to for
execution of the user program. A schematic diagram of the circuit required is shown inFigure 2-3.
Figure 2-2 MC68HC05B6 ‘load program in RAM and execute’ schematic diagram
32
OSC1
OSC2
IRQ
TCAP2
TCMP2
TCAP1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET
VDD
18
24
25
26
27
28
29
30
31
16
17
19
41
10 k
0.01 F
10 nF 47 F
10 M
4 MHz
22 pF
10 k
22 pF
P1
GND
+5V
2xV
DD
RESET
10
VRH
VRL
VPP1
PLMA
PLMB
TCMP1
RDI
TDO
NC
NC
RS232 level translator
suggested:
MC145406 or MAX232
9600 Bd
RS232
SCLK
10 k
10 k
10 k
11
9
22
8
7
40
20
21
51
1
23
2
3
4
5
12
13
14
33
34
35
36
37
38
39
42
43
44
45
46
47
48
49
6
15
50
52
optional
3 x 10 k
Connect as required
for the application
Connect as required
for the application
MC68HC05B6 (52-pin package)
MOTOROLA
2-6
MC68HC05B6MODES OF OPERATION AND PIN DESCRIPTIONS
2
Figure 2-3 MC68HC05B6 ‘jump to any address’ schematic diagram
32
OSC1
OSC2
IRQ
TCAP2
TCMP2
TCAP1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET
VDD
18
24
25
26
27
28
29
30
31
16
17
19
41
10 k
0.01 F
10 nF 47 F
10 M
4 MHz
22 pF
10 k
22 pF
P1
GND
+5V
2xV
DD
RESET
10
VRH
VRL
VPP1
PLMA
PLMB
TCMP1
RDI
TDO
NC
NC
SCLK
10 k
10 k
10 k
11
9
22
8
7
40
20
21
51
1
23
2
3
4
5
12
13
14
33
34
35
36
37
38
39
42
43
44
45
46
47
48
49
6
15
50
52
optional
3 x 10 k
Connect as required
for the application
8 x 10 k optional (see note)
8 x 10 k
8 x 10 k
MSBLSB
Select required address
Note:
These eight resistors are optional; direct connection is possible if pins PA0-PA7, PB0-PB7 and PC0-PC7 are
kept in input mode during application.
MC68HC05B6 (52-pin package)
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