Datasheet MC68HC705B5CFN, MC68HC705B5FN, MC68HC705B5MFN, MC68HC705B5VFN, MC68HC705B32FU Datasheet (Motorola)
...
HC05
MC68HC05B6/D
Rev. 3
MC68HC05B4
MC68HC705B5
MC68HC05B6
MC68HC05B8
MC68HC05B16
MC68HC705B16
MC68HC05B32
MC68HC705B32
TECHNICAL
DATA
MC68HC05B6
!MOTOROLA
TECHNICAL DATA
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INTRODUCTION
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
INPUT/OUTPUT PORTS
PROGRAMMABLE TIMER
SERIAL COMMUNICATIONS INTERFACE
PULSE LENGTH D/A CONVERTERS
ANALOG TO DIGITAL CONVERTER
RESETS AND INTERRUPTS
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
ORDERING INFORMATION
APPENDICES
HIGH SPEED OPERATION
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INTRODUCTION
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
INPUT/OUTPUT PORTS
PROGRAMMABLE TIMER
SERIAL COMMUNICATIONS INTERFACE
PULSE LENGTH D/A CONVERTERS
ANALOG TO DIGITAL CONVERTER
RESETS AND INTERRUPTS
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
ORDERING INFORMATION
MC68HC05B4
HIGH SPEED OPERATION
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All products are sold on Motorola’s Terms & Conditions of Supply. In ordering a product covered by this document the
Customer agrees to be bound by those Terms & Conditions and nothing contained in this document constitutes or forms part
of a contract (with the exception of the contents of this Notice). A copy of Motorola’s Terms & Conditions of Supply is available
on request.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All
operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts.
Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed,
intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and !are registered trademarks
of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office.
This document supersedes any earlier documentation relating to the products referred to herein. The information contained
in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn.
© MOTOROLA LTD., 1995
All Trade Marks recognised. This document contains information on new products. Specifications and information herein are
subject to change without notice.
MC68HC05B6
High-density Complementary
Metal Oxide Semiconductor
(HCMOS) Microcomputer Unit
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CAUTION
This document includes descriptions of the various
self-check and bootstrap mechanisms that are
currently implemented as firmware in the non-user
ROM areas of the MC68HC05B6 and related devices.
As these firmware routines are intended primarily to
help Motorola’s engineers test the devices, they may
be changed or removed at any time.
For this reason, Motorola recommends that the
self-check and bootstrap routines are not called from
from the user software. Customers who do call these
routines from the user software do so at their own risk.
MC68HC05B6 MOTOROLA
i
TABLE OF CONTENTS
Paragraph
Number
Page
NumberTitle
1
INTRODUCTION
1.1 Features................................................................................................................ 1-2
1.2 Mask options for the MC68HC05B6..................................................................... 1-2
2
MODES OF OPERATION AND PIN DESCRIPTIONS
2.1 Modes of operation...............................................................................................2-1
2.1.1 Single chip mode ............................................................................................ 2-1
2.1.2 Self-check mode............................................................................................. 2-1
2.2 Serial RAM loader ................................................................................................ 2-4
2.3 ‘Jump to any address’........................................................................................... 2-4
2.4 Low power modes................................................................................................. 2-7
2.4.1 STOP.............................................................................................................. 2-7
2.4.2 WAIT............................................................................................................... 2-9
2.4.2.1 Power consumption during WAIT mode.................................................... 2-9
2.4.3 SLOW mode.................................................................................................... 2-10
2.4.3.1 Miscellaneous register ............................................................................. 2-10
2.5 Pin descriptions ................................................................................................... 2-11
2.5.1 VDD and VSS................................................................................................. 2-11
2.5.2
IRQ ................................................................................................................. 2-11
2.5.3
RESET............................................................................................................ 2-11
2.5.4 TCAP1 ............................................................................................................ 2-11
2.5.5 TCAP2 ............................................................................................................ 2-12
2.5.6 TCMP1............................................................................................................2-12
2.5.7 TCMP2............................................................................................................2-12
2.5.8 OSC1, OSC2 .................................................................................................. 2-12
2.5.8.1 Crystal....................................................................................................... 2-12
2.5.8.2 Ceramic resonator..................................................................................... 2-12
2.5.8.3 External clock............................................................................................ 2-13
2.5.9 RDI (Receive data in)...................................................................................... 2-14
2.5.10 TDO (Transmit data out).................................................................................. 2-14
2.5.11 SCLK............................................................................................................... 2-14
MOTOROLA
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MC68HC05B6
Table of Contents (continued)
Paragraph
Number
Page
NumberTitle
2.5.12 PLMA...............................................................................................................2-14
2.5.13 PLMB...............................................................................................................2-14
2.5.14 VPP1................................................................................................................2-14
2.5.15 VRH.................................................................................................................2-14
2.5.16 VRL..................................................................................................................2-14
2.5.17 PA0 – PA7/PB0 – PB7/PC0 – PC7...................................................................2-14
2.5.18 PD0/AN0–PD7/AN7.........................................................................................2-14
3
MEMORY AND REGISTERS
3.1 Registers ...............................................................................................................3-1
3.2 RAM.......................................................................................................................3-1
3.3 ROM......................................................................................................................3-1
3.4 Self-check ROM ....................................................................................................3-2
3.5 EEPROM...............................................................................................................3-3
3.5.1 EEPROM control register ................................................................................3-3
3.5.2 EEPROM read operation.................................................................................3-5
3.5.3 EEPROM erase operation ...............................................................................3-5
3.5.4 EEPROM programming operation...................................................................3-6
3.5.5 Options register (OPTR)..................................................................................3-6
3.6 EEPROM during STOP mode...............................................................................3-7
3.7 EEPROM during WAIT mode................................................................................3-7
3.8 Miscellaneous register .........................................................................................3-9
4
INPUT/OUTPUT PORTS
4.1 Input/output programming .....................................................................................4-1
4.2 Ports A and B ........................................................................................................4-2
4.3 Port C ....................................................................................................................4-3
4.4 Port D ....................................................................................................................4-3
4.5 Port registers.........................................................................................................4-4
4.5.1 Port data registers A and B (PORTA and PORTB)..........................................4-4
4.5.2 Port data register C (PORTC)..........................................................................4-4
4.5.3 Port data register D (PORTD)..........................................................................4-5
4.5.3.1 A/D status/control register..........................................................................4-5
4.5.4 Data direction registers (DDRA, DDRB and DDRC)........................................4-5
4.6 Other port considerations......................................................................................4-6
MC68HC05B6 MOTOROLA
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Table of Contents (continued)
Paragraph
Number
Page
NumberTitle
5
PROGRAMMABLE TIMER
5.1 Counter................................................................................................................. 5-1
5.1.1 Counter register and alternate counter register ............................................ 5-3
5.2 Timer control and status....................................................................................... 5-4
5.2.1 Timer control register (TCR) ........................................................................... 5-4
5.2.2 Timer status register (TSR)............................................................................. 5-6
5.3 Input capture......................................................................................................... 5-7
5.3.1 Input capture register 1 (ICR1) ....................................................................... 5-7
5.3.2 Input capture register 2 (ICR2) ....................................................................... 5-8
5.4 Output compare.................................................................................................... 5-9
5.4.1 Output compare register 1 (OCR1)................................................................. 5-9
5.4.2 Output compare register 2 (OCR2)................................................................. 5-10
5.4.3 Software force compare.................................................................................. 5-11
5.5 Pulse Length Modulation (PLM) ........................................................................... 5-11
5.5.1 Pulse length modulation registers A and B (PLMA/PLMB) .......................... 5-11
5.6 Timer during STOP mode..................................................................................... 5-12
5.7 Timer during WAIT mode...................................................................................... 5-12
5.8 Timer state diagrams............................................................................................ 5-12
6
SERIAL COMMUNICATIONS INTERFACE
6.1 SCI two-wire system features............................................................................... 6-1
6.2 SCI receiver features............................................................................................ 6-3
6.3 SCI transmitter features........................................................................................ 6-3
6.4 Functional description........................................................................................... 6-3
6.5 Data format........................................................................................................... 6-5
6.6 Receiver wake-up operation................................................................................. 6-5
6.6.1 Idle line wake-up............................................................................................. 6-6
6.6.2 Address mark wake-up ................................................................................... 6-6
6.7 Receive data in (RDI) ........................................................................................... 6-6
6.8 Start bit detection.................................................................................................. 6-6
6.9 Transmit data out (TDO)....................................................................................... 6-8
6.10 SCI synchronous transmission............................................................................. 6-9
6.11 SCI registers......................................................................................................... 6-10
6.11.1 Serial communications data register (SCDR) ............................................... 6-10
6.11.2 Serial communications control register 1 (SCCR1) ...................................... 6-10
6.11.3 Serial communications control register 2 (SCCR2) ........................................ 6-14
6.11.4 Serial communications status register (SCSR) ............................................. 6-16
MOTOROLA
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MC68HC05B6
Table of Contents (continued)
Paragraph
Number
Page
NumberTitle
6.11.5 Baud rate register (BAUD)...............................................................................6-18
6.12 Baud rate selection................................................................................................6-19
6.13 SCI during STOP mode.........................................................................................6-21
6.14 SCI during WAIT mode..........................................................................................6-21
7
PULSE LENGTH D/A CONVERTERS
7.1 Miscellaneous register ..........................................................................................7-3
7.2 PLM clock selection...............................................................................................7-4
7.3 PLM during STOP mode .......................................................................................7-4
7.4 PLM during WAIT mode........................................................................................7-4
8
ANALOG TO DIGITAL CONVERTER
8.1 A/D converter operation.........................................................................................8-1
8.2 A/D registers..........................................................................................................8-3
8.2.1 Port D data register (PORTD)..........................................................................8-3
8.2.2 A/D result data register (ADDATA)...................................................................8-3
8.2.3 A/D status/control register (ADSTAT)...............................................................8-4
8.3 A/D converter during STOP mode.........................................................................8-5
8.4 A/D converter during WAIT mode..........................................................................8-6
8.5 Port D analog input................................................................................................8-6
9
RESETS AND INTERRUPTS
9.1 Resets ...................................................................................................................9-1
9.1.1 Power-on reset.................................................................................................9-2
9.1.2 Miscellaneous register ...................................................................................9-2
9.1.3
RESET pin.......................................................................................................9-3
9.1.4 Computer operating properly (COP) watchdog reset.......................................9-3
9.1.4.1 COP watchdog during STOP mode...........................................................9-4
9.1.4.2 COP watchdog during WAIT mode............................................................9-4
9.1.5 Functions affected by reset..............................................................................9-5
9.2 Interrupts ...............................................................................................................9-6
9.2.1 Interrupt priorities.............................................................................................9-6
9.2.2 Nonmaskable software interrupt (SWI)............................................................9-6
9.2.3 Maskable hardware interrupts..........................................................................9-7
MC68HC05B6 MOTOROLA
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Table of Contents (continued)
Paragraph
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Page
NumberTitle
9.2.3.1 External interrupt (
IRQ)............................................................................. 9-7
9.2.3.2 Miscellaneous register ............................................................................. 9-9
9.2.3.3 Timer interrupts......................................................................................... 9-10
9.2.3.4 Serial communications interface (SCI) interrupts...................................... 9-10
9.2.4 Hardware controlled interrupt sequence......................................................... 9-11
10
CPU CORE AND INSTRUCTION SET
10.1 Registers............................................................................................................. 10-1
10.1.1 Accumulator (A) ............................................................................................ 10-2
10.1.2 Index register (X)........................................................................................... 10-2
10.1.3 Program counter (PC)................................................................................... 10-2
10.1.4 Stack pointer (SP)......................................................................................... 10-2
10.1.5 Condition code register (CCR)...................................................................... 10-2
10.2 Instruction set ..................................................................................................... 10-3
10.2.1 Register/memory Instructions ....................................................................... 10-4
10.2.2 Branch instructions ....................................................................................... 10-4
10.2.3 Bit manipulation instructions ......................................................................... 10-4
10.2.4 Read/modify/write instructions...................................................................... 10-4
10.2.5 Control instructions ....................................................................................... 10-4
10.2.6 Tables............................................................................................................ 10-4
10.3 Addressing modes.............................................................................................. 10-11
10.3.1 Inherent......................................................................................................... 10-11
10.3.2 Immediate..................................................................................................... 10-11
10.3.3 Direct............................................................................................................. 10-11
10.3.4 Extended....................................................................................................... 10-12
10.3.5 Indexed, no offset.......................................................................................... 10-12
10.3.6 Indexed, 8-bit offset....................................................................................... 10-12
10.3.7 Indexed, 16-bit offset..................................................................................... 10-12
10.3.8 Relative......................................................................................................... 10-13
10.3.9 Bit set/clear................................................................................................... 10-13
10.3.10 Bit test and branch........................................................................................ 10-13
MOTOROLA
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MC68HC05B6
Table of Contents (continued)
Paragraph
Number
Page
NumberTitle
11
ELECTRICAL SPECIFICATIONS
11.1 Maximum ratings ................................................................................................11-1
11.2 Thermal characteristics and power considerations .............................................11-2
11.3 DC electrical characteristics ..............................................................................11-3
11.3.1 I
DD
trends for 5V operation ...............................................................11-4
11.3.2 I
DD
trends for 3.3V operation ..............................................................11-7
11.4 A/D converter characteristics ...........................................................................11-9
11.5 Control timing ..............................................................................................11-11
12
MECHANICAL DATA
12.1 MC68HC05B6 pin configurations........................................................................12-1
12.1.1 52-pin plastic leaded chip carrier (PLCC) .....................................................12-1
12.1.2 64-pin quad flat pack (QFP) ..........................................................................12-2
12.1.3 56-pin shrink dual in line package (SDIP) ....................................................12-3
12.2 MC68HC05B6 mechanical dimensions...............................................................12-4
12.2.1 52-pin plastic leaded chip carrier (PLCC) .....................................................12-4
12.2.2 64-pin quad flat pack (QFP) .........................................................................12-5
12.2.3 56-pin shrink dual in line package (SDIP)......................................................12-6
13
ORDERING INFORMATION
13.1 EPROMS.............................................................................................................13-2
13.2 Verification media................................................................................................13-2
13.3 ROM verification units (RVU)...............................................................................13-2
MC68HC05B6 MOTOROLA
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Table of Contents (continued)
Paragraph
Number
Page
NumberTitle
A
MC68HC05B4
B
MC68HC05B8
C
MC68HC705B5
C.1 EPROM.................................................................................................................C-5
C.1.1 EPROM programming operation.....................................................................C-5
C.2 EPROM registers..................................................................................................C-6
C.2.1 EPROM control register ...............................................................................C-6
C.3 Options register (OPTR) ......................................................................................C-7
C.4 Bootstrap mode ....................................................................................................C-8
C.4.1 Erased EPROM verification ............................................................................C-11
C.4.2 EPROM parallel bootstrap load.......................................................................C-11
C.4.3 EPROM (RAM) serial bootstrap load and execute..........................................C-13
C.4.4 RAM parallel bootstrap load and execute .......................................................C-14
C.4.5 Bootstrap loader timing diagrams ............................................................C-17
C.5 DC electrical characteristics .................................................................................C-19
C.6 Control timing........................................................................................................C-19
D
MC68HC05B16
D.1 Self-check routines..............................................................................................D-1
E
MC68HC705B16
E.1 EPROM................................................................................................................. E-5
E.1.1 EPROM read operation...................................................................................E-5
E.1.2 EPROM program operation.............................................................................E-5
E.1.3 EPROM/EEPROM/ECLK control register .....................................................E-6
E.1.4 Mask option register ......................................................................................E-8
E.1.5 EEPROM options register (OPTR) ................................................................E-9
E.2 Bootstrap mode ....................................................................................................E-10
E.2.1 Erased EPROM verification ............................................................................E-13
MOTOROLA
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MC68HC05B6
Table of Contents (continued)
Paragraph
Number
Page
NumberTitle
E.2.2 EPROM/EEPROM parallel bootstrap.............................................................. E-13
E.2.3 EEPROM/EPROM/RAM serial bootstrap........................................................ E-16
E.2.4 RAM parallel bootstrap ...................................................................................E-19
E.2.4.1 Jump to start of RAM ($0050)................................................................... E-20
E.2.5 Maximum ratings ............................................................................................ E-21
E.2.6 Thermal characteristics and power considerations......................................... E-22
E.2.7 DC electrical characteristics ....................................................................... E-23
E.2.8 A/D converter characteristics .....................................................................E-26
E.3 Control timing ................................................................................................ E-28
F
MC68HC05B32
G
MC68HC705B32
G.1 EPROM ................................................................................................................G-5
G.1.1 EPROM read operation...................................................................................G-5
G.1.2 EPROM program operation ............................................................................G-5
G.1.3 EPROM/EEPROM control register ...............................................................G-6
G.1.4 Mask option register .....................................................................................G-8
G.1.5 Options register (OPTR) ...............................................................................G-9
G.2 Bootstrap mode....................................................................................................G-10
G.2.1 Erased EPROM verification............................................................................G-13
G.2.2 EPROM/EEPROM parallel bootstrap..............................................................G-13
G.2.3 Serial RAM loader...........................................................................................G-16
G.2.3.1 Jump to start of RAM ($0051)...................................................................G-16
G.2.4 Maximum ratings ............................................................................................G-19
G.2.5 Thermal characteristics and power considerations.........................................G-20
G.2.6 DC electrical characteristics ......................................................................G-21
G.2.7 A/D converter characteristics ....................................................................G-24
G.2.8 Control timing ..........................................................................................G-26
H
HIGH SPEED OPERATION
H.1 DC electrical characteristics ............................................................................... H-2
H.2 A/D converter characteristics ..............................................................................H-3
H.3 Control timing for 5V operation .......................................................................H-4
MC68HC05B6 MOTOROLA
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LIST OF FIGURES
Figure
Number
Page
NumberTitle
1-1 MC68HC05B6 block diagram.................................................................................1-3
2-1 MC68HC05B6 self-check schematic diagram........................................................2-3
2-2 MC68HC05B6 ‘load program in RAM and execute’ schematic diagram ................2-5
2-3 MC68HC05B6 ‘jump to any address’ schematic diagram......................................2-6
2-4 STOP and WAIT flowcharts....................................................................................2-8
2-5 Slow mode divider block diagram...........................................................................2-10
2-6 Oscillator connections ............................................................................................2-13
3-1 Memory map of the MC68HC05B6 ........................................................................3-2
4-1 Standard I/O port structure.....................................................................................4-2
4-2 ECLK timing diagram..............................................................................................4-3
4-3 Port logic levels.......................................................................................................4-6
5-1 16-bit programmable timer block diagram ..............................................................5-2
5-2 Timer state timing diagram for reset.......................................................................5-13
5-3 Timer state timing diagram for input capture..........................................................5-13
5-4 Timer state timing diagram for output compare......................................................5-14
5-5 Timer state timing diagram for timer overflow.........................................................5-14
6-1 Serial communications interface block diagram......................................................6-2
6-2 SCI rate generator division.....................................................................................6-4
6-3 Data format.............................................................................................................6-5
6-4 SCI examples of start bit sampling technique ........................................................6-7
6-5 SCI sampling technique used on all bits.................................................................6-7
6-6 Artificial start following a framing error ...................................................................6-8
6-7 SCI start bit following a break.................................................................................6-8
6-8 SCI example of synchronous and asynchronous transmission..............................6-9
6-9 SCI data clock timing diagram (M=0) .....................................................................6-12
6-10 SCI data clock timing diagram (M=1) .....................................................................6-13
7-1 PLM system block diagram.....................................................................................7-1
7-2 PLM output waveform examples.............................................................................7-2
7-3 PLM clock selection................................................................................................7-4
8-1 A/D converter block diagram..................................................................................8-2
8-2 Electrical model of an A/D input pin........................................................................8-6
9-1 Reset timing diagram..............................................................................................9-1
9-2 Watchdog system block diagram............................................................................9-3
9-3 Interrupt flow chart..................................................................................................9-8
MOTOROLA
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MC68HC05B6
LIST OF FIGURES (continued)
Figure
Number
Page
NumberTitle
10-1 Programming model.............................................................................................10-1
10-2 Stacking order......................................................................................................10-1
11-1 Equivalent test load..............................................................................................11-2
11-2 Run I
DD
vs internal operating frequency (4.5V, 5.5V) ..........................................11-4
11-3 Run I
DD
(SM = 1) vs internal operating frequency (4.5V, 5.5V) ...........................11-4
11-4 Wait I
DD
vs internal operating frequency (4.5V, 5.5V)..........................................11-4
11-5 Wait I
DD
(SM = 1) vs internal operating frequency (4.5V, 5.5V)...........................11-5
11-6 Increase in I
DD
vs frequency for A/D, SCI systems active, VDD = 5.5V...............11-5
11-7 I
DD
vs mode vs internal operating frequency, VDD = 5.5V ...................................11-5
11-8 Run I
DD
vs internal operating frequency (3V, 3.6V).............................................11-7
11-9 Run I
DD
(SM = 1) vs internal operating frequency (3V,3.6V) ...............................11-7
11-10 Wait I
DD
vs internal operating frequency (3V, 3.6V).............................................11-7
11-11 Wait I
DD
(SM = 1) vs internal operating frequency (3V, 3.6V)..............................11-8
11-12 Increase in I
DD
vs frequency for A/D, SCI systems active, VDD = 3.6V................11-8
11-13 I
DD
vs mode vs internal operating frequency, VDD = 3.6V ...................................11-8
11-14 Timer relationship.................................................................................................11-13
12-1 52-pin PLCC pinout..............................................................................................12-1
12-2 64-pin QFP pinout................................................................................................12-2
12-3 56-pin SDIP pinout...............................................................................................12-3
12-4 52-pin PLCC mechanical dimensions ..................................................................12-4
12-5 64-pin QFP mechanical dimensions.....................................................................12-5
12-6 56-pin SDIP mechanical dimensions....................................................................12-6
A-1 MC68HC05B4 block diagram.................................................................................A-2
A-2 Memory map of the MC68HC05B4........................................................................A-3
B-1 MC68HC05B8 block diagram.................................................................................B-2
B-2 Memory map of the MC68HC05B8........................................................................B-3
C-1 MC68HC705B5 block diagram.............................................................................. C-2
C-2 Memory map of the MC68HC705B5..................................................................... C-3
C-3 Modes of operation flow chart (1 of 2)................................................................... C-9
C-4 Modes of operation flow chart (2 of 2)................................................................... C-10
C-5 Timing diagram with handshake............................................................................ C-11
C-6 EPROM(RAM) parallel bootstrap schematic diagram........................................... C-12
C-7 EPROM (RAM) serial bootstrap schematic diagram............................................. C-15
C-8 RAM parallel bootstrap schematic diagram........................................................... C-16
C-9 EPROM parallel bootstrap loader timing diagram................................................. C-17
C-10 RAM parallel loader timing diagram..................................................................... C-18
D-1 MC68HC05B16 block diagram.............................................................................. D-2
D-2 Memory map of the MC68HC05B16..................................................................... D-3
E-1 MC68HC705B16 block diagram.............................................................................E-2
E-2 Memory map of the MC68HC705B16....................................................................E-3
MC68HC05B6 MOTOROLA
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LIST OF FIGURES (continued)
Figure
Number
Page
NumberTitle
E-3 Modes of operation flow chart (1 of 2)................................................................... E-11
E-4 Modes of operation flow chart (2 of 2)................................................................... E-12
E-5 Timing diagram with handshake............................................................................ E-13
E-6 Parallel EPROM loader timing diagram................................................................. E-14
E-7 EPROM Parallel bootstrap schematic diagram......................................................E-15
E-8 RAM/EPROM/EEPROM serial bootstrap schematic diagram............................... E-17
E-9 Parallel RAM loader timing diagram...................................................................... E-19
E-10 RAM parallel bootstrap schematic diagram........................................................... E-20
E-11 Equivalent test load ............................................................................................... E-22
E-12 Timer relationship.................................................................................................. E-30
F-1 MC68HC05B32 block diagram...............................................................................F-2
F-2 Memory map of the MC68HC05B32......................................................................F-3
G-1 MC68HC705B32 block diagram............................................................................G-2
G-2 Memory map of the MC68HC705B32...................................................................G-3
G-3 Modes of operation flow chart (1 of 2)...................................................................G-11
G-4 Modes of operation flow chart (2 of 2)...................................................................G-12
G-5 Timing diagram with handshake............................................................................G-14
G-6 Parallel EPROM loader timing diagram.................................................................G-14
G-7 EPROM parallel bootstrap schematic diagram......................................................G-15
G-8 RAM load and execute schematic diagram...........................................................G-17
G-9 Parallel RAM loader timing diagram......................................................................G-18
G-10 Equivalent test load...............................................................................................G-20
G-11 Timer relationship..................................................................................................G-28
H-1 Timer relationship.................................................................................................. H-4
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MOTOROLA
xii
MC68HC05B6
MC68HC05B6 MOTOROLA
xiii
LIST OF TABLES
Table
Number
Page
NumberTitle
1-1 Data sheet appendices...........................................................................................1-1
2-1 Mode of operation selection ...................................................................................2-1
2-2 MC68HC05B6 self-check results............................................................................2-2
3-1 EEPROM control bits description...........................................................................3-4
3-2 Register outline.......................................................................................................3-8
3-3
IRQ sensitivity.........................................................................................................3-9
4-1 I/O pin states ..........................................................................................................4-2
6-1 Method of receiver wake-up...................................................................................6-11
6-2 SCI clock on SCLK pin...........................................................................................6-13
6-3 First prescaler stage...............................................................................................6-18
6-4 Second prescaler stage (transmitter) .....................................................................6-18
6-5 Second prescaler stage (receiver)..........................................................................6-19
6-6 SCI baud rate selection..........................................................................................6-20
8-1 A/D clock selection.................................................................................................8-4
8-2 A/D channel assignment.........................................................................................8-5
9-1 Effect of
RESET, POR, STOP and WAIT................................................................9-5
9-2 Interrupt priorities ...................................................................................................9-7
9-3
IRQ sensitivity.........................................................................................................9-9
10-1 MUL instruction.....................................................................................................10-5
10-2 Register/memory instructions...............................................................................10-5
10-3 Branch instructions...............................................................................................10-6
10-4 Bit manipulation instructions.................................................................................10-6
10-5 Read/modify/write instructions .............................................................................10-7
10-6 Control instructions...............................................................................................10-7
10-7 Instruction set (1 of 2)...........................................................................................10-8
10-8 Instruction set (2 of 2)...........................................................................................10-9
10-9 M68HC05 opcode map.........................................................................................10-10
11-1 Maximum ratings..................................................................................................11-1
11-2 Package thermal characteristics...........................................................................11-2
11-3 DC electrical characteristics for 5V operation.......................................................11-3
11-4 DC electrical characteristics for 3.3V operation....................................................11-6
11-5 A/D characteristics for 5V operation.....................................................................11-9
11-6 A/D characteristics for 3.3V operation..................................................................11-10
11-7 Control timing for 5V operation.............................................................................11-11
11-8 Control timing for 3.3V operation..........................................................................11-12
MOTOROLA
xiv
MC68HC05B6
LIST OF TABLES (continued)
Table
Number
Page
NumberTitle
13-1 MC order numbers ...............................................................................................13-1
13-2 EPROMs for pattern generation...........................................................................13-2
A-1 Register outline ......................................................................................................A-4
B-1 Register outline ......................................................................................................B-4
C-1 Register outline ..................................................................................................... C-4
C-2 Mode of operation selection.................................................................................. C-8
C-3 Bootstrap vector targets in RAM............................................................................C-14
C-4 Additional DC electrical characteristics for MC68HC705B5.................................. C-19
C-5 Additional control timing for MC68HC705B5......................................................... C-19
D-1 Register outline ..................................................................................................... D-4
E-1 Register outline ......................................................................................................E-4
E-2 EPROM control bits description .............................................................................E-6
E-3 EEPROM control bits description...........................................................................E-7
E-4 Mode of operation selection ...................................................................................E-10
E-5 Bootstrap vector targets in RAM.............................................................................E-18
E-6 Maximum ratings....................................................................................................E-21
E-7 Package thermal characteristics.............................................................................E-22
E-8 DC electrical characteristics for 5V operation ........................................................E-23
E-9 DC electrical characteristics for 3.3V operation .....................................................E-25
E-10 A/D characteristics for 5V operation.......................................................................E-26
E-11 A/D characteristics for 3.3V operation....................................................................E-27
E-12 Control timing for 5V operation...............................................................................E-28
E-13 Control timing for 3.3V operation............................................................................E-29
F-1 Register outline......................................................................................................F-4
G-1 Register outline.....................................................................................................G-4
G-2 EPROM control bits description ............................................................................G-6
G-3 EEPROM control bits description..........................................................................G-7
G-4 Mode of operation selection.................................................................................. G-10
G-5 Bootstrap vector targets in RAM............................................................................G-16
G-6 Maximum ratings...................................................................................................G-19
G-7 Package thermal characteristics............................................................................G-20
G-8 DC electrical characteristics for 5V operation .......................................................G-21
G-9 DC electrical characteristics for 3.3V operation ....................................................G-23
G-10 A/D characteristics for 5V operation...................................................................... G-24
G-11 A/D characteristics for 3.3V operation................................................................... G-25
G-12 Control timing for 5V operation.............................................................................. G-26
G-13 Control timing for operation at 3.3V....................................................................... G-27
H-1 Ordering information.............................................................................................. H-1
H-2 DC electrical characteristics for 5V operation .......................................................H-2
H-3 A/D characteristics for 5V operation...................................................................... H-3
MC68HC05B6 MOTOROLA
1-1
INTRODUCTION
1
1
INTRODUCTION
The MC68HC05B6 microcomputer (MCU) is a member of Motorola’s MC68HC05 family of
low-cost single chip microcomputers. This 8-bit MCU contains an on-chip oscillator, CPU, RAM,
ROM, EEPROM, A/D converter, pulse length modulated outputs, I/O, serial communications
interface, programmable timer system and watchdog. The fully static design allows operation at
frequencies down to dc to further reduce the already low power consumption to a few micro-amps.
This data sheet is structured such that devices similar to the MC68HC05B6 are described in a set
of appendices (see Table 1-1).
Table 1-1 Data sheet appendices
Device Appendix Differences from MC68HC05B6
MC68HC05B4 A 4K bytes ROM; no EEPROM
MC68HC05B8 B 7.25K bytes ROM
MC68HC705B5 C
6K bytes EPROM; self-check replaced by bootstrap
firmware; no EEPROM
MC68HC05B16 D 16K bytes ROM; increased RAM and self-check ROM
MC68HC705B16 E
16K bytes EPROM; increased RAM; self-check replaced
by bootstrap firmware; modified power-on reset routine
MC68HC05B32 F 32K bytes ROM; no page zero ROM; increased RAM
MC68HC705B32 G
32K bytes EPROM; no page zero ROM; increased RAM;
self-check mode replaced by bootstrap firmware
MOTOROLA
1-2
MC68HC05B6INTRODUCTION
1
1.1 Features
Hardware features
• Fully static design featuring the industry standard M68HC05 family CPU core
• On chip crystal oscillator with divide by 2 or a software selectable divide by 32 option (SLOW
mode)
• 2.1 MHz internal operating frequency at 5V; 1.0 MHz at 3V
• 176 bytes of RAM
• 5936 bytes of user ROM plus 14 bytes of user vectors
• 256 bytes of byte erasable EEPROM with internal charge pump and security bit
• Write/erase protect bit for 224 of the 256 bytes EEPROM
• Self test/bootstrap mode
• Power saving STOP, WAIT and SLOW modes
• Three 8-bit parallel I/O ports and one 8-bit input-only port
• Software option available to output the internal E-clock to port pin PC2
• 16-bit timer with 2 input captures and 2 output compares
• Computer operating properly (COP) watchdog timer
• Serial communications interface system (SCI) with independent transmitter/receiver baud rate
selection; receiver wake-up function for use in multi-receiver systems
• 8 channel A/D converter
• 2 pulse length modulation systems which can be used as D/A converters
• One interrupt request input plus 4 on-board hardware interrupt sources
• Available in 52-pin plastic leaded chip carrier (PLCC), 64-pin quad flat pack (QFP) and 56-pin
shrink dual in line (SDIP) packages
• Complete development system support available using the MMDS05 de velopment station with
the M68HC05BEM emulation module or the M68HC05BEVS evaluation system
1.2 Mask options for the MC68HC05B6
The MC68HC05B6 has three mask options that are programmed during manufacture and must
be specified on the order form.
• Power-on-reset delay (t
PORL
) = 16 or 4064 cycles
MC68HC05B6 MOTOROLA
1-3
INTRODUCTION
1
• Automatic watchdog enable/disable following a power-on or external reset
• Watchdog enable/disable during WAIT mode
Warning: It is recommended that an external clock is alw ays used if t
PORL
is set to 16 cycles. This
will prevent any problems arising with oscillator stability when the device is put into
STOP mode.
Figure 1-1 MC68HC05B6 block diagram
Port A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Port B
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Port C
PC0
PC1
PC2/ECLK
PC3
PC4
PC5
PC6
PC7
16-bit
programmable
timer
Port D
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
Oscillator
176 bytes
RAM
COP watchdog
RESET
IRQ
VDD
VSS
OSC1
OSC2
M68HC05
CPU
SCI
A/D converter
PLM
TCAP1
TCAP2
TCMP1
TCMP2
VRH
VRL
RDI
SCLK
TDO
VPP1
256 bytes
EEPROM
Charge pump
2 / 32
PLMA D/A
PLMB D/A
8-bit
432 bytes
User ROM
5950 bytes
self check ROM
(including 14 bytes
User vectors)
MOTOROLA
1-4
MC68HC05B6INTRODUCTION
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1
MC68HC05B6 MOTOROLA
2-1
MODES OF OPERATION AND PIN DESCRIPTIONS
2
2
MODES OF OPERATION AND PIN
DESCRIPTIONS
2.1 Modes of operation
The MC68HC05B6 MCU has two modes of operation, namely single chip and self check modes.
Table 2-1 shows the conditions required to enter each mode on the rising edge of
RESET.
2.1.1 Single chip mode
This is the normal operating mode of the MC68HC05B6. In this mode the device functions as a
self-contained microcomputer (MCU) with all on-board peripherals, including the three 8-bit I/O
ports and the 8-bit input-only port, available to the user. All address and data activity occurs within
the MCU.
2.1.2 Self-check mode
The self-check function available on the MC68HC05B6 provides an internal capability to
determine if the device is functional. Self-check is performed using the circuit shown in Figure 2-1.
Port C pins PC0–PC3 are monitored for the self-check results (light emitting diodes are shown but
other devices could be used), and are interpreted as described in Table 2-2. The self-check mode
Table 2-1 Mode of operation selection
IRQ pin TCAP1 pin PD3 PD4 Mode
VSS to VDDVSS to V
DD
X X Single chip
2V
DD
V
DD
0 X Self-check
2V
DD
V
DD
1 0 Serial RAM loader
2V
DD
V
DD
1 1 Jump to any address
MOTOROLA
2-2
MC68HC05B6MODES OF OPERATION AND PIN DESCRIPTIONS
2
is entered by applying 2 x VDD dc (via a 4.7k resistor) to the IRQ pin and 5V dc input (via a 4.7k
resistor) to the TCAP1 pin and then depressing the reset switch to execute a reset. After reset, the
following tests are performed automatically and once completed they continually repeat. A good
device will exhibit flashing LEDs; a bad device will be indicated by the LEDs holding at one value.
I/0 — Functionally exercises ports A, B, C and D
RAM — Counter test for each RAM byte
ROM — Exclusive OR with odd ones parity result
Timer — Tracks counter registers and checks ICF1, ICF2, OCF1,
OCF2 and TOF flags
SCI — Transmission test; check for RDRF, TDRE, TC and FE
flags
A/D — Check A/D functionality on internal channels: VRL, VRH
and (VRL + VRH)/2
EEPROM — This test is optional; it executes a write/erase test of the
256 bytes EEPROM (available only for the MC68HC05B6
version), and then deactivates the security bit.
PLM — Checks the PLM basic functionality
Interrupts — Tests external timer and SCI interrupts
Watchdog — Tests the watchdog
Table 2-2 MC68HC05B6 self-check results
PC3 PC2 PC1 PC0 Remarks
1 0 0 1 Bad port
0 1 1 0 Bad port
1 0 1 0 Bad RAM
1 0 1 1 Bad ROM
1 1 0 0 Bad Timer
1 1 0 1 Bad SCI
1 1 1 0 Bad A/D
0 0 0 0 Bad EEPROM (or other if B4)
0 0 0 1 Bad PLM
0 0 1 0 Bad interrupts
0 0 1 1 Bad watchdog
Flashing Good device
All others Bad device, bad port etc.
‘0’ indicates LED on; ‘1’ indicates LED off
MC68HC05B6 MOTOROLA
2-3
MODES OF OPERATION AND PIN DESCRIPTIONS
2
Figure 2-1 MC68HC05B6 self-check schematic diagram
6
40
51
OSC1
OSC2
IRQ
TCAP2
TCMP2
TCAP1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
VRLVSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
TCMP1
SCLK
PLMB
PLMA
TDO
RDI
VPP1
NC
RESET
NC VRH VDD
18
50
52
20
21
2
3
4
5
9
11
12
13
14
24
25
26
27
28
29
30
31
16
17
19
23
1
22
32
33
34
35
36
37
38
39
42
43
44
45
46
47
48
49
41 7
0.01 F
10 nF 47 F
10 M
4 MHz
22 pF
4k7
4k7
680
22 pF
4k7
4k7
680
680
680
BC239
P1
GND
+5V
2xV
DD
RESET
EEPROM tested
EEPROM not tested
15 8 10
Note:
For the MC68HC05B4, switches on PB5 and PB6 have no effect
All resistors are 10 k, unless otherwise stated.
MC68HC05B6 (52-pin package)
MOTOROLA
2-4
MC68HC05B6MODES OF OPERATION AND PIN DESCRIPTIONS
2
2.2 Serial RAM loader
The ‘load program in RAM and execute’ mode is entered if the following conditions are satisfied
when the reset pin is released to V
DD
. The format used is identical to the format used for the
MC68HC805C4. The SEC bit in the options register must be inactive, i.e. set to ‘1’.
–
IRQ at 2xV
DD
– TCAP1 at V
DD
– PD3 at VDD for at least 30 machine cycles after reset
– PD4 at V
SS
for at least 30 machine cycles after reset
In the ‘load program in RAM and execute’ routine, user programs are loaded into MCU RAM via
the SCI port and then executed. Data is loaded sequentially, starting at RAM location $0050, until
the last byte is loaded. Program control is then transferred to the RAM program starting at location
$0051. The first byte loaded is the count of the total number of bytes in the program plus the count
byte. The program starts at the second byte in RAM. During the firmware initialization stage, the
SCI is configured for the NRZ data format (idle line, start bit, eight data bits and stop bit). The baud
rate is 9600 with a 4 MHz crystal. A program to convert ASCII S-records to the format required by
the RAM loader is available from Motorola.
If immediate execution is not desired after loading the RAM program, it is possible to hold off
execution. This is accomplished b y setting the byte count to a v alue that is greater than the o verall
length of the loaded data. When the last byte is loaded, the firmware will halt operation expecting
additional data to arrive. At this point, the reset switch is placed in the reset position which will
reset the MCU, but keep the RAM program intact. All routines can now be entered from this state,
including the one which will execute the program in RAM (see Section 2.3).
To load a program in the EEPROM, the ‘load program in RAM and execute’ function is also used.
In this instance the process involves two distinct steps. Firstly, the RAM is loaded with a program
which will control the loading of the EEPROM, and when the RAM contents are executed, the
MCU is instructed to load the EEPROM.
The erased state of the EEPROM is $FF.
Figure 2-2 shows the schematic diagram of the circuit required for the serial RAM loader.
2.3 ‘Jump to any address’
The ‘jump to any address’ mode is entered when the reset pin is released to VDD, if the following
conditions are satisfied:
–
IRQ at 2xV
DD
– TCAP1 at V
DD
– PD3 at VDD for at least 30 machine cycles after reset
– PD4 at V
DD
for at least 30 machine cycles after reset
MC68HC05B6 MOTOROLA
2-5
MODES OF OPERATION AND PIN DESCRIPTIONS
2
This function allows execution of programs previously loaded in RAM or EEPROM using the
methods outlined in Section 2.2.
To execute the ‘jump to any address’ function, data input at port A has to be $CC and data input at
port B and port C should represent the MSB and LSB respectively, of the address to jump to for
execution of the user program. A schematic diagram of the circuit required is shown inFigure 2-3.
Figure 2-2 MC68HC05B6 ‘load program in RAM and execute’ schematic diagram
32
OSC1
OSC2
IRQ
TCAP2
TCMP2
TCAP1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET
VDD
18
24
25
26
27
28
29
30
31
16
17
19
41
10 k
0.01 F
10 nF 47 F
10 M
4 MHz
22 pF
10 k
22 pF
P1
GND
+5V
2xV
DD
RESET
10
VRH
VRL
VPP1
PLMA
PLMB
TCMP1
RDI
TDO
NC
NC
RS232 level translator
suggested:
MC145406 or MAX232
9600 Bd
RS232
SCLK
10 k
10 k
10 k
11
9
22
8
7
40
20
21
51
1
23
2
3
4
5
12
13
14
33
34
35
36
37
38
39
42
43
44
45
46
47
48
49
6
15
50
52
optional
3 x 10 k
Connect as required
for the application
Connect as required
for the application
MC68HC05B6 (52-pin package)
MOTOROLA
2-6
MC68HC05B6MODES OF OPERATION AND PIN DESCRIPTIONS
2
Figure 2-3 MC68HC05B6 ‘jump to any address’ schematic diagram
32
OSC1
OSC2
IRQ
TCAP2
TCMP2
TCAP1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET
VDD
18
24
25
26
27
28
29
30
31
16
17
19
41
10 k
0.01 F
10 nF 47 F
10 M
4 MHz
22 pF
10 k
22 pF
P1
GND
+5V
2xV
DD
RESET
10
VRH
VRL
VPP1
PLMA
PLMB
TCMP1
RDI
TDO
NC
NC
SCLK
10 k
10 k
10 k
11
9
22
8
7
40
20
21
51
1
23
2
3
4
5
12
13
14
33
34
35
36
37
38
39
42
43
44
45
46
47
48
49
6
15
50
52
optional
3 x 10 k
Connect as required
for the application
8 x 10 k optional (see note)
8 x 10 k
8 x 10 k
MSBLSB
Select required address
Note:
These eight resistors are optional; direct connection is possible if pins PA0-PA7, PB0-PB7 and PC0-PC7 are
kept in input mode during application.
MC68HC05B6 (52-pin package)
MC68HC05B6 MOTOROLA
2-7
MODES OF OPERATION AND PIN DESCRIPTIONS
2
2.4 Low power modes
The STOP and WAIT instructions have different effects on the programmable timer, the serial
communications interface, the watchdog system, the EEPROM and the A/D converter. These
different effects are described in the following sections.
2.4.1 STOP
The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the
internal oscillator is turned off, halting all internal processing including timer, serial
communications interface and the A/D converter (see flowchart in Figure 2-4). The only way for
the MCU to wake-up from the STOP mode is b y receipt of an e xternal interrupt or by the detection
of a reset (logic low on
RESET pin or a power-on reset).
During STOP mode, the I-bit in the CCR is cleared to enable external interrupts (see Section
10.1.5). The SM bit is cleared to allow nominal speed operation for the 4064 cycles count while
exiting STOP mode (see Section 2.4.3).
All other registers and memory remain unaltered and all input/output lines remain unchanged.
This continues until an external interrupt (
IRQ) or reset is sensed, at which time the internal
oscillator is turned on. The external interrupt or reset causes the program counter to vector to the
corresponding locations ($1FFA, B and $1FFE, F respectively).
When leaving STOP mode, a t
PORL
internal cycles delay is provided to give the oscillator time to
stabilise before releasing CPU operation. This delay is selectable via a mask option to be either
16 or 4064 cycles. The CPU will resume operation by servicing the interrupt that wakes it up, or
by fetching the reset vector, if reset wakes it up.
Warning: If t
PORL
is selected to be 16 cycles, it is recommended that an external clock signal is
used to avoid problems with oscillator stability while the device is in STOP mode.
Note:
The stacking corresponding to an eventual interrupt to go out of STOP mode will only
be executed when going out of STOP mode.
The following list summarizes the effect of STOP mode on the individual modules of the
MC68HC05B6.
– The watchdog timer is reset; refer to Section 9.1.4.1
– The EEPROM acts as read-only memory (ROM); refer to Section 3.6
– All SCI activity stopped; refer to Section 6.13
– The timer stops counting; refer to Section 5.6
– The PLM outputs remain at current level; refer to Section 7.2
– The A/D converter is disabled; refer to Section 8.3
– The I-bit in the CCR is cleared
MOTOROLA
2-8
MC68HC05B6MODES OF OPERATION AND PIN DESCRIPTIONS
2
Figure 2-4 STOP and WAIT flowcharts
Timer interrupt?
IRQ
external
interrupt?
SCI interrupt?
Stop oscillator and all
clocks.
Clear I bit.
STOP WAIT
Reset?
IRQ
external
interrupt?
Generate watchdog
interrupt
Reset?
Watchdog active?
(1) Fetch reset vector or
(2) Service interrupt:
a. stack
b. set I-bit
c. vector to interrupt
routine
(1) Fetch reset vector or
(2) Service interrupt:
a. stack
b. set I-bit
c. vector to interrupt
routine
Turn on oscillator.
Wait for time delay to
stabilise
Restart processor clock
YES
NO
YES
YES
YES
YES
YES
YES
NO
NO
NO
NO
NO
NO
Oscillator activ e. Timer , SCI,
A/D, EEPROM clocks active.
Processor clocks stopped
Clear I-bit
MC68HC05B6 MOTOROLA
2-9
MODES OF OPERATION AND PIN DESCRIPTIONS
2
2.4.2 WAIT
The WAIT instruction places the MCU in a low power consumption mode, but WAIT mode
consumes more power than STOP mode. All CPU action is suspended and the watchdog is
disabled, but the timer, A/D and SCI systems remain active and operate as normal (see flowchart
in Figure 2-4). All other memory and registers remain unaltered and all parallel input/output lines
remain unchanged. The programming or erase mechanism of the EEPROM is also unaffected, as
well as the charge pump high voltage generator.
During WAIT mode the I-bit in the CCR is cleared to enable all interrupts. The INTE bit in the
miscellaneous register (Section 2.5) is not affected by WAIT mode. When any interrupt or reset is
sensed, the program counter vectors to the locations containing the start address of the interrupt
or reset service routine.
Any
IRQ, timer (overflow, input capture or output compare) or SCI interrupt (in addition to a logic
low on the
RESET pin) causes the processor to exit WAIT mode.
If a non-reset exit from WAIT mode is performed (i.e. timer overflow interrupt exit), the state of the
remaining systems will be unchanged.
If a reset exit from WAIT mode is performed the entire system reverts to the disabled reset state.
Note:
The stacking corresponding to an eventual interrupt to leave WAIT mode will only be
executed when leaving WAIT mode.
The following list summarizes the effect of WAIT mode on the modules of the MC68HC05B6.
– The watchdog timer functions according to the mask option selected; refer
to Section 9.1.4.2
– The EEPROM is not affected; refer to Section 3.7
– The SCI is not affected; refer to Section 6.14
– The timer is not affected; refer to Section 5.7
– The PLM is not affected; refer to Section 7.4
– The A/D converter is not affected; refer to Section 8.4
– The I-bit in the CCR is cleared
2.4.2.1 Power consumption during WAIT mode
Power consumption during WAIT mode depends on how many systems are active. The power
consumption will be highest when all the systems (A/D, timer, EEPROM and SCI) are active, and
lowest when the EEPROM erase and programming mechanism, SCI and A/D are disabled. The
timer cannot be disabled in WAIT mode. It is important that before entering WAIT mode, the
programmer sets the relevant control bits for the individual modules to reflect the desired
functionality during WAIT mode.
Power consumption may be further reduced by the use of SLOW mode.
MOTOROLA
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MC68HC05B6MODES OF OPERATION AND PIN DESCRIPTIONS
2
2.4.3 SLOW mode
The SLOW mode function is controlled by the SM bit in the miscellaneous register at location
$000C. It allows the user to insert, under software control, an extra divide-by-16 between the
oscillator and the internal clock driver (see Figure 2-5). This f eature permits a slo w down of all the
internal operations and thus reduces power consumption. The SLOW mode function should not
be enabled while using the A/D converter or while erasing/programming the EEPROM unless the
internal A/D RC oscillator is turned on.
2.4.3.1 Miscellaneous register
SM — Slow mode
1 (set) – The system runs at a bus speed 16 times lower than normal
(f
OSC
/32). SLOW mode affects all sections of the device, including
SCI, A/D and timer.
0 (clear) – The system runs at normal bus speed (f
OSC
/2).
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
Note:
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
Figure 2-5 Slow mode divider block diagram
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Miscellaneous $000C POR INTP INTN INTE SFA SFB SM WDOG ?001 000?
OSC1
pin
OSC2
pin
Oscillator
f
OSC
Control logicSM–bit
f
OSC
/2
2 16
Main internal clock
f
OSC
/32
(bit 1, $000C)
MC68HC05B6 MOTOROLA
2-11
MODES OF OPERATION AND PIN DESCRIPTIONS
2
2.5 Pin descriptions
2.5.1 VDD and VSS
Power is supplied to the microcontroller using these tw o pins. VDD is the positive supply and VSS
is ground.
It is in the nature of CMOS designs that very fast signal transitions occur on the MCU pins. These
short rise and fall times place very high short-duration current demands on the power supply. To
prevent noise problems, special care must be taken to provide good power supply by-passing at
the MCU. By-pass capacitors should have good high-frequency characteristics and be as close to
the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are
loaded.
2.5.2 IRQ
This is an input-only pin for external interrupt sources. Interrupt triggering is selected using the
INTP and INTN bits in the miscellaneous register, to be one of four options detailed in Table 9-3.
In addition, the external interrupt facility (
IRQ) can be disabled using the INTE bit in the
miscellaneous register (see Section 3.8). It is only possible to change the interrupt option bits in
the miscellaneous register while the I-bit is set. Selecting a different interrupt option will
automatically clear any pending interrupts. Further details of the external interrupt procedure can
be found in Section 9.2.3.1.
The
IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity.
2.5.3 RESET
This active low I/O pin is used to reset the MCU. Applying a logic zero to this pin f orces the de vice
to a known start-up state. An external RC-circuit can be connected to this pin to generate a
power-on-reset (POR) if required. In this case, the time constant must be great enough (at least
100ms) to allow the oscillator circuit to stabilise. This input has an internal Schmitt trigger to
improve noise immunity. When a reset condition occurs internally, i.e. from the COP watchdog, the
RESET pin provides an active-low open drain output signal that may be used to reset external
hardware.
2.5.4 TCAP1
The TCAP1 input controls the input capture 1 function of the on-chip programmable timer system.
MOTOROLA
2-12
MC68HC05B6MODES OF OPERATION AND PIN DESCRIPTIONS
2
2.5.5 TCAP2
The TCAP2 input controls the input capture 2 function of the on-chip programmable timer system.
2.5.6 TCMP1
The TCMP1 pin is the output of the output compare 1 function of the timer system.
2.5.7 TCMP2
The TCMP2 pin is the output of the output compare 2 function of the timer system.
2.5.8 OSC1, OSC2
These pins provide control input for an on-chip oscillator circuit. A crystal, ceramic resonator or
external clock signal connected to these pins supplies the oscillator clock. The oscillator frequency
(f
OSC
) is divided by two to give the internal bus frequency (fOP). There is also a software option
which introduces an additional divide by 16 into the oscillator clock, giving an internal bus
frequency of f
OSC
/32.
2.5.8.1 Crystal
The circuit shown in Figure 2-6(a) is recommended when using either a crystal or a ceramic
resonator. Figure 2-6(d) lists the recommended capacitance and f eedback resistance v alues. The
internal oscillator is designed to interface with an AT-cut parallel-resonant quartz crystal resonator
in the frequency range specified for f
OSC
(see Section 11.5). Use of an external CMOS oscillator
is recommended when crystals outside the specified ranges are to be used. The crystal and
associated components should be mounted as close as possible to the input pins to minimise
output distortion and start-up stabilisation time. The manufacturer of the particular crystal being
considered should be consulted for specific information.
2.5.8.2 Ceramic resonator
A ceramic resonator may be used instead of a crystal in cost sensitive applications. The circuit shown
in Figure 2-6(a) is recommended when using either a crystal or a ceramic resonator. Figure 2-6(d) lists
the recommended capacitance and feedback resistance values. The manufacturer of the particular
ceramic resonator being considered should be consulted for specific information.
MC68HC05B6 MOTOROLA
2-13
MODES OF OPERATION AND PIN DESCRIPTIONS
2
2.5.8.3 External clock
An external clock should be applied to the OSC1 input, with the OSC2 pin left unconnected, as
shown in Figure 2-6(c). The t
OXOV
or t
ILCH
specifications (see Section 11.5) do not apply when
using an external clock input. The equivalent specification of the external clock source should be
used in lieu of t
OXOV
or t
ILCH
.
Figure 2-6 Oscillator connections
Ceramic resonator
2 – 4MHz Unit
RS(typ) 10
C
0
40 pF
C
1
4.3 pF
C
OSC1
30 pF
C
OSC2
30 pF
R
P
1 – 10 M
Q 1250 —
Crystal
2MHz 4MHz Unit
RS(max) 400 75
C
0
5 7 pF
C
1
8 12 nF
C
OSC1
15 – 40 15 – 30 pF
C
OSC2
15 – 30 15 – 25 pF
R
P
10 10 M
Q 30 000 40 000 —
OSC1 OSC2
R
P
MCU
C
OSC2
C
OSC1
OSC1 OSC2
MCU
NCExternal
clock
OSC1 OSC2
R
S
C
1
L
C
0
(d) Typical crystal and ceramic resonator parameters
(c) External clock source connections
(b) Crystal equivalent circuit
(a) Crystal/ceramic resonator
oscillator connections
MOTOROLA
2-14
MC68HC05B6MODES OF OPERATION AND PIN DESCRIPTIONS
2
2.5.9 RDI (Receive data in)
The RDI pin is the input pin of the SCI receiver.
2.5.10 TDO (Transmit data out)
The TDO pin is the output pin of the SCI transmitter.
2.5.11 SCLK
The SCLK pin is the clock output pin of the SCI transmitter.
2.5.12 PLMA
The PLMA pin is the output of pulse length modulation converter A.
2.5.13 PLMB
The PLMB pin is the output of pulse length modulation converter B.
2.5.14 VPP1
The VPP1 pin is the output of the charge pump for the EEPROM1 array.
2.5.15 VRH
The VRH pin is the positive reference voltage for the A/D converter.
2.5.16 VRL
The VRL pin is the negative reference voltage for the A/D converter.
2.5.17 PA0 – PA7/PB0 – PB7/PC0 – PC7
These 24 I/O lines comprise ports A, B and C. The state of any pin is software programmable, and
all the pins are configured as inputs during power-on or reset.
Under software control the PC2 pin can output the internal E-clock (see Section 4.2).
2.5.18 PD0/AN0–PD7/AN7
This 8-bit input only port (D) shares its pins with the A/D converter. When enabled, the A/D
converter uses pins PD0/AN0 – PD7/AN7 as its analog inputs. On reset, the A/D converter is
disabled which forces the port D pins to be input only port pins (see Section 8.5).
MC68HC05B6 MOTOROLA
3-1
MEMORY AND REGISTERS
3
3
MEMORY AND REGISTERS
The MC68HC05B6 MCU is capable of addressing 8192 bytes of memory and registers with its
program counter. The memory map includes 5950 bytes of User ROM (including User vectors),
432 bytes of self check ROM, 176 bytes of RAM and 256 bytes of EEPROM.
3.1 Registers
All the I/O, control and status registers of the MC68HC05B6 are contained within the first 32-b yte
block of the memory map, as shown in Figure 3-1. The miscellaneous register is shown in Section
3.8 as this register contains bits which are relevant to several modules.
3.2 RAM
The user RAM comprises 176 bytes of memory, from $0050 to $00FF. This is shared with a 64
byte stack area. The stack begins at $00FF and may extend down to $00C0.
Note:
Using the stack area f or data stor age or tempor ary work locations requires care to prevent
the data from being overwritten due to stacking from an interrupt or subroutine call.
3.3 ROM
The User ROM consists of 5950 bytes of ROM mapped as follows:
• 48 bytes of page zero ROM from $0020 to $004F
• 5888 bytes of User ROM from $0800 to $1EFF
• 14 bytes of User vectors from $1FF2 to $1FFF
MOTOROLA
3-2
MC68HC05B6MEMORY AND REGISTERS
3
3.4 Self-check ROM
There are two areas of self-check ROM (ROMI and ROMII) located from $0200 to $02BF (192
bytes) and $1F00 to $1FEF (240 bytes) respectively.
Figure 3-1 Memory map of the MC68HC05B6
$1FFE–F
$1FF6–7
Port B data register
Port C data register
Port D input data register
Port A data register
$0000
Compare low register 2
A/D data register
User vectors
(14 bytes)
$0000
I/O
(32 bytes)
$0020
$00C0
$0100
$1FF0
Stack
RAM
(176 bytes)
$02C0
$0200
$1F00
$0050
Port A data direction register
Port B data direction register
Port C data direction register
EEPROM/ECLK control register
A/D status/control register
Pulse length modulation A
Pulse length modulation B
Miscellaneous register
SCI baud rate register
SCI control register 1
SCI control register 2
SCI status register
SCI data register
Timer control register
Timer status register
Capture high register 1
Capture low register 1
Compare high register 1
Compare low register 1
Counter high register
Counter low register
Alternate counter high register
Alternate counter low register
Capture high register 2
Capture low register 2
Compare high register 2
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Page 0 User
ROM
(48 bytes)
Self-check ROM I
(192 bytes)
User ROM
(5888 bytes)
Self-check ROM II
(240 bytes)
$0800
$1FF2–3
OPTR (1 byte)
Non protected (31 bytes)
Protected (224 bytes)
EEPROM
(256 bytes)
$0101
$0120
$0100Options register
Reserved
MC68HC05B6 Registers
SCI
Timer overflow
Timer output compare 1& 2
Timer input capture 1 & 2
External
IRQ
SWI
Reset/power-on reset
$1FF4–5
$1FF8–9
$1FFA–B
$1FFC–D
MC68HC05B6 MOTOROLA
3-3
MEMORY AND REGISTERS
3
3.5 EEPROM
The user EEPROM consists of 256 bytes of memory located from address $0100 to $01FF. 255
bytes are general purpose and 1 byte is used by the option register. The non-volatile EEPROM is
byte erasable.
An internal charge pump provides the EEPROM voltage (V
PP1
), which removes the need to supply
a high voltage for erase and programming functions. The charge pump is a capacitor/diode ladder
network which will give a very high impedance output of around 20-30 M. The voltage of the
charge pump is visible at the VPP1 pin. During normal operation of the device, where
programming/erasing of the EEPROM array will occur, VPP1 should ne ver be connected to either
VDD or VSS as this could prevent the charge pump reaching the necessary programming voltage.
Where it is considered dangerous to leave VPP1 unconnected for reasons of excessive noise in
a system, it may be tied to V
DD
; this will protect the EEPROM data but will also increase power
consumption, and therefore it is recommended that the protect bit function is used for regular
protection of EEPROM data (see Section 3.5.5).
In order to achieve a higher degree of security for stored data, there is no capability for bulk or row
erase operations.
The EEPROM control register ($0007) provides control of the EEPROM programming and erase
operations.
Warning: The VPP1 pin should never be connected to VSS, as this could cause permanent
damage to the device.
3.5.1 EEPROM control register
ECLK
See Section 4.3 for a description of this bit.
E1ERA — EEPROM erase/programming bit
Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the
EEPROM is for erasing or programming purposes.
1 (set) – An erase operation will take place.
0 (clear) – A programming operation will take place.
Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
EEPROM/ECLK control $0007 0 0 0 0 ECLK E1ERA E1LAT E1PGM 0000 0000
MOTOROLA
3-4
MC68HC05B6MEMORY AND REGISTERS
3
E1LAT — EEPROM programming latch enable bit
1 (set) – Address and data can be latched into the EEPROM for further
program or erase operations, providing the E1PGM bit is cleared.
0 (clear) – Data can be read from the EEPROM. The E1ERA bit and the
E1PGM bit are reset to zero when E1LAT is ‘0’.
STOP, power-on and external reset clear the E1LAT bit.
Note:
After the t
ERA1
erase time or t
PROG1
programming time, the E1LAT bit has to be reset
to zero in order to clear the E1ERA bit and the E1PGM bit.
E1PGM — EEPROM charge pump enable/disable
1 (set) – Internal charge pump generator switched on.
0 (clear) – Internal charge pump generator switched off.
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array.
This bit cannot be set before the data is selected, and once this bit has been set it can only be
cleared by clearing the E1LAT bit.
A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are giv e in Table 3-1.
Note:
All combinations are not shown in the above table, since the E1PGM and E1ERA bits
are cleared when the E1LAT bit is at zero, and will result in a read condition.
Table 3-1 EEPROM control bits description
E1ERA E1LAT E1PGM Description
0 0 0 Read condition
0 1 0 Ready to load address/data for program/erase
0 1 1 Byte programming in progress
1 1 0 Ready for byte erase (load address)
1 1 1 Byte erase in progress
MC68HC05B6 MOTOROLA
3-5
MEMORY AND REGISTERS
3
3.5.2 EEPROM read operation
To be able to read from EEPROM, the E1LAT bit has to be at logic zero, as shown in Table 3-1.
While this bit is at logic zero, the E1PGM bit and the E1ERA bit are permanently reset to zero and
the 256 bytes of EEPROM may be read as if it were a normal ROM area. The internal charge
pump generator is automatically switched off since the E1PGM bit is reset.
If a read operation is executed while the E1LAT bit is set (erase or programming sequence), data
resulting from the operation will be $FF.
Note:
When not performing any programming or erase operation, it is recommended that
EEPROM should remain in the read mode (E1LAT = 0)
3.5.3 EEPROM erase operation
To erase the contents of a byte of the EEPROM, the following steps should be taken:
1 Set the E1LAT bit.
2 Set the E1ERA bit (1& 2 may be done simultaneously with the same
instruction).
3 Write address/data to the EEPROM address to be erased.
4 Set the E1PGM bit.
5 Wait for a time t
ERA1
.
6 Reset the E1LAT bit (to logic zero).
While an erase operation is being performed, any access of the EEPROM array will not be
successful.
The erased state of the EEPROM is $FF and the programmed state is $00.
Note:
Data written to the address to be erased is not used, therefore its value is not
significant.
If a second word is to be erased, it is important that the E1LAT bit be reset before restarting the
erasing sequence otherwise any write to a new address will have no effect. This condition provides
a higher degree of security for the stored data.
User programs must be running from the RAM or ROM as the EEPROM will have its address and
data buses latched.
MOTOROLA
3-6
MC68HC05B6MEMORY AND REGISTERS
3
3.5.4 EEPROM programming operation
To program a byte of EEPROM, the following steps should be taken:
1 Set the E1LAT bit.
2 Write address/data to the EEPROM address to be programmed.
3 Set the E1PGM bit.
4 Wait for time t
PROG1
.
5 Reset the E1LAT bit (to logic zero).
While a programming operation is being performed, any access of the EEPROM array will not be
successful.
Warning: To program a byte correctly, it has to have been previously erased.
If a second word is to be programmed, it is important that the E1LAT bit be reset before restarting
the programming sequence otherwise any write to a new address will have no effect. This
condition provides a higher degree of security for the stored data.
User programs must be running from the RAM or ROM as the EEPROM will have its address and
data buses latched.
Note:
224 bytes of EEPR OM (address $0120 to $01FF) can be program and erase protected
under the control of bit 1 of the OPTR register detailed in Section 3.5.5.
3.5.5 Options register (OPTR)
This register (OPTR), located at $0010, contains the secure and protect functions for the
EEPROM and allows the user to select options in a non-volatile manner. The contents of the
OPTR register are loaded into data latches with each power-on or external reset.
(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Options (OPTR)
(1)
$0100
EE1P SEC Not affected
MC68HC05B6 MOTOROLA
3-7
MEMORY AND REGISTERS
3
EE1P – EEPROM protect bit
In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts,
both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to
$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit
of the options register.
1 (set) – Part 2 of the EEPR OM arr ay is not protected; all 256 bytes of EEPROM
can be accessed for any read, erase or programming operations
0 (clear) – Part 2 of the EEPROM array is protected; any attempt to erase or
program a location will be unsuccessful
When this bit is set to 1 (erased), the protection will remain until the next power-on or external
reset. EE1P can only be written to ‘0’ when the ELAT bit in the EEPROM control register is set.
SEC – Security bit
This high security bit allows the user to secure the EEPROM data from external accesses. When
the SEC bit is at ‘0’, the EEPROM contents are secured by preventing any entry to test mode. The
only way to erase the SEC bit to ‘1’ externally is to enter self-check mode, at which time the entire
EEPROM contents will be erased. When the SEC bit is changed, its new value will have no effect
until the next external or power-on reset.
3.6 EEPROM during STOP mode
When entering STOP mode, the EEPROM is automatically set to the read mode and the VPP1
high voltage charge pump generator is automatically disabled.
3.7 EEPROM during WAIT mode
The EEPROM is not affected by WAIT mode. Any program/erase operation will continue as in
normal operating mode. The charge pump is not affected by WAIT mode, therefore it is possible
to wait the t
ERA1
erase time or t
PROG1
programming time in WAIT mode.
Under normal operating conditions, the charge pump generator is driven by the internal CPU
clocks. When the operating frequency is low, e.g. during WAIT mode, the cloc king should be done
by the internal A/D RC oscillator. The RC oscillator is enabled by setting the ADRC bit of the A/D
status/control register at $0009.
MOTOROLA
3-8
MC68HC05B6MEMORY AND REGISTERS
3
(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
Table 3-2 Register outline
Register name Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State on
reset
Port A data (PORTA) $0000 Undefined
Port B data (PORTB) $0001 Undefined
Port C data (PORTC) $0002 PC2/
ECLK
Undefined
Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
Port A data direction (DDRA) $0004 0000 0000
Port B data direction (DDRB) $0005 0000 0000
Port C data direction (DDRC) $0006 0000 0000
EEPROM/ECLK control $0007 0 0 0 0 ECLK E1ERA E1LAT E1PGM 0000 0000
A/D data (ADDATA) $0008 0000 0000
A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000
Pulse length modulation A (PLMA) $000A 0000 0000
Pulse length modulation B (PLMB) $000B 0000 0000
Miscellaneous $000C POR
(1)
INTP INTN INTE SFA SFB SM WDOG
(2)
?001 000?
SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
SCI control 1 (SCCR1) $000E R8 T8
M WAKE CPOL CPHA LBCL Undefined
SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000
SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u
SCI data (SCDR) $0011 0000 0000
Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undefined
Input capture high 1 $0014 Undefined
Input capture low 1 $0015 Undefined
Output compare high 1 $0016 Undefined
Output compare low 1 $0017 Undefined
Timer counter high $0018 1111 1111
Timer counter low $0019 1111 1100
Alternate counter high $001A 1111 1111
Alternate counter low $001B 1111 1100
Input capture high 2 $001C Undefined
Input capture low 2 $001D Undefined
Output compare high 2 $001E Undefined
Output compare low 2 $001F Undefined
Options (OPTR)
(3)
$0100 EE1P SEC Not affected
MC68HC05B6 MOTOROLA
3-9
MEMORY AND REGISTERS
3
3.8 Miscellaneous register
POR — Power-on reset bit (see Section 9.1)
This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the
user to make a software distinction between a power-on and an external reset. This bit cannot be
set by software and is cleared by writing it to zero.
1 (set) – A power-on reset has occurred.
0 (clear) – No power-on reset has occurred.
INTP, INTN — External interrupt sensitivity options (see Section 9.2)
These two bits allow the user to select which edge the
IRQ pin will be sensitive to (see Table 3-3).
Both bits can be written to only while the I-bit is set, and are cleared by power-on or external reset,
thus the device is initialised with negative edge and low level sensitivity.
INTE — External interrupt enable (see Section 9.2)
1 (set) – External interrupt function (
IRQ) enabled.
0 (clear) – External interrupt function (IRQ) disabled.
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,
thus enabling the external interrupt function.
(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Miscellaneous $000C POR
(1)
INTP INTN INTE SFA SFB SM WDOG
(2)
?001 000?
Table 3-3
IRQ sensitivity
INTP INTN IRQ sensitivity
0 0 Negative edge and low level sensitive
0 1 Negative edge only
1 0 Positive edge only
1 1 Positive and negative edge sensitive
MOTOROLA
3-10
MC68HC05B6MEMORY AND REGISTERS
3
SFA — Slow or fast mode selection for PLMA (see Section 7.1)
This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation
output.
1 (set) – Slow mode PLMA (4096 x timer clock period).
0 (clear) – Fast mode PLMA (256 x timer clock period).
SFB — Slow or fast mode selection for PLMB (see Section 7.1)
This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation
output.
1 (set) – Slow mode PLMB (4096 x timer clock period).
0 (clear) – Fast mode PLMB (256 x timer clock period).
Note:
The highest speed of the PLM system corresponds to the frequency of the TOF bit
being set, multiplied by 256. The lowest speed of the PLM system corresponds to the
frequency of the TOF bit being set, multiplied by 16.
Warning: Because the SF A bit and SFB bit are not doub le buffered, it is mandatory to set the SF A
bit and SFB bit to the desired values before writing to the PLM registers; not doing so
could temporarily give incorrect values at the PLM outputs.
SM — Slow mode (see Section 2.4.3)
1 (set) – The system runs at a bus speed 16 times lower than normal
(f
OSC
/32). SLOW mode affects all sections of the device, including
SCI, A/D and timer.
0 (clear) – The system runs at normal bus speed (f
OSC
/2).
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
WDOG — Watchdog enable/disable (see Section 9.1.4)
The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.
Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.
1 (set) – Watchdog counter cleared and enabled.
0 (clear) – The watchdog cannot be disabled by software; writing a zero to this
bit has no effect.
MC68HC05B6 MOTOROLA
4-1
INPUT/OUTPUT PORTS
4
4
INPUT/OUTPUT PORTS
In single-chip mode, the MC68HC05B6 has a total of 24 I/O lines, arranged as three 8-bit ports
(A, B and C), and eight input-only lines, arranged as one 8-bit port (D). Each I/O line is individually
programmable as either input or output, under the software control of the data direction registers .
The 8-bit input-only port (D) shares its pins with the A/D converter, when the A/D converter is
enabled. To avoid glitches on the output pins, data should be written to the I/O port data register
before writing ones to the corresponding data direction register bits to set the pins to output mode .
4.1 Input/output programming
The bidirectional port lines may be programmed as inputs or outputs under software control. The
direction of each pin is determined by the state of the corresponding bit in the port data direction
register (DDR). Each port has an associated DDR. Any I/O port pin is configured as an output if
its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding
DDR bit is cleared to a logic zero.
At power-on or reset, all DDRs are cleared, thus configuring all port pins as inputs. The data
direction registers can be written to or read by the MCU. During the programmed output state, a
read of the data register actually reads the value of the output data latch and not the I/O pin. The
operation of the standard port hardware is shown schematically in Figure 4-1.
MOTOROLA
4-2
MC68HC05B6INPUT/OUTPUT PORTS
4
Table 4-1 shows the effect of reading from or writing to an I/O pin in various circumstances. Note
that the read/write signal shown is internal and not available to the user.
4.2 Ports A and B
These ports are standard M68HC05 bidirectional I/O por ts, each comprising a data register and
a data direction register.
Reset does not affect the state of the data register, but clears the data direction register, thereby
returning all port pins to input mode. Writing a ‘1’ to any DDR bit sets the corresponding port pin
to output mode.
Figure 4-1 Standard I/O port structure
Table 4-1 I/O pin states
R/W DDRn Action of MCU write to/read of data bit
0 0 The I/O pin is in input mode. Data is written into the output data latch.
0 1 Data is written into the output data latch, and output to the I/O pin.
1 0 The state of the I/O pin is read.
1 1 The I/O pin is in output mode. The output data latch is read.
Latched data
register bit
DDRn
DATA
Input
buffer
Output
buffer
O/P
data
buffer
M68HC05 internal connections
DDRn DATA I/O Pin
1 0 0
1 1 1
0 0 tristate
0 1 tristate
I/O
Pin
Output
Input
Data direction
register bit
MC68HC05B6 MOTOROLA
4-3
INPUT/OUTPUT PORTS
4
4.3 Port C
In addition to the standard port functions described for port A and B, port C pin 2 can be
configured, using the ECLK bit of the EEPROM/ECLK control register, to output the CPU clock. If
this is selected the corresponding DDR bit is automatically set and bit 2 of port C will always read
the output data latch. The other port C pins are not affected by this feature.
ECLK — External clock output bit
1 (set) – ECLK CPU clock is output on PC2.
0 (clear) – ECLK CPU clock is not output on PC2; port C acts as a normal I/O port.
The ECLK bit is cleared by power-on or e xternal reset. It is not affected by the execution of a STOP
or WAIT instruction.
The timing diagram of the clock output is shown in Figure 4-2.
4.4 Port D
This 8-bit input-only port shares its pins with the A/D converter subsystem. When the A/D
converter is enabled, pins PD0-PD7 read the eight analog inputs to the A/D con verter. Port D can
be read at any time, however, if it is read during an A/D conversion sequence noise, may be
injected on the analog inputs, resulting in reduced accuracy of the A/D. Furthermore, performing
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
EEPROM/ECLK control $0007 0 0 0 0 ECLK E1ERA E1LAT E1PGM 0000 0000
Figure 4-2 ECLK timing diagram
Internal clock (PHI2)
External clock (ECLK/PC2)
Output port (if write to output port)
MOTOROLA
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MC68HC05B6INPUT/OUTPUT PORTS
4
a digital read of port D with levels other than VDD or VSS on the port D pins will result in greater
power dissipation during the read cycle.
As port D is an input-only port there is no DDR associated with it. Also, at power up or external
reset, the A/D converter is disabled, thus the port is configured as a standard input-only port.
Note:
It is recommended that all unused input ports and I/O ports be tied to an appropr iate
logic level (i.e. either V
DD
or VSS).
4.5 Port registers
The following sections explain in detail the individual bits in the data and control registers
associated with the ports.
4.5.1 Port data registers A and B (PORTA and PORTB)
Each bit can be configured as input or output via the corresponding data direction bit in the port
data direction register (DDRx).
The state of the port data registers following reset is not defined.
4.5.2 Port data register C (PORTC)
Each bit can be configured as input or output via the corresponding data direction bit in the port
data direction register (DDRx).
In addition, bit 2 of port C is used to output the CPU clock if the ECLK bit in the EEPROM
CTL/ECLK register is set (see Section 4.3).
The state of the port data registers following reset is not defined.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Port A data (PORTA) $0000 Undefined
Port B data (PORTB) $0001 Undefined
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Port C data (PORTC) $0002
PC2/
ECLK
Undefined
MC68HC05B6 MOTOROLA
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INPUT/OUTPUT PORTS
4
4.5.3 Port data register D (PORTD)
All the port D bits are input-only and are shared with the A/D converter. The function of each bit is
determined by the ADON bit in the A/D status/control register.
The state of the port data registers following reset is not defined.
4.5.3.1 A/D status/control register
ADON — A/D converter on
1 (set) – A/D converter is switched on; all port D pins act as analog inputs for
the A/D converter.
0 (clear) – A/D converter is switched off; all port D pins act as input only pins.
Reset clears the ADON bit, thus configuring port D as an input only port.
4.5.4 Data direction registers (DDRA, DDRB and DDRC)
Writing a ‘1’ to any bit configures the corresponding port pin as an output; conversely, writing any
bit to ‘0’ configures the corresponding port pin as an input.
Reset clears these registers, thus configuring all ports as inputs.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
A/D status/control $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Port A data direction (DDRA) $0004 0000 0000
Port B data direction (DDRB) $0005 0000 0000
Port C data direction (DDRC) $0006 0000 0000
MOTOROLA
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MC68HC05B6INPUT/OUTPUT PORTS
4
4.6 Other port considerations
All output ports can emulate ‘open-drain’ outputs. This is achieved by writing a zero to the rele vant
output port latch. By toggling the corresponding data direction bit, the por t pin will either be an
output zero or tri-state (an input). This is shown diagrammatically in Figure 4-3.
When using a port pin as an ‘open-drain’ output, certain precautions must be taken in the user
software. If a read-modify-write instruction is used on a port where the ‘open-drain’ is assigned
and the pin at this time is programmed as an input, it will read it as a ‘one’. The read-modify-write
instruction will then write this ‘one’ into the output data latch on the next cycle. This would cause
the ‘open-drain’ pin not to output a ‘zero’ when desired.
Note:
‘Open-drain’ outputs should not be pulled above VDD.
Figure 4-3 Port logic levels
DDRn A Y
(b)
1 0 0
Normal operation – tri state
1 1 1
0 0 tri state
0 1 tri state
1 0 low
‘Open-drain’
1 1 —
0 0 high
0 1 high
Y
A
Read buffer output
Data direction register bit DDRn
Px0
VDD
V
DD
DDRx, bit 0 = 0
Portx, bit 0 = 0
DDRx, bit 0 = 0
Portx, bit 0 = 0
(c)
(a)
‘Open-drain’ output
MC68HC05B6 MOTOROLA
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PROGRAMMABLE TIMER
5
5
PROGRAMMABLE TIMER
The programmable timer on the MC68HC05B6 consists of a 16-bit read-only free-running counter,
with a fixed divide-by-four prescaler, plus the input capture/output compare circuitry. The timer can
be used for many purposes including measuring pulse length of two input signals and generating
two output signals. Pulse lengths for both input and output signals can vary from several
microseconds to many seconds. In addition, it works in conjunction with the pulse width
modulation (PLM) system to execute two 8-bit D/A PLM (pulse length modulation) conversions,
with a choice of two repetition rates. The timer is also capab le of generating periodic interrupts or
indicating passage of an arbitrary multiple of four CPU cycles. A b lock diagram is shown in Figure
5-1, and timing diagrams are shown in Figure 5-2, Figure 5-3, Figure 5-4 and Figure 5-5.
The timer has a 16-bit architecture, hence each specific functional segment is represented by two
8-bit registers (except the PLMA and PLMB which use one 8-bit register for each). These registers
contain the high and low byte of that functional segment. Accessing the low byte of a specific timer
function allows full control of that function; however, an access of the high b yte inhibits that specific
timer function until the low byte is also accessed.
The 16-bit programmable timer is monitored and controlled by a group of sixteen registers, full
details of which are contained in this section.
Note:
A problem may arise if an interrupt occurs in the time between the high and low bytes
being accessed. To prevent this, the I-bit in the condition code register (CCR) should be
set while manipulating both the high and low byte register of a specific timer function,
ensuring that an interrupt does not occur.
5.1 Counter
The key element in the programmable timer is a 16-bit, free-running counter or counter register,
preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the
timer a resolution of 2 s if the internal bus cloc k is 2 MHz. The counter is incremented during the
low portion of the internal bus clock. Software can read the counter at any time without affecting
its value.
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MC68HC05B6PROGRAMMABLE TIMER
5
Figure 5-1 16-bit programmable timer block diagram
Internal
Internal bus
8
Output
compare
register 1
processor
clock
+
+
8-bit
buffer
4
High Low
16-bit
free-running
counter
Counter
alternate
register
register 1
register 2
Input capture
Internal timer bus
Overflow
detect
circuit
Edge
detect
TCAP1
TCMP2
TCMP1
Latch
D
C
Q
compare
Output
register 2
Input capture
byte byte
High
byte
Low
byte
High
byte
Low
byte
High
byte
Low
byte
Low
byte
High
byte
circuit 1
compare
Output
circuit 2
compare
Output
circuit 1
Edge
detect
circuit 2
TCAP2
pin
pin
pin
pin
D
C
Q
Latch
7 6 5 4 3
Timer status
register
Timer control
$0013
$0012
$0018
$0019
$001A
$001B
$001C
$0016
$0017
$0014
$0015
$001E
$001F $001D
To PLM
register
ICF1 OCF1 TOF ICF2 OCF2
ICIE OCIE TOIE FOLV2 OLVL2 IEDG1 OLVL1
FOLV1
Interrupt circuit
Input capture
interrupt
$1FF8,9
Output compare
interrupt
$1FF6,7
Overflow interrupt
$1FF4,5
COP watchdog
counter input
MC68HC05B6 MOTOROLA
5-3
PROGRAMMABLE TIMER
5
5.1.1 Counter register and alternate counter register
The double-byte, free-running counter can be read from either of two locations, $18-$19 (counter
register) or $1A-$1B (alternate counter register). A read from only the less significant byte (LSB)
of the free-running counter ($19 or $1B) receives the count value at the time of the read. If a read
of the free-running counter or alter nate counter register first addresses the more significant byte
(MSB) ($18 or $1A), the LSB is transferred to a buffer. This buffer value remains fixed after the first
MSB read, even if the user reads the MSB several times. This buffer is accessed when reading
the free-running counter or alternate counter register LSB and thus completes a read sequence
of the total counter value. In reading either the free-running counter or alternate counter register,
if the MSB is read, the LSB must also be read to complete the sequence. If the timer overflow flag
(TOF) is set when the counter register LSB is read then a read of the timer status register (TSR)
will clear the flag.
The alternate counter register differs from the counter register only in that a read of the LSB does
not clear TOF. Therefore, where it is critical to avoid the possibility of missing timer overflow
interrupts due to clearing of TOF, the alternate counter register should be used.
The free-running counter is set to $FFFC during power-on and external reset and is always a
read-only register. During a power-on reset, the counter begins running after the oscillator start-up
delay. Because the free-running counter is 16 bits preceded by a fixed divide-by-4 prescaler, the
value in the free-running counter repeats every 262,144 internal bus clock cycles. T OF is set when
the counter overflows (from $FFFF to $0000); this will cause an interrupt if TOIE is set.
In some particular timing control applications it may be desirable to reset the 16-bit free running
counter under software control. When the low byte of the counter ($19 or $1B) is written to, the
counter is configured to its reset value ($FFFC).
The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of
the flags and enable bits remain unaltered by this operation. If access has previously been made
to the high byte of the free-running counter ($18 or $1A), then the reset counter operation
terminates the access sequence.
Warning: This operation may affect the function of the watchdog system (see Section 9.1.4). The
PLM results will also be affected while resetting the counter.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Timer counter high $0018 1111 1111
Timer counter low $0019 1111 1100
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Alternate counter high $001A 1111 1111
Alternate counter low $001B 1111 1100
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MC68HC05B6PROGRAMMABLE TIMER
5
5.2 Timer control and status
The various functions of the timer are monitored and controlled using the timer control and status
registers described below.
5.2.1 Timer control register (TCR)
The timer control register ($0012) is used to enable the input captures (ICIE), output compares
(OCIE), and timer overflow (TOIE) functions as well as forcing output compares (FOLV1 and
FOLV2), selecting input edge sensitivity (IEDG1) and levels of output polarity (OLV1 and OLV2).
ICIE — Input captures interrupt enable
If this bit is set, a timer interrupt is enabled whenever the ICF1 or ICF2 status flag (in the timer
status register) is set.
1 (set) – Interrupt enabled.
0 (clear) – Interrupt disabled.
OCIE — Output compares interrupt enable
If this bit is set, a timer interrupt is enabled whenever the OCF1 or OCF2 status flag (in the timer
status register) is set.
1 (set) – Interrupt enabled.
0 (clear) – Interrupt disabled.
TOIE — Timer overflow interrupt enable
If this bit is set, a timer interrupt is enabled whenever the TOF status flag (in the timer status
register) is set.
1 (set) – Interrupt enabled.
0 (clear) – Interrupt disabled.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
MC68HC05B6 MOTOROLA
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PROGRAMMABLE TIMER
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FOLV2 — Force output compare 2
This bit always reads as z ero, hence writing a zero to this bit has no eff ect. Writing a one at this position
will force the OLV2 bit to the corresponding output level latch, thus appearing at the TCMP2 pin. Note
that this bit does not affect the OCF2 bit of the status register (see Section 5.4.3).
1 (set) – OLV2 bit forced to output level latch.
0 (clear) – No effect.
FOLV1 — Force output compare 1
This bit always reads as z ero, hence writing a zero to this bit has no eff ect. Writing a one at this position
will force the OLV1 bit to the corresponding output level latch, thus appearing at the TCMP1 pin. Note
that this bit does not affect the OCF1 bit of the status register (see Section 5.4.3).
1 (set) – OLV1 bit forced to output level latch.
0 (clear) – No effect.
OLV2 — Output level 2
When OLV2 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level
which will appear on the TCMP2 pin.
1 (set) – A high output level will appear on the TCMP2 pin.
0 (clear) – A low output level will appear on the TCMP2 pin.
IEDG1 — Input edge 1
When IEDG1 is set, a positive-going edge on the TCAP1 pin will trigger a transfer of the
free-running counter value to the input capture register 1. When clear, a negative-going edge
triggers the transfer.
1 (set) – TCAP1 is positive-going edge sensitive.
0 (clear) – TCAP1 is negative-going edge sensitive.
Note:
There is no need for an equivalent bit for the input capture register 2 as TCAP2 is
negative-going edge sensitive only.
OLV1 — Output level 1
When OLV1 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level
which will appear on the TCMP1 pin.
1 (set) – A high output level will appear on the TCMP1 pin.
0 (clear) – A low output level will appear on the TCMP1 pin.
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MC68HC05B6PROGRAMMABLE TIMER
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5.2.2 Timer status register (TSR)
The timer status register ($13) contains the status bits corresponding to the four timer interrupt
conditions – ICF1,OCF1, TOF, ICF2 and OCF2.
Accessing the timer status register satisfies the first condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
ICF1 — Input capture flag 1
This bit is set when the selected polarity of edge is detected by the input capture edge detector 1
at TCAP1; an input capture interrupt will be generated, if ICIE is set. ICF1 is cleared by reading
the TSR and then the input capture low register 1 ($15).
1 (set) – A valid input capture has occurred.
0 (clear) – No input capture has occurred.
OCF1 — Output compare flag 1
This bit is set when the output compare 1 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF1 is cleared by reading
the TSR and then the output compare 1 low register ($17).
1 (set) – A valid output compare has occurred.
0 (clear) – No output compare has occurred.
TOF — Timer overflow status flag
This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow interrupt
will occur if TOIE is set. T OF is cleared b y reading the TSR and the counter low register ($19).
1 (set) – Timer overflow has occurred.
0 (clear) – No timer overflow has occurred.
When using the timer overflow function and reading the free-running counter at random times to
measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally
cleared if:
1 The timer status register is read or written when TOF is set, and
2 The LSB of the free-running counter is read, but not for the purpose of
servicing the flag.
Reading the alternate counter register instead of the counter register will avoid this potential
problem.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undefined
MC68HC05B6 MOTOROLA
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PROGRAMMABLE TIMER
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ICF2 — Input capture flag 2
This bit is set when a negative edge is detected by the input capture edge detector 2 at TCAP2;
an input capture interrupt will be generated if ICIE is set. ICF2 is cleared by reading the TSR and
then the input capture low register 2 ($1D).
1 (set) – A valid (negative) input capture has occurred.
0 (clear) – No input capture has occurred.
OCF2 — Output compare flag 2
This bit is set when the output compare 2 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF2 is cleared by reading
the TSR and then the output compare 2 low register ($1F).
1 (set) – A valid output compare has occurred.
0 (clear) – No output compare has occurred.
5.3 Input capture
‘Input capture’ is a technique whereby an external signal is used to trigger a read of the free
running counter. In this way it is possible to relate the timing of an external signal to the internal
counter value, and hence to elapsed time.
There are two input capture registers: input capture register 1 (ICR1) and input capture register 2 (ICR2).
The same input capture interrupt enable bit (ICIE) is used for the two input captures.
5.3.1 Input capture register 1 (ICR1)
The two 8-bit registers that mak e up the 16-bit input capture register 1 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit 1 senses
a valid transition at TCAP1. The level transition that triggers the counter transfer is defined by the
input edge bit (IEDG1). When an input capture 1 occurs, the corresponding flag ICF1 in TSR is
set. An interrupt can also accompany an input capture 1 provided the ICIE bit in TCR is set. The
8 most significant bits are stored in the input capture high 1 register at $14, the 8 least significant
bits in the input capture low 1 register at $15.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Input capture high 1 $0014 Undefined
Input capture low 1 $0015 Undefined
MOTOROLA
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MC68HC05B6PROGRAMMABLE TIMER
5
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the e xternal transition. This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the input
capture register 1 on each valid signal transition whether the input capture 1 flag (ICF1) is set or
clear. The input capture register 1 always contains the free-running counter value that
corresponds to the most recent input capture 1. After a read of the input capture 1 register MSB
($14), the counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes
the time used in the input capture software routine and its interaction with the main program to
determine the minimum pulse period. A read of the input capture 1 register LSB ($15) does not
inhibit the free-running counter transfer since the two actions occur on opposite edges of the
internal bus clock.
Reset does not affect the contents of the input capture 1 register, e xcept when exiting ST OP mode
(see Section 5.6).
5.3.2 Input capture register 2 (ICR2)
The two 8-bit registers that mak e up the 16-bit input capture register 2 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit 2 senses
a negative transition at pin TCAP2. When an input capture 2 occurs , the corresponding flag ICF2
in TSR is set. An interrupt can also accompany an input capture 2 provided the ICIE bit in TCR is
set.The 8 most significant bits are stored in the input capture 2 high register at $1C, the 8 least
significant bits in the input capture 2 low register at $1D.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the e xternal transition. This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the input
capture register 2 on each negative signal transition whether the input capture 2 flag (IC2F) is set
or clear. The input capture register 2 always contains the free-running counter value that
corresponds to the most recent input capture 2. After a read of the input capture register 2 MSB
($1C), the counter transfer is inhibited until the LSB ($1D) is also read. This characteristic causes
the time used in the input capture software routine and its interaction with the main program to
determine the minimum pulse period. A read of the input capture register 2 LSB ($1C) does not
inhibit the free-running counter transfer since the two actions occur on opposite edges of the
internal bus clock.
Reset does not affect the contents of the input capture 2 register, e xcept when exiting ST OP mode
(see Section 5.6).
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Input capture high 2 $001C Undefined
Input capture low 2 $001D Undefined
MC68HC05B6 MOTOROLA
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PROGRAMMABLE TIMER
5
5.4 Output compare
‘Output compare’ is a technique which may be used, for e xample, to generate an output waveform,
or to signal when a specific time period has elapsed, by presetting the output compare register to
the appropriate value.
There are two output compare registers: output compare register 1 (OCR1) and output compare
register 2 (OCR2).
Note:
The same output compare interrupt enable bit (OCIE) is used for the two output
compares.
5.4.1 Output compare register 1 (OCR1)
The 16-bit output compare register 1 is made up of two 8-bit registers at locations $16 (MSB) and
$17 (LSB). The contents of the output compare register 1 are compared with the contents of the
free-running counter continually and, if a match is found, the corresponding output compare flag
(OCF1) in the timer status register is set and the output level (OLVL1) is transferred to pin TCMP1.
The output compare register 1 values and the output level bit should be changed after each
successful comparison to establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The
free-running counter is updated every four internal bus clock cycles.)
After a processor write cycle to the output compare register 1 containing the MSB ($16), the output
compare function is inhibited until the LSB ($17) is also written. The user must write both bytes
(locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare
1 function. The processor can write to either byte of the output compare register 1 without affecting
the other byte. The output level (OLVL1) bit is clocked to the output level register and hence to the
TCMP1 pin whether the output compare flag 1 (OCF1) is set or clear. The minimum time required
to update the output compare register 1 is a function of the program rather than the internal
hardware. Because the output compare flag 1 and the output compare register 1 are not defined
at power on, and not affected by reset, care must be taken when initializing output compare
functions with software. The following procedure is recommended:
– Write to output compare high 1 to inhibit further compares;
– Read the timer status register to clear OCF1 (if set);
– Write to output compare low 1 to enable the output compare 1 function.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Output compare high 1 $0016 Undefined
Output compare low 1 $0017 Undefined
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MC68HC05B6PROGRAMMABLE TIMER
5
The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
5.4.2 Output compare register 2 (OCR2)
The 16-bit output compare register 2 is made up of two 8-bit registers at locations $1E (MSB) and
$1F (LSB). The contents of the output compare register 2 are compared with the contents of the
free-running counter continually and, if a match is found, the corresponding output compare flag
(OCF2) in the timer status register is set and the output level (OLVL2) is transferred to pin TCMP2.
The output compare register 2 values and the output level bit should be changed after each
successful comparison to establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The
free-running counter is updated every four internal bus clock cycles.)
After a processor write cycle to the output compare register 2 containing the MSB ($1E), the
output compare function is inhibited until the LSB ($1F) is also written. The user must write both
bytes (locations) if the MSB is written first. A write made only to the LSB ($1F) will not inhibit the
compare 2 function. The processor can write to either byte of the output compare register 2
without affecting the other byte. The output level (OLVL2) bit is clocked to the output level register
and hence to the TCMP2 pin whether the output compare flag 2 (OCF2) is set or clear. The
minimum time required to update the output compare register 2 is a function of the program rather
than the internal hardware. Because the output compare flag 2 and the output compare register
2 are not defined at power on, and not affected by reset, care must be taken when initializing
output compare functions with software. The following procedure is recommended:
– Write to output compare high 2 to inhibit further compares;
– Read the timer status register to clear OCF2 (if set);
– Write to output compare low 2 to enable the output compare 2 function.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Output compare high 2 $001E Undefined
Output compare low 2 $001F Undefined
MC68HC05B6 MOTOROLA
5-11
PROGRAMMABLE TIMER
5
The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
5.4.3 Software force compare
A software force compare is required in many applications . T o achie ve this, bit 3 (FOLV1 for OCR1)
and bit 4 (FOL V2 f or OCR2) in the timer control register are used. These bits always read as ‘zero’,
but a write to ‘one’ causes the respective OLVL1 or OLVL2 values to be copied to the respective
output level (TCMP1 and TCMP2 pins).
Internal logic is arranged such that in a single instruction, one can change OLVL1 and/or OLVL2,
at the same time causing a forced output compare with the new values of OLVL1 and OLVL2. In
conjunction with normal compare, this function allows a wide r ange of applications including fix ed
frequency generation.
Note:
A software force compare will affect the corresponding output pin TCMP1 and/or
TCMP2, but will not affect the compare flag, thus it will not generate an interrupt.
5.5 Pulse Length Modulation (PLM)
The programmable timer works in conjunction with the PLM system to execute two 8-bit D/A PLM
conversions, with a choice of two repetition rates (see Section 7).
5.5.1 Pulse length modulation registers A and B (PLMA/PLMB)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Pulse length modulation A (PLMA) $000A 0000 0000
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Pulse length modulation B (PLMB) $000B 0000 0000
MOTOROLA
5-12
MC68HC05B6PROGRAMMABLE TIMER
5
5.6 Timer during STOP mode
When the MCU enters STOP mode, the timer counter stops counting and remains at that
particular count value until STOP mode is exited by an interrupt. If STOP mode is exited by
power-on or external reset, the counter is forced to $FFFC but if it is exited by external interrupt
(
IRQ) then the counter resumes from its stopped value.
Another feature of the programmable timer is that if at least one valid input capture edge occurs
at one of the TCAP pins while in STOP mode, the corresponding input capture detect circuitry is
armed. This action does not wake the MCU or set any timer flags, but when the MCU does
wake-up there will be an active input capture flag (and data) from that first valid edge which
occurred during STOP mode.
If STOP mode is exited by an external reset then no such input capture flag or data action takes
place even if there was a valid input capture edge (at one of the TCAP pins) during STOP mode.
5.7 Timer during WAIT mode
The timer system is not affected by WAIT mode and continues normal operation. Any valid timer
interrupt will wake-up the system.
5.8 Timer state diagrams
The relationships between the internal clock signals, the counter contents and the status of the
flag bits are shown in the following figures. It should be noted that the signals labelled ‘internal’
(processor clock, timer clocks and reset) are not available to the user.
MC68HC05B6 MOTOROLA
5-13
PROGRAMMABLE TIMER
5
Figure 5-2 Timer state timing diagram for reset
Figure 5-3 Timer state timing diagram for input capture
Internal
processor clock
Internal
reset
16-bit
counter
External reset
or end of POR
Internal
timer clocks
$FFFC $FFFD $FFFE $FFFF
Note:
The counter and timer control registers are the only ones affected by power-on or external reset.
T00
T01
T11
T10
Internal
processor clock
16-bit
counter
$F123 $F124 $F125 $F126
Internal
timer clocks
T00
T01
T11
T10
Internal
capture latch
$F124$????
Input capture
register
Input capture
flag
Input
edge
}
}
}
}
Note:
If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then
the input capture flag will be set during the next T11 state.
MOTOROLA
5-14
MC68HC05B6PROGRAMMABLE TIMER
5
Figure 5-4 Timer state timing diagram for output compare
Figure 5-5 Timer state timing diagram for timer overflow
Internal
processor clock
16-bit
counter
$F456 $F457 $F458 $F459
Internal
timer clocks
T00
T01
T11
T10
$F457
CPU writes $F457
Output compare
flag and TCMP1,2
Note: 1 The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state
T01. Thus a four cycle diff erence may exist between the write to the compare register and the actual compare .
2 The output compare flag is set at the timer state T11 that f ollows the comparison match ($F457 in this example).
Output compare
register
Compare register
latch
(Note 2)
(Note 1)
(Note 1)
Internal
processor clock
16-bit
counter
$FFFF $0000 $0001 $0002
Internal
timer clocks
T00
T01
T11
T10
Note:
The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared
by a read of the timer status register during the internal processor clock high time , followed by a read of the
counter low register.
Timer overflow
flag
MC68HC05B6 MOTOROLA
6-1
SERIAL COMMUNICATIONS INTERFACE
6
6
SERIAL COMMUNICATIONS INTERFACE
A full-duplex asynchronous serial communications interface (SCI) is provided with a standard
non-return-to-zero (NRZ) format and a variety of baud rates. The SCI transmitter and receiver are
functionally independent and have their own baud rate generator; however they share a common
baud rate prescaler and data format.
The serial data format is standard mark/space (NRZ) and provides one start bit, eight or nine data
bits, and one stop bit.
The SCLK pin is the output of the transmitter clock. It outputs the transmitter data clock for
synchronous transmission (no clocks on start bit and stop bit, and a software option to send clock
on last data bit). This allows control of peripherals containing shift registers (e.g. LCD drivers).
Phase and polarity of these clocks are software programmable.
Any SCI bidirectional communication requires a two-wire system: receive data in (RDI) and
transmit data out (TDO).
‘Baud’ and ‘bit rate’ are used synonymously in the following description.
6.1 SCI two-wire system features
• Standard NRZ (mark/space) format
• Advanced error detection method with noise detection for noise duration of up to 1/16th bit time
• Full-duplex operation (simultaneous transmit and receive)
• 32 software selectable baud rates
• Different baud rates for transmit and receive; for each transmit baud rate, 8 possible receive
baud rates
• Software selectable word length (eight or nine bits)
• Separate transmitter and receiver enable bits
• Capable of being interrupt driven
• Transmitter clocks available without altering the regular transmitter or receiver functions
• Four separate enable bits for interrupt control
MOTOROLA
6-2
MC68HC05B6SERIAL COMMUNICATIONS INTERFACE
6
Figure 6-1 Serial communications interface block diagram
& & & &
+
+
Internal bus
SCI interrupt
Transmit
Receive
TDO
pin
RDI
Transmitter
control
Receiver
control
clock
Clock extraction
phase and
polarity control
pin
Receiver
clock
Transmitter
Flag
control
data register
data register
TIE
TCIE
RIE
ILIE
TE
RE
SBK
RWU
7
6
5
4
3
2
1
0
$000F
SCCR2
SCSR
$0010
SCCR1
$000E
TRDE TC RDRF IDLE OR NF FE
TE SBK
$0011
(See note) (See note)
R8 T8 M WAKE CPOL CPHA LBCL
012
4
3
6
5
7
7 6 5 2341
SCLK
pin
Wake up
unit
Receive
data shift
register
Transmit
data shift
register
$0011
Note:
The serial communications data register (SCI SCDR) is controlled by the internal
R/
W signal. It is the transmit data register when wr itten to and the receiv e data
register when read.
7
MC68HC05B6 MOTOROLA
6-3
SERIAL COMMUNICATIONS INTERFACE
6
6.2 SCI receiver features
• Receiver wake-up function (idle line or address bit)
• Idle line detection
• Framing error detection
• Noise detection
• Overrun detection
• Receiver data register full flag
6.3 SCI transmitter features
• Transmit data register empty flag
• Transmit complete flag
• Send break
6.4 Functional description
A block diagram of the SCI is shown in Figure 6-1. Option bits in serial control register1 (SCCR1)
select the ‘wake-up’ method (W AKE bit) and data word length (M-bit) of the SCI. SCCR2 provides
control bits that individually enable the transmitter and receiver, enable system interrupts and
provide the wake-up enable bit (RWU) and the send break code bit (SBK). Control bits in the baud
rate register (BAUD) allow the user to select one of 32 different baud rates for the transmitter and
receiver (see Section 6.11.5).
Data transmission is initiated by writing to the serial communications data register (SCDR).
Provided the transmitter is enabled, data stored in the SCDR is transferred to the transmit data
shift register. This transfer of data sets the transmit data register empty flag (TDRE) in the SCI
status register (SCSR) and generates an interrupt (if transmitter interrupts are enabled). The
transfer of data to the transmit data shift register is synchronized with the bit rate clock (see Figure
6-2). All data is transmitted least significant bit first. Upon completion of data transmission, the
transmission complete flag (TC) in the SCSR is set (provided no pending data, preamble or break
is to be sent) and an interrupt is generated (if the transmit complete interrupt is enabled). If the
transmitter is disabled, and the data, preamble or break (in the transmit data shift register) has
been sent, the TC bit will also be set. This will also generate an interrupt if the transmission
complete interrupt enable bit (TCIE) is set. If the transmitter is disab led during a tr ansmission, the
character being transmitted will be completed before the transmitter gives up control of the
TDO pin.
MOTOROLA
6-4
MC68HC05B6SERIAL COMMUNICATIONS INTERFACE
6
When SCDR is read, it contains the last data byte received, provided that the receiver is enabled.
The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has
been transferred from the input serial shift register to the SCDR; this will cause an interrupt if the
receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is
synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error
flags in the SCSR may be set if data reception errors occurred.
An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects
idle line transmission) in SCSR is set. This allows a receiver that is not in the wake-up mode to
detect the end of a message or the preamble of a new message, or to resynchronize with the
transmitter. A v alid character must be receiv ed before the idle line condition or the IDLE bit will not
be set and idle line interrupt will not be generated.
The SCP0 and SCP1 bits function as a prescaler for SCR0–SCR2 to generate the receiver baud rate
and for SCT0–SCT2 to generate the transmitter baud rate. Together , these eight bits provide multiple
transmitter/receiver rate combinations for a given crystal frequency (see Figure 6-2). This register
should only be written to while both the transmitter and receiver are disabled (TE=0, RE=0).
Figure 6-2 SCI rate generator division
SCP1 SPC0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
Internal processor clock
SCP0 – SCP1
prescaler
rate control
( NP)
SCR0 – SCR2
receiver
( NR)
SCT0 – SCT2
transmitter
rate control
( NT)
16
Transmitter clock Receiver clock
rate control
7 6 5 4 3 2 1 0
$000D
Baud rate register
Note:
There is a fixed rate divide-by-16 before the transmitter to compensate for the inherent divide-by-16 of the receiver (sampling).
This means that by loading the same value for both the transmitter and receiver baud rate selector, the same baud rates can be
obtained.
MC68HC05B6 MOTOROLA
6-5
SERIAL COMMUNICATIONS INTERFACE
6
6.5 Data format
Receive data or transmit data is the serial data that is transferred to the internal data bus from the
receive data input pin (RDI) or from the internal bus to the transmit data output pin (TDO). The
non-return-to-zero (NRZ) data format shown in Figure 6-3 is used and must meet the following
criteria:
– The idle line is brought to a logic one state prior to transmission/reception of
a character.
– A start bit (logic zero) is used to indicate the start of a frame.
– The data is transmitted and received least significant bit first.
– A stop bit (logic one) is used to indicate the end of a frame. A frame consists
of a start bit, a character of eight or nine data bits, and a stop bit.
– A break is defined as the transmission or reception of a low (logic zero) for at
least one complete frame time (10 zeros for 8-bit f ormat, 11 zeros for 9-bit).
6.6 Receiver wake-up operation
The receiver logic hardware also supports a receiver wake-up function which is intended for
systems having more than one receiv er. With this function a transmitting device directs messages
to an individual receiver or group of receivers by passing addressing information as the initial
byte(s) of each message. The wake-up function allows receivers not addressed to remain in a
dormant state for the remainder of the unwanted message. This eliminates any further software
overhead to service the remaining characters of the unwanted message and thus improves
system performance.
The receiver is placed in wake-up mode by setting the receiver wake-up bit (RWU) in the SCCR2
register. While RWU is set, all of the receiver related status flags (RDRF, IDLE, OR, NF, and FE)
are inhibited (cannot become set). Note that the idle line detect function is inhibited while the RWU
bit is set. Although RWU may be cleared by a software write to SCCR2, it would be unusual to do
so. Normally RWU is set by software and is cleared automatically in hardware by one of the two
methods described below.
Figure 6-3 Data format
StartStop
Control bit M selects
8 or 9 bit data
Start
Idle line 0 1 2 3 4 5 6 7 8
0
MOTOROLA
6-6
MC68HC05B6SERIAL COMMUNICATIONS INTERFACE
6
6.6.1 Idle line wake-up
In idle line wake-up mode, a dormant receiver wakes up as soon as the RDI line becomes idle.
Idle is defined as a continuous logic high level on the RDI line for ten (or eleven) full bit times.
Systems using this type of wake-up must provide at least one character time of idle between
messages to wake up sleeping receivers, but must not allow any idle time between characters
within a message.
6.6.2 Address mark wake-up
In address mark wake-up, the most significant bit (MSB) in a character is used to indicate whether
it is an address (1) or data (0) character. Sleeping receivers will wake up whenever an address
character is received. Systems using this method for wake-up would set the MSB of the first
character of each message and leave it clear f or all other characters in the message . Idle periods
may be present within messages and no idle time is required between messages for this w ake-up
method.
6.7 Receive data in (RDI)
Receive data is the serial data that is applied through the input line and the SCI to the internal bus.
The receiver circuitry clocks the input at a rate equal to 16 times the baud rate. This time is ref erred
to as the RT rate in Figure 6-4 and as the receiver clock in Figure 6-2.
The receiver clock generator is controlled by the baud rate register, as shown in Figure 6-1 and
Figure 6-2; however, the SCI is synchronized by the start bit, independent of the transmitter.
Once a valid start bit is detected, the star t bit, each data bit and the stop bit are sampled three
times at RT intervals 8 R T, 9 RT and 10 RT (1 RT is the position where the bit is e xpected to start),
as shown in Figure 6-5. The value of the bit is determined by voting logic which takes the value of
the majority of the samples. A noise flag is set when all three samples on a valid start bit or data
bit or the stop bit do not agree.
6.8 Start bit detection
When the input (idle) line is detected low, it is tested for three more sample times (referred to as
the start edge verification samples in Figure 6-4). If at least two of these three verification samples
detect a logic zero, a valid start bit has been detected, otherwise the line is assumed to be idle. A
noise flag is set if one of the three verification samples detect a logic one, thus a valid start bit
could be assumed with a set noise flag present.
MC68HC05B6 MOTOROLA
6-7
SERIAL COMMUNICATIONS INTERFACE
6
If there has been a framing error without detection of a break (10 zeros for 8 bit format or 11 zeros
for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the start
edge will be placed artificially. The last bit received in the data shift register is inverted to a logic
one, and the three logic one start qualifiers (shown in Figure 6-4) are forced into the sample shift
register during the interval when detection of a start bit is anticipated (see Figure 6-6); therefore,
the start bit will be accepted no sooner than it is anticipated.
Figure 6-4 SCI examples of start bit sampling technique
Figure 6-5 SCI sampling technique used on all bits
1 1 1 11 1 1111 1 0 0 0 0
1RT 2RT 3RT 5RT 7RT4RT 6RT 8RT
Start
qualifiers
Idle
Start edge
verification samples
16X internal sampling clock
RT clock edges for all three examples
Noise
Start
1 1 1 11 1 1110 1 0 0 0 0
1 1 1 11 1 1111 1 0 0 1 0
Start
Start
Noise
RDI
RDI
RDI
<<<
SamplesPresent bit Next bitPrevious bit
16RT 1RT 8RT 9RT 10RT 16RT1RT
RDI
MOTOROLA
6-8
MC68HC05B6SERIAL COMMUNICATIONS INTERFACE
6
If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $0000) produced
the framing error, the start bit will not be artificially induced and the receiver must actually detect
a logic one before the start bit can be recognised (see Figure 6-7).
6.9 Transmit data out (TDO)
Transmit data is the serial data from the internal data bus that is applied through the SCI to the
output line. Data format is as discussed in Section 6.5 and shown in Figure 6-3. The transmitter
generates a bit time by using a derivative of the R T clock, thus producing a transmission rate equal
to 1/16th that of the receiver sample clock (assuming the same baud rate is selected for both the
receiver and transmitter).
Figure 6-6 Artificial start following a framing error
Figure 6-7 SCI start bit following a break
Data Expected stop
Data samples
Artificial edge
Start bit
Data
RDI
Data Expected stop
Data samples
Start edge
Start bit
Data
RDI
a) Case 1: receive line low during artificial edge
b) Case 2: receive line high during expected start edge
Expected stop
Data samples
Detected as valid start edge
Start bit
RDI
Break
Start
qualifiers
Start edge
verification
samples
MC68HC05B6 MOTOROLA
6-9
SERIAL COMMUNICATIONS INTERFACE
6
6.10 SCI synchronous transmission
The SCI transmitter allows the user to control a one way synchronous serial transmission. The
SCLK pin is the clock output of the SCI transmitter. No clocks are sent to that pin during start bit
and stop bit. Depending on the state of the LBCL bit (bit 0 of SCCR1), clocks will or will not be
activated during the last valid data bit (address mark). The CPOL bit (bit 2 of SCCR1) allows the
user to select the clock polarity, and the CPHA bit (bit 1 of SCCR1) allows the user to select the
phase of the external clock (see Figure 6-8, Figure 6-9 and Figure 6-10).
During idle, preamble and send break, the external SCLK clock is not activated.
These options allow the user to serially control peripherals which consist of shift registers, without
losing any functions of the SCI transmitter which can still talk to other SCI receivers. These options
do not affect the SCI receiver which is independent of the transmitter.
The SCLK pin works in conjunction with the TDO pin. When the SCI transmitter is disabled
(TE = 0), the SCLK and TDO pins go to the high impedance state.
Note:
The LBCL, CPOL and CPHA bits have to be selected before enabling the transmitter
to ensure that the clocks function correctly. These bits should not be changed while the
transmitter is enabled.
Figure 6-8 SCI example of synchronous and asynchronous transmission
RDI
TDO
SCLK
Output port
Data out
Data in
Data in
Clock
Enable
Asynchronous
MC68HC05B6
(e.g. Modem)
Synchronous
(e.g. shift register,
display driver, etc.)
MOTOROLA
6-10
MC68HC05B6SERIAL COMMUNICATIONS INTERFACE
6
6.11 SCI registers
The SCI system is configured and controlled by five registers: SCDR, SCCR1, SCCR2, SCSR,
and BAUD.
6.11.1 Serial communications data register (SCDR)
The SCDR is controlled by the internal R/W signal and performs two functions in the SCI. It acts
as the receive data register (RDR) when it is read and as the transmit data register (TDR) when
it is written. Figure 6-1 shows this register as two separate registers, RDR and TDR. The RDR
provides the interface from the receive shift register to the internal data bus and the TDR pro vides
the parallel interface from the internal data bus to the transmit shift register.
The receive data register is a read-only register containing the last byte of data received from the
shift register for the internal data bus. The RDR full bit (RDRF) in the serial communications status
register is set to indicate that a byte has been transferred from the input serial shift register to the
SCDR. The transfer is synchronized with the receiver bit rate clock (from the receiver control) as
shown in Figure 6-1. All data is received with the least significant bit first.
The transmit data register (TDR) is a write-only register containing the next byte of data to be
applied to the transmit shift register from the internal data bus. As long as the transmitter is
enabled, data stored in the SCDR is transferred to the tr ansmit shift register (after the current byte
in the shift register has been transmitted).
The transfer is synchronized with the transmitter bit rate clock (from the transmitter control) as
shown in Figure 6-1. All data is received with the least significant bit first.
6.11.2 Serial communications control register 1 (SCCR1)
The SCI control register 1 (SCCR1) contains control bits related to the nine data bit character
format, the receiver wake-up feature and the options to output the transmitter clocks for
synchronous transmissions.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
SCI data (SCDR) $0011 0000 0000
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undefined
MC68HC05B6 MOTOROLA
6-11
SERIAL COMMUNICATIONS INTERFACE
6
R8 — Receive data bit 8
This read-only bit is the ninth serial data bit received when the SCI system is configured for nine
data bit operation (M = 1). The most significant bit (bit 8) of the received character is transferred
into this bit at the same time as the remaining eight bits (bits 0–7) are transferred from the serial
receive shifter to the SCI receive data register.
T8 — Transmit data bit 8
This read/write bit is the ninth data bit to be transmitted when the SCI system is configured for nine
data bit operation (M = 1). When the eight low order bits (bits 0–7) of a transmit character are
transferred from the SCI data register to the serial transmit shift register, this bit (bit 8) is
transferred to the ninth bit position of the shifter.
M — Mode (select character format)
The read/write M-bit controls the character length for both the transmitter and receiver at the same
time. The 9th data bit is most commonly used as an extra stop bit or in conjunction with the
‘address mark’ wake-up method. It can also be used as a parity bit (see Table 6-1).
1 (set) – Start bit, 8 data bits, 1 stop bit.
0 (clear) – Start bit, 9 data bits, 1 stop bit.
WAKE — Wake-up mode select
This bit allows the user to select the method for receiver wake-up. The WAKE bit can be read or
written to any time. See Table 6-1.
1 (set) – Wake-up on address mark.
0 (clear) – Wake-up on idle line.
Table 6-1 Method of receiver wake-up
WAKE M Method of receiver wake-up
0 x
Detection of an idle line allows the next data type received to cause the receive
data register to fill and produce an RDRF flag.
1 0
Detection of a received one in the eighth data bit allows an RDRF flag and
associated error flags.
1 1
Detection of a received one in the ninth data bit allows an RDRF flag and
associated error flags.
x = Don’t care
MOTOROLA
6-12
MC68HC05B6SERIAL COMMUNICATIONS INTERFACE
6
CPOL – Clock polarity
This bit allows the user to select the polarity of the clocks to be sent to the SCLK pin. It works in
conjunction with the CPHA bit to produce the desired clock-data relation (see Figure 6-9 and
Figure 6-10).
1 (set) – Steady high value at SCLK pin outside transmission window.
0 (clear) – Steady low value at SCLK pin outside transmission window.
This bit should not be manipulated while the transmitter is enabled.
CPHA – Clock phase
This bit allows the user to select the phase of the clocks to be sent to the SCLK pin. This bit works
in conjunction with the CPOL bit to produce the desired clock-data relation (see Figure 6-9 and
Figure 6-10).
1 (set) – SCLK clock line activated at beginning of data bit.
0 (clear) – SCLK clock line activated in middle of data bit.
This bit should not be manipulated while the transmitter is enabled.
Figure 6-9 SCI data clock timing diagram (M=0)
Idle or preceding
transmission
clock
Stop
Start
LSB
data
M = 0 (8 data bits)
Idle or next
LBCL bit controls last data clock
transmission
clock
clock
clock
*
*
*
*
*
Start Stop
0 1 2 3 4 5 6
MSB
7
(CPOL = 0, CPHA = 0)
(CPOL = 0, CPHA = 1)
(CPOL = 1, CPHA = 0)
(CPOL = 1, CPHA = 1)
MC68HC05B6 MOTOROLA
6-13
SERIAL COMMUNICATIONS INTERFACE
6
LBCL – Last bit clock
This bit allows the user to select whether the clock associated with the last data bit transmitted
(MSB) has to be output to the SCLK pin. The clock of the last data bit is output to the SCLK pin if
the LBCL bit is a logic one, and is not output if it is a logic zero.
The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected by
M-bit (seeTable 6-2).
This bit should not be manipulated while the transmitter is enabled.
Figure 6-10 SCI data clock timing diagram (M=1)
Table 6-2 SCI clock on SCLK pin
Data format M-bit LBCL bit
Number of clocks on
SCLK pin
8 bit 0 0 7
8 bit 0 1 8
9 bit 1 0 8
9 bit 1 1 9
Idle or preceding
transmission
clock
StopStart
LSB
data
M = 1 (9 data bits)
Idle or next
LBCL bit controls last data clock
transmission
clock
clock
clock
*
*
*
*
Start Stop
0 1 2 3 4 5 6
MSB
7
*
8
(CPOL = 0, CPHA = 0)
(CPOL = 0, CPHA = 1)
(CPOL = 1, CPHA = 0)
(CPOL = 1, CPHA = 1)
MOTOROLA
6-14
MC68HC05B6SERIAL COMMUNICATIONS INTERFACE
6
6.11.3 Serial communications control register 2 (SCCR2)
The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI
functions.
TIE — Transmit interrupt enable
1 (set) – TDRE interrupts enabled.
0 (clear) – TDRE interrupts disabled.
TCIE — Transmit complete interrupt enable
1 (set) – TC interrupts enabled.
0 (clear) – TC interrupts disabled.
RIE — Receiver interrupt enable
1 (set) – RDRF and OR interrupts enabled.
0 (clear) – RDRF and OR interrupts disabled.
ILIE — Idle line interrupt enable
1 (set) – IDLE interrupts enabled.
0 (clear) – IDLE interrupts disabled.
TE — Transmitter enable
When the transmit enable bit is set, the tr ansmit shift register output is applied to the TDO line and
the corresponding clocks are applied to the SCLK pin. Depending on the state of control bit M
(SCCR1), a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones is transmitted when software
sets the TE bit from a cleared state.
If a transmission is in progress and a zero is written to TE, the transmitter will wait until after the
present byte has been transmitted before placing the TDO and the SCLK pin in the idle, high
impedance state.
If the TE bit has been written to a zero and then set to a one before the current byte is transmitted,
the transmitter will wait for that byte to be transmitted and will then initiate transmission of a new
preamble. After this latest transmission, and provided the TDRE bit is set (no new data to
transmit), the line remains idle (driven high while TE = 1); otherwise, normal transmission occurs.
This function allows the user to neatly terminate a transmission sequence.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
SCI control (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000
MC68HC05B6 MOTOROLA
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SERIAL COMMUNICATIONS INTERFACE
6
After loading the last byte in the serial communications data register and receiving the TDRE flag,
the user should clear TE. Transmission of the last byte will then be completed and the line will go
idle.
1 (set) – Transmitter enabled.
0 (clear) – Transmitter disabled.
RE — Receiver enable
1 (set) – Receiver enabled.
0 (clear) – Receiver disabled.
When RE is clear (receiver disabled) all the status bits associated with the receiver (RDRF, IDLE,
OR, NF and FE) are inhibited.
RWU — Receiver wake-up
When the receiver wake-up bit is set by the user software, it puts the receiv er to sleep and enables
the wake-up function. The type of wake-up mode for the receiver is determined by the WAKE bit
discussed above (in the SCCR1). When the RWU bit is set, no status flags will be set. Flags which
were set previously will not be cleared when RWU is set.
If the WAKE bit is cleared, R WU is cleared by the SCI logic after receiving 10 (M = 0) or 11 (M =1)
consecutive ones. Under these conditions, RWU cannot be set if the line is idle. If the WAKE bit
is set, RWU is cleared after receiving an address bit. The RDRF flag will then be set and the
address byte stored in the receiver data register.
SBK — Send break
If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11 (M = 1)
zeros and then reverts to idle sending data. If SBK remains set, the transmitter will continually
send whole blocks of zeros (sets of 10 or 11) until cleared. At the completion of the break code,
the transmitter sends at least one high bit to guarantee recognition of a valid start bit.
MOTOROLA
6-16
MC68HC05B6SERIAL COMMUNICATIONS INTERFACE
6
6.11.4 Serial communications status register (SCSR)
The serial communications status register (SCSR) pro vides inputs to the interrupt logic circuits for
generation of the SCI system interrupt. In addition, a noise flag bit and a framing error bit are also
contained in the SCSR.
TDRE — Transmit data register empty flag
This bit is set when the contents of the transmit data register are transferred to the serial shift
register. New data will not be transmitted unless the SCSR register is read before writing to the
transmit data register to clear the TDRE flag.
If the TDRE bit is clear, this indicates that the transfer has not yet occurred and a write to the serial
communications data register will overwrite the previous value. The TDRE bit is cleared by
accessing the serial communications status register (with TDRE set) followed by writing to the
serial communications data register.
TC — Transmit complete flag
This bit is set to indicate that the SCI transmitter has no meaningful information to transmit (no
data in shifter, no preamble, no break). When TC is set the serial line will go idle (continuous
MARK). The TC bit is cleared by accessing the serial communications data register (with TC set)
followed by writing to the serial communications data register. It does not inhibit the transmitter
function in any way.
RDRF — Receive data register full flag
This bit is set when the contents of the receiver serial shift register are transferred to the receiver
data register.
If multiple errors are detected in any one received word, the NF and RDRF bits will be aff ected as
appropriate during the same clock cycle. The RDRF bit is cleared when the serial communications
status register is accessed (with RDRF set) followed by a read of the serial communications data
register.
IDLE — Idle line detected flag
This bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven
consecutive “1”s). This bit will not be set by the idle line condition when the RWU bit is set. This
allows a receiver that is not in the wake-up mode to detect the end of a message, detect the
preamble of a new message or resynchronize with the transmitter. The IDLE bit is cleared by
accessing the serial communications status register (with IDLE set) followed b y a read of the serial
communications data register. Once cleared, IDLE will not be set again until after RDRF has been
set, (i.e. until after the line has been active and becomes idle again).
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u
MC68HC05B6 MOTOROLA
6-17
SERIAL COMMUNICATIONS INTERFACE
6
OR — Overrun error flag
This bit is set when a new byte is ready to be transferred from the receiver shift register to the
receiver data register and the receive data register is already full (RDRF bit is set). Data transfer
is inhibited until the RDRF bit is cleared. Data in the serial communications data register is valid
in this case, but additional data received during an overrun condition (including the byte causing
the overrun) will be lost.
The OR bit is cleared when the serial communications status register is accessed (with OR set)
followed by a read of the serial communications data register.
NF — Noise error flag
This bit is set if there is noise on a ‘valid’ start bit, any of the data bits or on the stop bit. The NF
bit is not set by noise on the idle line nor by invalid start bits. If there is noise, the NF bit is not set
until the RDRF flag is set. Each data bit is sampled three times as described in Section 6.7.
The NF bit represents the status of the byte in the serial communications data register. For the
byte being received (shifted in) there will be also a ‘working’ noise flag, the value of which will be
transferred to the NF bit when the serial data is loaded into the serial communications data
register. The NF bit does not generate an interrupt because the RDRF bit gets set with NF and
can be used to generate the interrupt.
The NF bit is cleared when the serial communications status register is accessed (with NF set)
followed by a read of the serial communications data register.
FE — Framing error flag
This bit is set when the word boundaries in the bit stream are not synchronized with the receiver
bit counter (generated by the reception of a logic zero bit where a stop bit was expected). The FE
bit reflects the status of the byte in the receive data register and the transfer from the receive
shifter to the receive data register is inhibited by an overrun. The FE bit is set during the same
cycle as the RDRF bit but does not get set in the case of an overrun (OR). The framing error flag
inhibits further transfer of data into the receive data register until it is cleared.
The FE bit is cleared when the serial communications status register is accessed (with FE set)
followed by a read of the serial communications data register.
MOTOROLA
6-18
MC68HC05B6SERIAL COMMUNICATIONS INTERFACE
6
6.11.5 Baud rate register (BAUD)
The baud rate register provides the means to select two different or equivalent baud rates for the
transmitter and receiver.
SCP1, SCP0 — Serial prescaler select bits
These read/write bits determine the prescale factor, NP, by which the inter nal processor clock is
divided before it is applied to the transmitter and receiver rate control dividers, NT and NR. This
common prescaled output is used as the input to a divider that is controlled by the SCR0–SCR2
bits for the SCI receiver, and by the SCT0–SCT2 bits for the transmitter.
SCT2, SCT1,SCT0 — SCI rate select bits (transmitter)
These three read/write bits select the baud rates for the transmitter. The prescaler output is
divided by the factors shown in Table 6-4.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
SCI baud rate (BAUD) $000D SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 00uu uuuu
Table 6-3 First prescaler stage
SCP1 SCP0
Prescaler
division ratio (NP)
0 0 1
0 1 3
1 0 4
1 1 13
Table 6-4 Second prescaler stage (transmitter)
SCT2 SCT1 SCT0
Transmitter
division ratio (NT)
0 0 0 1
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 16
1 0 1 32
1 1 0 64
1 1 1 128
MC68HC05B6 MOTOROLA
6-19
SERIAL COMMUNICATIONS INTERFACE
6
SCR2, SCR1, SCR0 — SCI rate select bits (receiver)
These three read/write bits select the baud rates for the receiver. The prescaler output described
above is divided by the factors shown in Table 6-5.
The following equations are used to calculate the receiver and transmitter baud rates:
where:
NP = prescaler divide ratio
NT = transmitter baud rate divide ratio
NR = receiver baud rate divide ratio
baudTx = transmitter baud rate
baudRx = receiver baud rate
f
OSC
= oscillator frequency
6.12 Baud rate selection
The flexibility of the baud rate generator allows many different baud rates to be selected. A
particular baud rate may be generated in several ways by manipulating the various prescaler and
division ratio bits. Table 6-6 shows the baud rates that can be achieved, for five typical crystal
frequencies. These are effectively the highest baud rates which can be achieved using a given
crystal.
Table 6-5 Second prescaler stage (receiver)
SCR2 SCR1 SCR0
Receiver
division ratio (NR)
0 0 0 1
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 16
1 0 1 32
1 1 0 64
1 1 1 128
baudTx
f
osc
32 NP N
T• •
----------------------------------
=
baudRx
f
osc
32 NP NR• •
--------------------------------
---
=
MOTOROLA
6-20
MC68HC05B6SERIAL COMMUNICATIONS INTERFACE
6
Note:
The examples shown above do not apply when the part is operating in slow mode (see
Section 2.4.3).
Table 6-6 SCI baud rate selection
Crystal frequency – f
osc
(MHz)
SCP1 SCP0 SCT/R2 SCT/R1 SCT/R0 NP NT/NR 4.194304 4.00 2.4576 2.00 1.8432
0 0 0 0 0 1 1 131072 125000 76800 62500 57600
0 0 0 0 1 1 2 65536 62500 38400 31250 28800
0 0 0 1 0 1 4 32768 31250 19200 15625 14400
0 0 0 1 1 1 8 16384 15625 9600 7813 7200
0 0 1 0 0 1 16 8192 7813 4800 3906 3600
0 0 1 0 1 1 32 4096 3906 2400 1953 1800
0 0 1 1 0 1 64 2048 1953 1200 977 900
0 0 1 1 1 1 128 1024 977 600 488 450
0 1 0 0 0 3 1 43691 41667 25600 20833 19200
0 1 0 0 1 3 2 21845 20833 12800 10417 9600
0 1 0 1 0 3 4 10923 10417 6400 5208 4800
0 1 0 1 1 3 8 5461 5208 3200 2604 2400
0 1 1 0 0 3 16 2731 2604 1600 1302 1200
0 1 1 0 1 3 32 1365 1302 800 651 600
0 1 1 1 0 3 64 683 651 400 326 300
0 1 1 1 1 3 128 341 326 200 163 150
1 0 0 0 0 4 1 32768 31250 19200 15625 14400
1 0 0 0 1 4 2 16384 15625 9600 7813 7200
1 0 0 1 0 4 4 8192 7813 4800 3906 3600
1 0 0 1 1 4 8 4096 3906 2400 1953 1800
1 0 1 0 0 4 16 2048 1953 1200 977 900
1 0 1 0 1 4 32 1024 977 600 488 450
1 0 1 1 0 4 64 512 488 300 244 225
1 0 1 1 1 4 128 256 244 150 122 113
1 1 0 0 0 13 1 10082 9615 5908 4808 4431
1 1 0 0 1 13 2 5041 4808 2954 2404 2215
1 1 0 1 0 13 4 2521 2404 1477 1202 1108
1 1 0 1 1 13 8 1260 1202 738 601 554
1 1 1 0 0 13 16 630 601 369 300 277
1 1 1 0 1 13 32 315 300 185 150 138
1 1 1 1 0 13 64 158 150 92 75 69
1 1 1 1 1 13 128 79 75 46 38 35
MC68HC05B6 MOTOROLA
6-21
SERIAL COMMUNICATIONS INTERFACE
6
6.13 SCI during STOP mode
When the MCU enters STOP mode, the baud rate generator driving the receiver and transmitter
is shut down. This stops all SCI activity. Both the receiver and the transmitter are unable to
operate.
If the STOP instruction is executed during a transmitter transfer, that transfer is halted. When
STOP mode is exited as a result of an external interrupt, that particular transmission resumes.
If the receiver is receiving data when the STOP instruction is executed, received data sampling is
stopped (baud generator stops) and the rest of the data is lost.
Warning: For the above reasons, all SCI transactions should be in the idle state when the ST OP
instruction is executed.
6.14 SCI during WAIT mode
The SCI system is not affected by WAIT mode and continues normal operation. Any valid SCI
interrupt will wake-up the system. If required, the SCI system can be disabled prior to entering
WAIT mode by writing a zero to the transmitter and receiver enable bits in the serial
communication control register 2 at $000F. This action will result in a reduction of power
consumption during WAIT mode.
MOTOROLA
6-22
MC68HC05B6SERIAL COMMUNICATIONS INTERFACE
THIS PAGE INTENTIONALLY LEFT BLANK
6
MC68HC05B6 MOTOROLA
7-1
PULSE LENGTH D/A CONVERTERS
7
7
PULSE LENGTH D/A CONVERTERS
The pulse length D/A converter (PLM) system works in conjunction with the timer to execute two
8-bit D/A conversions, with a choice of two repetition rates. (See Figure 7-1.)
Figure 7-1 PLM system block diagram
PLMA
register
PLMB
‘A’ register
buffer
‘B’ register
‘A’
comparator
‘B’
Latch
Zero detector
SFA
bit
SFB
D/A
pin
Timer bus From timer
Data bus
8
16
multiplexer
‘A’
‘B’
buffer
register
comparator
multiplexer
PLMA
PLMB
D/A
R
S
bit
Zero detector
8
16
8 8
pin
Latch
R
S
MOTOROLA
7-2
MC68HC05B6PULSE LENGTH D/A CONVERTERS
7
The D/A converter has two data registers associated with it, PLMA and PLMB.
This is a dual 8-bit resolution D/A converter associated with two output pins (PLMA and PLMB).
The outputs are pulse length modulated signals whose duty cycle ratio may be modified. These
signals can be used directly as PLMs, or the filtered average may be used as general purpose
analog outputs.
The longest repetition period is 4096 times the programmable timer clock period (CPU clock
multiplied by four), and the shortest repetition period is 256 times the programmable timer clock
period (the repetition rate frequencies for a 4 MHz crystal are 122 Hz and 1953 Hz respectively).
Registers PLMA ($0A) and PLMB ($0B) are associated with the pulse length values of the two
counters. A value of $00 loaded into these registers results in a continuously low output on the
corresponding D/A output pin. A value of $80 results in a 50% duty cycle output, and so on, to the
maximum value $FF corresponding to an output which is at ‘1’ f or 255/256 of the cycle . When the
MCU makes a write to register PLMA or PLMB the new value will only be picked up by the D/A
converters at the end of a complete cycle of conversion. This results in a monotonic change of the
DC component at the output without overshoots or vicious starts (a vicious start is an output which
gives totally erroneous PLM during the period immediately following an update of the PLM D/A
registers). This feature is achieved by double buffering of the PLM D/A registers. Examples of
PWM output waveforms are shown in Figure 7-2.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Pulse length modulation A (PLMA) $000A 0000 0000
Pulse length modulation B (PLMB) $000B 0000 0000
Figure 7-2 PLM output waveform examples
256 T
255 T
128 T
T
$80
$FF
T = 4 CPU clocks in fast mode and 64 CPU clocks in slow mode
128 T
T
$00
$01
255 T
MC68HC05B6 MOTOROLA
7-3
PULSE LENGTH D/A CONVERTERS
7
Note:
Since the PLM system uses the timer counter, PLM results will be affected while resetting
the timer counter. Both D/A registers are reset to $00 during power-on or external reset.
WAIT mode does not affect the output waveform of the D/A converters .
7.1 Miscellaneous register
SFA — Slow or fast mode selection for PLMA
This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation
output.
1 (set) – Slow mode PLMA (4096 x timer clock period).
0 (clear) – Fast mode PLMA (256 x timer clock period).
SFB — Slow or fast mode selection for PLMB
This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation
output.
1 (set) – Slow mode PLMB (4096 x timer clock period).
0 (clear) – Fast mode PLMB (256 x timer clock period).
The highest speed of the PLM system corresponds to the frequency of the TOF bit being set,
multiplied by 256. The lowest speed of the PLM system corresponds to the frequency of the TOF
bit being set, multiplied by 16. Because the SFA bit and SFB bit are not double buffered, it is
mandatory to set them to the desired values before writing to the PLM registers; not doing so could
temporarily give incorrect values at the PLM outputs.
SM — Slow mode
1 (set) – The system runs at a bus speed 16 times lower than normal
(f
OSC
/32). SLOW mode affects all sections of the device, including
SCI, A/D and timer.
0 (clear) – The system runs at normal bus speed (f
OSC
/2).
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Miscellaneous $000C POR INTP INTN INTE SFA SFB SM WDOG ?001 000?
MOTOROLA
7-4
MC68HC05B6PULSE LENGTH D/A CONVERTERS
7
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
Note:
The bits that are shown shaded in the above representation are explained individually
in the relevant sections of this manual. The complete register plus an explanation of
each bit can be found in Section 3.8
7.2 PLM clock selection
The slow/fast mode of the PLM D/A converters is selected by bits 1, 2, and 3 of the miscellaneous
register at address $000C (SFA bit for PLMA and SFB bit for PLMB). The slow/fast mode has no
effect on the D/A converters’ 8-bit resolution (see Figure 7-3).
7.3 PLM during STOP mode
On entering STOP mode, the PLM outputs remain at their par ticular level. When STOP mode is
exited by an interrupt, the PLM systems resume regular operation. If STOP mode is exited by
power-on or external reset the registers values are forced to $00.
7.4 PLM during WAIT mode
The PLM system is not affected by WAIT mode and continues normal operation.
Figure 7-3 PLM clock selection
f
OSC
2
32
SM bit = 0
SM bit = 1
4 x4096
x256
SF bit = 1
SF bit = 0
Timer
clock
PLM
clock
Bus
frequency (f
OP
)
MC68HC05B6 MOTOROLA
8-1
ANALOG TO DIGITAL CONVERTER
8
8
ANALOG TO DIGITAL CONVERTER
The analog to digital converter system consists of a single 8-bit successive approximation
converter and a sixteen channel multiplexer. Eight of the channels are connected to the
PD0/AN0 – PD7/AN7 pins of the MC68HC05B6 and the other eight channels are dedicated to
internal reference points for test functions. The channel input pins do not have any internal output
driver circuitry connected to them because such circuitry would load the analog input signals due
to output buffer leakage current. There is one 8-bit result data register (address $08) and one 8-bit
status/control register (address $09).
The A/D converter is ratiometric and two dedicated pins, VRH and VRL, are used to supply the
reference voltage levels for all analog inputs. These pins are used in preference to the system
power supply lines because any voltage drops in the bonding wires of the heavily loaded supply
pins could degrade the accuracy of the A/D conversion. An input voltage equal to or greater than
V
RH
converts to $FF (full scale) with no overflow indication and an input voltage equal to V
RL
converts to $00.
The A/D converter can operate from either the bus clock or an inter nal RC type oscillator. The
internal RC type oscillator is activated by the ADRC bit in the A/D status/control register (ADSTAT)
and can be used to give a sufficiently high clock rate to the A/D converter when the bus speed is too
low to provide accurate results. When the A/D converter is not being used it can be disconnected,
by clearing the ADON bit in the ADSTAT register, in order to save power (see Section 8.2.3).
For further information on A/D converter operation please refer to the M68HC11 Reference
Manual — M68HC11RM/AD.
8.1 A/D converter operation
The A/D converter consists of an analog multiplexer, an 8-bit digital to analog con verter capacitor
array, a comparator and a successive approximation register (SAR) (see Figure 8-1).
There are eleven options that can be selected by the multiplexer; AN0–AN7, VRH, (VRH+VRL)/2
or VRL. Selection is done via the CHx bits in the ADSTAT register (see Section 8.2.3). AN0–AN7
are the only input points for A/D conversion operations; the others are reference points that can
be used for test purposes.
MOTOROLA
8-2
MC68HC05B6ANALOG TO DIGITAL CONVERTER
8
The A/D reference input (AN0–AN7) is applied to a precision internal D/A converter. Control logic
drives this D/A converter and the analog output is successively compared with the analog input
sampled at the beginning of the conversion. The conversion is monotonic with no missing codes.
The result of each successive comparison is stored in the SAR and, when the conversion is
complete, the contents of the SAR are transferred to the read-only result data register ($08), and
the conversion complete flag, COCO, is set in the A/D status/control register ($09).
Warning: Any write to the A/D status/control register will abort the current conversion, reset the
conversion complete flag and start a new conversion on the selected channel.
At power-on or external reset, both the ADRC and ADON bits are cleared; thus the A/D is disabled.
Figure 8-1 A/D converter block diagram
AN0
VRH
(VRH+VRL)/2
VRL
Analog MUX
A/D result register (ADDATA) $08
8-bit capacitive DAC
with sample and hold
VRH
VRL
Result
A/D status/control register (ADSTAT)$09
(Channel assignment)
COCO
ADRCADON0CH3CH2CH1CH0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Successive approximation
register (SAR) and control
MC68HC05B6 MOTOROLA
8-3
ANALOG TO DIGITAL CONVERTER
8
8.2 A/D registers
8.2.1 Port D data register (PORTD)
Port D is an input-only port which routes the eight analog inputs to the A/D converter. When the
A/D converter is disabled, the pins are configured as standard input-only port pins, which can be
read via the port D data register.
Note:
When the A/D function is enabled, pins PD0–PD7 will act as analog inputs. Using a pin
or pins as A/D inputs does not affect the ability to read port D as static inputs; however,
reading port D during an A/D conversion sequence may inject noise on the analog
inputs and result in reduced accuracy of the A/D result.
Performing a digital read of por t D with levels other than V
DD
or VSS on the pins will
result in greater power dissipation during the read cycle, and may give unpredictable
results on the corresponding port D pins.
8.2.2 A/D result data register (ADDATA)
ADDATA is a read-only register which is used to store the results of A/D conversions. Each result
is loaded into the register from the SAR and the conversion complete flag, COCO , in the ADSTAT
register is set.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
A/D data (ADDATA) $0008 0000 0000
MOTOROLA
8-4
MC68HC05B6ANALOG TO DIGITAL CONVERTER
8
8.2.3 A/D status/control register (ADSTAT)
COCO — Conversion complete flag
1 (set) – COCO is set each time a conversion is complete, allowing the new
result to be read from the A/D result data register ($08). The
converter then starts a new conversion.
0 (clear) – COCO is cleared by reading the result data register or writing to the
status/control register.
Reset clears the COCO flag.
ADRC — A/D RC oscillator control
The ADRC bit allows the user to control the A/D RC oscillator, which is used to provide a
sufficiently high clock rate to the A/D to ensure accuracy when the chip is running at low speeds.
1 (set) – When the ADRC bit is set, the A/D RC oscillator is turned on and, if
ADON is set, the A/D runs from the RC oscillator clock. See Table 8-1.
0 (clear) – When the ADRC bit is cleared, the A/D RC oscillator is turned-off
and, if ADON is set, the A/D runs from the CPU clock.
When the A/D RC oscillator is turned on, it takes a time t
ADRC
to stabilize (see Table 11-7 and
Table 11-8). During thistime A/D conversion results may be inaccurate.
Note:
If the MCU bus clock falls below 1MHz, the A/D RC oscillator should be switched on.
Power-on or external reset clears the ADRC bit.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
State
on reset
A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000
Table 8-1 A/D clock selection
ADRC ADON
RC
oscillator
A/D
converter
Comments
0 0 OFF OFF A/D switched off.
0 1 OFF ON A/D using CPU clock.
1 0 ON OFF Allows the RC oscillator to stabilize.
1 1 ON ON A/D using RC oscillator clock.
MC68HC05B6 MOTOROLA
8-5
ANALOG TO DIGITAL CONVERTER
8
ADON — A/D converter on
The ADON bit allows the user to enable/disable the A/D converter.
1 (set) – A/D converter is switched on.
0 (clear) – A/D converter is switched off.
When the A/D converter is switched on, it takes a time t
ADON
for the current sources to stabilize
(see Table 11-7 and Table 11-8). During this time A/D conversion results may be inaccurate.
Power-on or external reset will clear the ADON bit, thus disabling the A/D converter.
CH3–CH0 — A/D channels 3, 2, 1 and 0
The CH3–CH0 bits allow the user to determine which channel of the A/D converter multiplexer is
selected. See Table 8-2 for channel selection.
Reset clears the CH0–CH3 bits.
8.3 A/D converter during STOP mode
When the MCU enters STOP mode with the A/D converter turned on, the A/D clocks are stopped
and the A/D converter is disabled for the duration of STOP mode, including the 4064 cycles
start-up time. If the A/D RC oscillator is in operation it will also be disabled.
Table 8-2 A/D channel assignment
CH3 CH2 CH1 CH0 Channel selected
0 0 0 0 AN0
0 0 0 1 AN1
0 0 1 0 AN2
0 0 1 1 AN3
0 1 0 0 AN4
0 1 0 1 AN5
0 1 1 0 AN6
0 1 1 1 AN7
1 0 0 0 VRH pin (high)
1 0 0 1 (VRH + VRL) / 2
1 0 1 0 VRL pin (low)
1 0 1 1 VRL pin (low)
1 1 0 0 VRL pin (low)
1 1 0 1 VRL pin (low)
1 1 1 0 VRL pin (low)
1 1 1 1 VRL pin (low)
MOTOROLA
8-6
MC68HC05B6ANALOG TO DIGITAL CONVERTER
8
8.4 A/D converter during WAIT mode
The A/D converter is not affected by WAIT mode and continues normal operation.
In order to reduce power consumption the A/D converter can be disconnected, under software
control using the ADON bit and the ADRC bit in the A/D status/control register at $0009, before
entering WAIT mode.
8.5 Port D analog input
The external analog voltage value to be processed by the A/D con verter is sampled on an internal
capacitor through a resistive path, provided by input-selection switches and a sampling aperture
time switch, as shown in Figure 8-2. Sampling time is limited to 12 bus clock cycles. After
sampling, the analog value is stored on the capacitor and held until the end of conversion. During
this hold time, the analog input is disconnected from the internal A/D system and the external
voltage source sees a high impedance input.
The equivalent analog input during sampling is an RC low-pass filter with a minimum resistance
of 50 k and a capacitance of at least 10pF. It should be noted that these are typical values
measured at room temperature.
Figure 8-2 Electrical model of an A/D input pin
Analog
input
pin
Input protection device
V
RL
< 2pF
+ ~20V
- ~0.7V
400 nA
junction
leakage
50k
10pF
DAC
capacitance
Note:
The analog switch is closed during the 12 cycle sample time only.
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