Datasheet MC68341FT25, MC68341FT16, MC68341FT16V Datasheet (Motorola)

Parts Not Suitable for New Designs

For Additional Information

End-Of-Life Product Change Notice

MC68341

Integrated Processor

User’s Manual

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not
convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola
product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims,
costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are
registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

µ

© MOTOROLA, 1993

PREFACE

The complete documentation package for the MC68341 consists of the MC68341UM/AD,

MC68341 Integrated Processor User’s Manual
Programmer’s Reference Manual,
Product Brief

.

and the MC68341P/D,

, M68000PM/AD,

MC68341 Integrated Processor

MC68000 Family

The
capabilities, registers, and operation of the MC68341; the

Reference Manual
Integrated Processor Product Brief

capabilities.
This user’s manual is organized as follows:

MC68341 Integrated Processor User’s Manual

provides instruction details for the MC68341; and the

provides a brief description of the MC68341

Section 1 Device Overview Section 9 Queued Serial Peripheral
Section 2 Signal Descriptions Module
Section 3 Bus Operation Section 10 IEEE 1149.1 Test Access
Section 4 System Integration Module Port
Section 5 CPU32 Section 11 Applications
Section 6 DMA Controller Module Section 12 Electrical Characteristics
Section 7 Serial Module Section 13 Ordering Information and
Section 8 Timer Modules Mechanical Data

68K FAX-IT –

Documentation Comments

describes the programming,

MC68000 Family Programmer’s

MC68341

FAX [phone]—Documentation Comments Only

The Motorola High-End Technical Publications Department provides a fax number for you
to submit any questions or comments about this document or how to order other
documents. We welcome your suggestions for improving our documentation. Please do
not fax technical questions.

Please provide the part number and revision number (located in upper right-hand corner
of the cover) and the title of the document. When referring to items in the manual, please
reference by the page number, paragraph number, figure number, table number, and line
number if needed.

When sending a fax, please provide your name, company, fax number, and phone
number including area code.

Applications and Technical Information

For questions or comments pertaining to technical information, questions, and
applications, please contact one of the following sales offices nearest you.

— Sales Offices —

UNITED STATES

ALABAMA, Huntsville [phone]
ARIZONA, Tempe [phone]
CALIFORNIA, Agoura Hills [phone]
CALIFORNIA, Los Angeles [phone]
CALIFORNIA, Irvine [phone]
CALIFORNIA, Rosevllle [phone]
CALIFORNIA, San Diego [phone]
CALIFORNIA, Sunnyvale [phone]
COLORADO, Colorado Springs [phone]
COLORADO, Denver [phone]
CONNECTICUT, Wallingford [phone]
FLORIDA, Maitland [phone]
FLORIDA, Pompano Beach/Fort.

Lauderdale [phone]

FLORIDA, Clearwater [phone]
GEORGlA, Atlanta [phone]
IDAHO, Boise [phone]
ILLINOIS, Chicago/Hoffman Estates [phone]
INDlANA, Fort Wayne [phone]
INDIANA, Indianapolis [phone]
INDIANA, Kokomo [phone]
IOWA, Cedar Rapids [phone]
KANSAS, Kansas City/Mission [phone]
MARYLAND, Columbia [phone]
MASSACHUSETTS, Marborough [phone]
MASSACHUSETTS, Woburn [phone]
MICHIGAN, Detroit [phone]
MINNESOTA, Minnetonka [phone]
MISSOURI, St. Louis [phone]
NEW JERSEY, Fairfield [phone]
NEW YORK, Fairport [phone]
NEW YORK, Hauppauge [phone]
NEW YORK, Poughkeepsie/Fishkill [phone]
NORTH CAROLINA, Raleigh [phone]
OHIO, Cleveland [phone]
OHIO, Columbus Worthington [phone]
OHIO, Dayton [phone]
OKLAHOMA, Tulsa [phone]
OREGON, Portland [phone]
PENNSYLVANIA, Colmar [phone]

Philadelphia/Horsham [phone]

TENNESSEE, Knoxville [phone]
TEXAS, Austin [phone]
TEXAS, Houston [phone]
TEXAS, Plano [phone]
VIRGINIA, Richmond [phone]
WASHINGTON, Bellevue [phone]

Seattle Access [phone]
WISCONSIN, Milwaukee/Brookfield [phone]

Field Applications Engineering Available

Through All Sales Offices

CANADA

BRITISH COLUMBIA, Vancouver [phone]
ONTARIO, Toronto [phone]
ONTARIO, Ottawa [phone]
QUEBEC, Montreal [phone]

INTERNATIONAL

AUSTRALIA, Melbourne (61-3)887-0711
AUSTRALIA, Sydney (61(2)906-3855
BRAZIL, Sao Paulo 55(11)815-4200
CHINA, Beijing 86 505-2180

FINLAND, Helsinki 358-0-35161191

Car Phone [phone]

FRANCE, Paris/Vanves 33(1)40 955 900
GERMANY, Langenhagen/ Hanover 49(511)789911
GERMANY, Munich 49 89 92103-0
GERMANY, Nuremberg 49 911 64-3044
GERMANY, Sindelfingen 49 7031 69 910
GERMANY,Wiesbaden 49 611 761921
HONG KONG, Kwai Fong 852-4808333

Tai Po 852-6668333

INDIA, Bangalore (91-812)627094
ISRAEL, Tel Aviv 972(3)753-8222
ITALY, Milan 39(2)82201
JAPAN, Aizu 81(241)272231
JAPAN, Atsugi 81(0462)23-0761
JAPAN, Kumagaya 81(0485)26-2600
JAPAN, Kyushu 81(092)771-4212
JAPAN, Mito 81(0292)26-2340
JAPAN, Nagoya 81(052)232-1621
JAPAN, Osaka 81(06)305-1801
JAPAN, Sendai 81(22)268-4333
JAPAN, Tachikawa 81(0425)23-6700
JAPAN, Tokyo 81(03)3440-3311
JAPAN, Yokohama 81(045)472-2751
KOREA, Pusan 82(51)4635-035
KOREA, Seoul 82(2)554-5188
MALAYSIA, Penang 60(4)374514
MEXICO, Mexico City 52(5)282-2864
MEXICO, Guadalajara 52(36)21-8977

Marketing 52(36)21-9023
Customer Service 52(36)669-9160

NETHERLANDS, Best (31)49988 612 11
PUERTO RICO, San Juan [phone]
SINGAPORE (65)2945438
SPAIN, Madrid 34(1)457-8204

or 34(1)457-8254

SWEDEN, Solna 46(8)734-8800
SWITZERLAND, Geneva 41(22)7991111
SWITZERLAND, Zurich 41(1)730 4074
TAlWAN, Taipei 886(2)717-7089
THAILAND, Bangkok (66-2)254-4910
UNITED KINGDOM, Aylesbury 44(296)395-252

FULL LINE REPRESENTATIVES

COLORADO, Grand Junction

Cheryl Lee Whitely [phone]
KANSAS, Wichita
Melinda Shores/Kelly Greiving [phone]
NEVADA, Reno
Galena Technology Group [phone]
NEW MEXICO, Albuquerque
S&S Technologies, lnc. [phone]
UTAH, Salt Lake City
Utah Component Sales, Inc. [phone]
WASHINGTON, Spokane
Doug Kenley [phone]
ARGENTINA, Buenos Aires
Argonics, S.A. [phone]

HYBRID COMPONENTS RESELLERS

Elmo Semiconductor [phone]
Minco Technology Labs Inc. [phone]
Semi Dice Inc. [phone]

10/31/95 SECTION 1: OVERVIEW UM Rev 1

TABLE OF CONTENTS

Paragraph Page

Number Title Number

Section 1

Device Overview

1.1 Features .............................................................................................. 1-2

Section 2

Signal Descriptions

2.1 Signal Index ........................................................................................ 2-3

2.2 Bus Signals ......................................................................................... 2-5

2.2.1 Address Bus .................................................................................... 2-6

2.2.1.1 Address Bus (A23–A0) ................................................................ 2-6

2.2.1.2 Address Bus (A31–A24) .............................................................. 2-6

2.2.2 Address Strobe (AS)........................................................................ 2-6

2.2.3 M68000 Address Strobe (68KAS) .................................................... 2-6

2.2.4 Data Bus (D15–D0) ......................................................................... 2-6

2.2.5 Data Strobe (DS)............................................................................. 2-7

2.2.6 Upper And Lower Data Strobes (UDS , LDS) ................................... 2-7

2.2.7 Byte Write Enable (UWE , LWE) ....................................................... 2-7

2.2.8 Read/Write (R/W) ............................................................................ 2-7

2.2.9 Transfer Size (SIZ1, SIZ0)............................................................... 2-8

2.2.10 Function Codes (FC3–FC0)............................................................. 2-8

2.2.11 Chip Selects (CS7 –CS1 , CS0 /AVEC).............................................. 2-8

2.2.12 Interrupt Request Level (IRQ7 – IRQ1) ........................................... 2-9

2.3 Bus Control Signals............................................................................. 2-9

2.3.1 Data and Size Acknowledge (DSACK1 , DSACK0) .......................... 2-9

2.4 Bus Arbitration Signals........................................................................ 2-9

2.4.1 Bus Request (BR) ............................................................................ 2-9

2.4.2 Bus Grant (BG )................................................................................ 2-10

2.4.3 Bus Grant Acknowledge (BGACK) .................................................. 2-10

2.4.4 Read-Modify-Write Cycle (RMC/RTCOUT) ..................................... 2-10

2.5 Exception Control Signals ................................................................... 2-10

2.5.1 Reset (RESET) ................................................................................ 2-10

2.5.2 Halt (HALT)...................................................................................... 2-10

2.5.3 Bus Error (BERR )............................................................................ 2-10

2.6 Clock Signals ...................................................................................... 2-11

2.6.1 System Clock (CLKOUT)................................................................. 2-11

2.6.2 Crystal Oscillator (EXTAL, XTAL).................................................... 2-11

MOTOROLA MC68341 USER'S MANUAL iii

10/31/95 SECTION 1: OVERVIEW UM Rev.1.0

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

2.6.3 External Clock (EXTCLK)................................................................ 2-11

2.6.4 External Filter Capacitor (XFC) ....................................................... 2-11

2.6.5 Clock Mode Select (MODCK, Port B0)............................................ 2-11

2.7 Instrumentation and Emulation Signals............................................... 2-11

2.7.1 Instruction Fetch (IFETCH ).............................................................. 2-11

2.7.2 Instruction Pipe (IPIPE) ................................................................... 2-12

2.7.3 Breakpoint (BKPT ) .......................................................................... 2-12

2.7.4 Freeze (FREEZE)............................................................................ 2-12

2.8 DMA Module Signals .......................................................................... 2-12

2.8.1 DMA Request (DREQ2 , DREQ1 ).................................................... 2-12

2.8.2 DMA Acknowledge (DACK2, DACK1/DDACK2 , DDACK1 ) ............. 2-13

2.8.3 DMA Done (DONE2 , DONE1 )......................................................... 2-13

2.8.4 Data Transfer Complete (DTC ) ....................................................... 2-13

2.8.5 DMA Ready (RDY2, RDY1) ............................................................ 2-13

2.9 Serial Module Signals ......................................................................... 2-13

2.9.1 Serial Crystal Oscillator (X2, X1) ..................................................... 2-13

2.9.2 Serial External Clock Input (SCLK) ................................................. 2-13

2.9.3 Receive Data (RxDA, RxDB)........................................................... 2-14

2.9.4 Transmit Data (TxDA, TxDB)........................................................... 2-14

2.9.5 Clear to Send (CTSA, CTSB) .......................................................... 2-14

2.9.6 Request to Send (RTSA, RTSB) ..................................................... 2-14

2.9.7 Transmitter Ready (T≈RDYA ).......................................................... 2-14

2.9.8 Receiver Ready (R≈RDYA) ............................................................. 2-14

2.10 Queued Serial Module Signals ........................................................... 2-15

2.10.1 Master In Slave Out (MISO)............................................................ 2-15

2.10.2 Master Out Slave In (MOSI)............................................................ 2-15

2.10.3 QSPI Serial Clock (QSCLK)............................................................ 2-15

2.10.4 QSPI Peripheral Chip Select (PCS1, PCS0)................................... 2-15

2.11 Timer Signals ...................................................................................... 2-15

2.11.1 Timer Gate (TGATE2 ) ..................................................................... 2-15

2.11.2 Timer Input (TIN) ............................................................................. 2-16

2.11.3 Timer Output (TOUT) ...................................................................... 2-16

2.12 Test Signals ........................................................................................ 2-16

2.12.1 Test Clock (TCK) ............................................................................. 2-16

2.12.2 Test Mode Select (TMS) ................................................................. 2-16

2.12.3 Test Data In (TDI)............................................................................ 2-16

2.12.4 Test Data Out (TDO) ....................................................................... 2-16

2.13 Real Time Clock Mode Signals........................................................... 2-16

2.13.1 Battery Switch (BSW )...................................................................... 2-16

2.13.2 Battery Voltage (V

2.13.3 Real Time Clock Output (RMC/RTCOUT) ....................................... 2-17

2.14 System Power and Ground (VCC AND GND) .................................... 2-17

BATT

)................................................................. 2-16

iv MC68341 USER’S MANUAL MOTOROLA

10/31/95 SECTION 1: OVERVIEW UM Rev 1

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

Section 3

Bus Operation

3.1 68000 Bus Mode ..................................................................................... 3-1

3.2 Bus Transfer Signals............................................................................... 3-2

3.2.1 Bus Control Signals ............................................................................. 3-3

3.2.2 Function Code Signals ............................................................................ 3-4

3.2.3 Address Bus (A31–A0)............................................................................ 3-5

3.2.4 Address Strobe (AS) ............................................................................... 3-5

3.2.5 68000 Address Strobe (AS68K) .............................................................. 3-5

3.2.6 Data Bus (D15–D0)................................................................................. 3-5

3.2.7 Data Strobe (DS)..................................................................................... 3-5

3.2.8 Upper and Lower Data Strobes (UDS and LDS )..................................... 3-6

3.2.9 Upper and Lower Write Enables (UWE and LWE) .................................. 3-6

3.2.10 Data Transfer Complete (DTC)............................................................... 3-6

3.2.11 Bus Cycle Termination Signals ............................................................... 3-6

3.2.11.1 Data Transfer and Size Acknowledge Signals

(DSACK1 and DSACK0). ................................................................. 3-6

3.1.11.2 Bus Error (BERR) ............................................................................. 3-7

3.2.11.3 Autovector (AVEC)........................................................................... 3-7

3.3 Data Transfer Mechanism....................................................................... 3-7

3.3.1 Dynamic Bus Sizing ................................................................................ 3-7

3.3.2 Misaligned Operands .............................................................................. 3-9

3.3.3 Operand Transfer Cases......................................................................... 3-10

3.3.3.1 Byte Operand to 8-Bit Port, Odd or Even (A0 = X) .......................... 3-10

3.3.3.2 Byte Operand to 16-Bit Port, Even (A0 = 0)..................................... 3-10

3.3.3.3 Byte Operand to 16-Bit Port, Odd (A0 = 1) ...................................... 3-11

3.3.3.4 Word Operand to 8-Bit Port, Aligned ............................................... 3-11

3.3.3.5 Word Operand to 16-Bit Port, Aligned ............................................. 3-12

3.3.3.6 Long-word Operand to 8-Bit Port, Aligned. ...................................... 3-12

3.3.3.7 Long-Word Operand to 16-Bit Port, Aligned .................................... 3-14

3.3.4 Bus Operation...................................................................................... 3-16

3.3.5 Synchronous Operation with DSACK≈ ................................................ 3-16

3.3.6 Fast Termination Cycles...................................................................... 3-17

3.4 Data Transfer Cycles........................................................................... 3-18

3.4.1 M68300 Read Cycle................................................................................ 3-18

3.4.2 68000 Read Cycle................................................................................... 3-21

3.4.3 M68300 Write Cycle................................................................................ 3-23

3.4.4 68000 Write Cycle................................................................................... 3-26

3.4.5 Read-Modify-Write Cycle ........................................................................ 3-29

3.5 CPU Space Cycles.................................................................................. 3-31

3.5.1 Breakpoint Acknowledge Cycle............................................................... 3-31

MOTOROLA MC68341 USER'S MANUAL v

10/31/95 SECTION 1: OVERVIEW UM Rev.1.0

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

3.5.2 LPSTOP Broadcast Cycle....................................................................... 3-32

3.5.3 Module Base Address Register Access.................................................. 3-36

3.5.4 Interrupt Acknowledge Bus Cycles ......................................................... 3-36

3.5.4.1 Interrupt Acknowledge Cycle—Terminated Normally.......................... 3-36

3.5.4.2 Autovector Interrupt Acknowledge Cycle............................................. 3-38

3.5.4.3 Spurious Interrupt Cycle...................................................................... 3-39

3.6 Bus Exception Control Cycles................................................................. 3-41

3.6.1 Bus Errors ............................................................................................... 3-43

3.6.2 Retry Operation....................................................................................... 3-45

3.6.3 Halt Operation......................................................................................... 3-47

3.6.4 Double Bus Fault .................................................................................... 3-48

3.7 Bus Arbitration ........................................................................................ 3-49

3.7.1 Bus Request ........................................................................................... 3-52

3.7.2 Bus Grant................................................................................................ 3-52

3.7.3 Bus Grant Acknowledge ......................................................................... 3-52

3.7.4 Bus Arbitration Control............................................................................ 3-53

3.7.5 Show Cycles ........................................................................................... 3-53

3.8 Reset Operation...................................................................................... 3-55

Section 4

System Integration Module

4.1 Module Overview .................................................................................... 4-1

4.2 Module Operation.................................................................................... 4-2

4.2.1 Module Base Address Register Operation .......................................... 4-2

4.2.2 System Configuration and Protection Operation ................................. 4-3

4.2.2.1 System Configuration ...................................................................... 4-5

4.2.2.2 Internal Bus Monitor......................................................................... 4-6

4.2.2.3 Double Bus Fault Monitor ................................................................ 4-6

4.2.2.4 Spurious Interrupt Monitor ............................................................... 4-6

4.2.2.5 Software Watchdog ......................................................................... 4-6

4.2.2.6 Periodic Interrupt Timer ................................................................... 4-7

4.2.2.6.1 Periodic Timer Period Calculation................................................ 4-8

4.2.2.6.2 Using the Periodic Timer as a Real-Time Clock........................... 4-9

4.2.2.7 Simultaneous Interrupts by Sources in the SIM41........................... 4-9

4.2.3 Clock Synthesizer Operation............................................................... 4-9

4.2.3.1 Phase Comparator and Filter........................................................... 4-12

4.2.3.2 Frequency Divider............................................................................ 4-12

4.2.3.3 Clock Control ................................................................................... 4-15

4.2.4 Chip Select Operation ......................................................................... 4-15

4.2.4.1 Programmable Features .................................................................. 4-15

4.2.4.2 Global Chip Select Operation .......................................................... 4-16

vi MC68341 USER’S MANUAL MOTOROLA

10/31/95 SECTION 1: OVERVIEW UM Rev 1

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

4.2.5 External Bus Interface Operation ........................................................ 4-17

4.2.5.1 Port A. .............................................................................................. 4-17

4.2.5.2 Port B ............................................................................................... 4-17

4.2.6 Low-Power Stop .................................................................................. 4-18

4.2.7 Freeze.................................................................................................. 4-19

4.3 Programming Model ................................................................................ 4-19

4.3.1 Module Base Address Register (MBAR) ............................................. 4-22

4.3.2 System Configuration and Protection Registers.................................. 4-23

4.3.2.1 Module Configuration Register (MCR)............................................. 4-23

4.3.2.2 Autovector Register (AVR)............................................................... 4-25

4.3.2.3 Reset Status Register (RSR) ........................................................... 4-25

4.3.2.4 Software Interrupt Vector Register (SWIV) ...................................... 4-26

4.3.2.5 System Protection Control Register (SYPCR)................................. 4-26

4.3.2.6 Periodic Interrupt Control Register (PICR)....................................... 4-28

4.3.2.7 Periodic Interrupt Timer Register (PITR) ......................................... 4-28

4.3.2.8 Software Service Register (SWSR) ................................................. 4-29

4.3.3 Clock Synthesizer Control Register (SYNCR)..................................... 4-29

4.3.4 Chip Select Registers .......................................................................... 4-31

4.3.4.1 Base Select Registers ......................................................................... 4-31

4.3.4.2 Address Mask Registers.................................................................. 4-33

4.3.4.3 Bus Select Register.......................................................................... 4-35

4.3.4.4 Map Select Register......................................................................... 4-35

4.3.4.5 Chip Select Registers Programming Example................................. 4-35

4.3.5 External Bus Interface Control............................................................. 4-36

4.3.5.1 Port A Pin Assignment Register 1 (PPARA1) .................................. 4-36

4.3.5.2 Port A Pin Assignment Register 2 (PPARA2) .................................. 4-36

4.3.5.3 Port A Data Direction Register (DDRA). .......................................... 4-37

4.3.5.4 Port A Data Register (PORTA) ........................................................ 4-37

4.3.5.5 Port B Pin Assignment Register (PPARB)....................................... 4-37

4.3.5.6 Port B Data Direction Register (DDRB) ........................................... 4-38

4.3.5.7 Port B Data Register (PORTB, PORTB1)........................................ 4-38

4.3.5.8 Port C Pin Assignment Register (PPARC)....................................... 4-38

4.4 Real Time Clock ...................................................................................... 4-39

4.4.1 Reset ................................................................................................... 4-39

4.4.2 RTC Interrupt Control Register (RICR)................................................ 4-39

4.4.3 RTC Control/Status Register (RCR).................................................... 4-40

4.4.3 RTC Calibration Control Register (RCCR) .......................................... 4-41

4.4.4 RTC Time of Day Registers................................................................. 4-43

4.4.5 RTC Alarm Registers........................................................................... 4-45

4.4.6 RTC Power Up Operation.................................................................... 4-46

4.4.7 RTC Power Down Operation............................................................... 4-46

MOTOROLA MC68341 USER'S MANUAL vii

10/31/95 SECTION 1: OVERVIEW UM Rev.1.0

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

4.5 MC68340 Initialization Sequence............................................................ 4-46

4.5.1 Startup................................................................................................. 4-47

4.5.2 SIM41 Module Configuration............................................................... 4-47

4.5.3 SIM41 Example Configuration Code ................................................... 4-48

SECTION 5

CPU32

5.1 Overview ............................................................................................. 5-1

5.1.1 Features .......................................................................................... 5-2

5.1.2 Virtual Memory ................................................................................ 5-2

5.1.3 Loop Mode Instruction Execution .................................................... 5-3

5.1.4 Vector Base Register....................................................................... 5-4

5.1.5 Exception Handling.......................................................................... 5-4

5.1.6 Addressing Modes........................................................................... 5-5

5.2 Architecture Summary ........................................................................ 5-5

5.2.1 Programming Model ........................................................................ 5-6

5.2.2 Registers ......................................................................................... 5-7

5.3 Instruction Set ..................................................................................... 5-8

5.3.1 M68000 Family Compatibility .......................................................... 5-10

5.3.1.1 New Instructions .......................................................................... 5-10

5.3.1.1.1 Low-Power Stop (LPSTOP) ..................................................... 5-10

5.3.1.1.2 Table Lookup and Interpolate (TBL)......................................... 5-10

5.3.1.2 Unimplemented Instructions ........................................................ 5-10

5.3.2 Instruction Format and Notation...................................................... 5-10

5.3.3 Instruction Summary ....................................................................... 5-13

5.3.3.1 Condition Code Register.............................................................. 5-18

5.3.3.2 Data Movement Instructions ........................................................ 5-19

5.3.3.3 Integer Arithmetic Operations...................................................... 5-20

5.3.3.4 Logic Instructions......................................................................... 5-22

5.3.3.5 Shift and Rotate Instructions........................................................ 5-22

5.3.3.6 Bit Manipulation Instructions........................................................ 5-23

5.3.3.7 Binary-Coded Decimal (BCD) Instructions................................... 5-24

5.3.3.8 Program Control Instructions ....................................................... 5-24

5.3.3.9 System Control Instructions......................................................... 5-25

5.3.3.10 Condition Tests............................................................................ 5-27

5.3.4 Using the TBL Instructions .............................................................. 5-27

5.3.4.1 Table Example 1 Standard Usage ........................................... 5-28

5.3.4.2 Table Example 2 Compressed Table....................................... 5-29

5.3.4.3 Table Example 3 8-Bit Independent Variable........................... 5-30

5.3.4.4 Table Example 4 Maintaining Precision ................................... 5-32

5.3.4.5 Table Example 5 Surface Interpolations .................................. 5-34

5.3.5 Nested Subroutine Calls.................................................................. 5-34

viii MC68341 USER’S MANUAL MOTOROLA

10/31/95 SECTION 1: OVERVIEW UM Rev 1

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

5.3.6 Pipeline Synchronization with the NOP Instruction ......................... 5-34

5.4 Processing States ............................................................................... 5-34

5.4.1 State Transitions.............................................................................. 5-35

5.4.2 Privilege Levels ............................................................................... 5-35

5.4.2.1 Supervisor Privilege Level ........................................................... 5-35

5.4.2.2 User Privilege Level ..................................................................... 5-36

5.4.2.3 Changing Privilege Level ............................................................. 5-36

5.5 Exception Processing.......................................................................... 5-36

5.5.1 Exception Vectors............................................................................ 5-37

5.5.1.1 Types of Exceptions..................................................................... 5-38

5.5.1.2 Exception Processing Sequence ................................................. 5-38

5.5.1.3 Exception Stack Frame................................................................ 5-39

5.5.1.4 Multiple Exceptions ...................................................................... 5-39

5.5.2 Processing of Specific Exceptions................................................... 5-41

5.5.2.1 Reset............................................................................................ 5-41

5.5.2.2 Bus Error ...................................................................................... 5-43

5.5.2.3 Address Error ............................................................................... 5-43

5.5.2.4 Instruction Traps .......................................................................... 5-44

5.5.2.5 Software Breakpoints................................................................... 5-44

5.5.2.6 Hardware Breakpoints ................................................................. 5-45

5.5.2.7 Format Error ................................................................................. 5-45

5.5.2.8 Illegal or Unimplemented Instructions.......................................... 5-45

5.5.2.9 Privilege Violations....................................................................... 5-46

5.5.2.10 Tracing ......................................................................................... 5-47

5.5.2.11 Interrupts...................................................................................... 5-48

5.5.2.12 Return from Exception ................................................................. 5-49

5.5.3 Fault Recovery ................................................................................ 5-50

5.5.3.1 Types of Faults ............................................................................ 5-52

5.5.3.1.1 Type I—Released Write Faults................................................. 5-52

5.5.3.1.2 Type II—Prefetch, Operand, RMW, and MOVEP Faults.......... 5-53

5.5.3.1.3 Type III—Faults During MOVEM Operand Transfer ................ 5-54

5.5.3.1.4 Type IV—Faults During Exception Processing......................... 5-54

5.5.3.2 Correcting a Fault......................................................................... 5-55

5.5.3.2.1 Type I—Completing Released Writes via Software ................. 5-55

5.5.3.2.2 Type I—Completing Released Writes via RTE......................... 5-55

5.5.3.2.3 Type II—Correcting Faults via RTE.......................................... 5-56

5.5.3.2.4 Type III—Correcting Faults via Software.................................. 5-56

5.5.3.2.5 Type III—Correcting Faults by Conversion and Restart........... 5-56

5.5.3.2.6 Type III—Correcting Faults via RTE......................................... 5-57

5.5.3.2.7 Type IV—Correcting Faults via Software ................................. 5-57

5.5.4 CPU32 Stack Frames...................................................................... 5-58

5.5.4.1 Four-Word Stack Frame .............................................................. 5-58

MOTOROLA MC68341 USER'S MANUAL ix

10/31/95 SECTION 1: OVERVIEW UM Rev.1.0

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

5.5.4.2 Six-Word Stack Frame................................................................. 5-58

5.5.4.3 Bus Error Stack Frame ................................................................ 5-58

5.6 Development Support ......................................................................... 5-61

5.6.1 CPU32 Integrated Development Support........................................ 5-61

5.6.1.1 Background Debug Mode (BDM) Overview................................. 5-62

5.6.1.2 Deterministic Opcode Tracking Overview.................................... 5-62

5.6.1.3 On-Chip Hardware Breakpoint Overview..................................... 5-63

5.6.2 Background Debug Mode................................................................ 5-63

5.6.2.1 Enabling BDM.............................................................................. 5-63

5.6.2.2 BDM Sources............................................................................... 5-64

5.6.2.2.1 External BKPT Signal............................................................... 5-64

5.6.2.2.2 BGND Instruction ..................................................................... 5-64

5.6.2.2.3 Double Bus Fault...................................................................... 5-64

5.6.2.3 Entering BDM .............................................................................. 5-64

5.6.2.4 Command Execution.................................................................... 5-65

5.6.2.5 BDM Registers............................................................................. 5-65

5.6.2.5.1 Fault Address Register (FAR) .................................................. 5-65

5.6.2.5.2 Return Program Counter (RPC) ............................................... 5-65

5.6.2.5.3 Current Instruction Program Counter (PCC). ........................... 5-65

5.6.2.6 Returning from BDM .................................................................... 5-66

5.6.2.7 Serial Interface............................................................................. 5-66

5.6.2.7.1 CPU Serial Logic...................................................................... 5-67

5.6.2.7.2 Development System Serial Logic ........................................... 5-69

5.6.2.8 Command Set .............................................................................. 5-71

5.6.2.8.1 Command Format .................................................................... 5-71

5.6.2.8.2 Command Sequence Diagram................................................. 5-72

5.6.2.8.3 Command Set Summary.......................................................... 5-73

5.6.2.8.4 Read A/D Register (RAREG/RDREG) ..................................... 5-74

5.6.2.8.5 Write A/D Register (WAREG/WDREG).................................... 5-75

5.6.2.8.6 Read System Register (RSREG)............................................. 5-75

5.6.2.8.7 Write System Register (WSREG) ............................................ 5-76

5.6.2.8.8 Read Memory Location (READ)............................................... 5-77

5.6.2.8.9 Write Memory Location (WRITE) ............................................. 5-78

5.6.2.8.10 Dump Memory Block (DUMP).................................................. 5-79

5.6.2.8.11 Fill Memory Block (FILL) .......................................................... 5-80

5.6.2.8.12 Resume Execution (GO) .......................................................... 5-81

5.6.2.8.13 Call User Code (CALL) ............................................................ 5-82

5.6.2.8.14 Reset Peripherals (RST) .......................................................... 5-84

5.6.2.8.15 No Operation (NOP)................................................................. 5-84

5.6.2.8.16 Future Commands.................................................................... 5-85

5.6.3 Deterministic Opcode Tracking ....................................................... 5-85

5.6.3.1 Instruction Fetch (IFETCH).......................................................... 5-85

x MC68341 USER’S MANUAL MOTOROLA

10/31/95 SECTION 1: OVERVIEW UM Rev 1

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

5.6.3.2 Instruction Pipe (IPIPE)................................................................ 5-85

5.6.3.3 Opcode Tracking During Loop Mode ........................................... 5-87

5.7 Instruction Execution Timing ............................................................... 5-87

5.7.1 Resource Scheduling ...................................................................... 5-87

5.7.1.1 Microsequencer............................................................................ 5-87

5.7.1.2 Instruction Pipeline....................................................................... 5-87

5.7.1.3 Bus Controller Resources ............................................................ 5-88

5.7.1.3.1 Prefetch Controller ................................................................... 5-89

5.7.1.3.2 Write-Pending Buffer. ............................................................... 5-89

5.7.1.3.3 Microbus Controller .................................................................. 5-89

5.7.1.4 Instruction Execution Overlap ...................................................... 5-89

5.7.1.5 Effects of Wait States................................................................... 5-90

5.7.1.6 Instruction Execution Time Calculation........................................ 5-91

5.7.1.7 Effects of Negative Tails .............................................................. 5-92

5.7.2 Instruction Stream Timing Examples............................................... 5-92

5.7.2.1 Timing Example 1—Execution Overlap ....................................... 5-93

5.7.2.2 Timing Example 2—Branch Instructions...................................... 5-93

5.7.2.3 Timing Example 3—Negative Tails.............................................. 5-94

5.7.3 Instruction Timing Tables ................................................................ 5-95

5.7.3.1 Fetch Effective Address ............................................................... 5-97

5.7.3.2 Calculate Effective Address ......................................................... 5-98

5.7.3.3 MOVE Instruction......................................................................... 5-99

5.7.3.5 Arithmetic/Logic Instructions........................................................ 5-101

5.7.3.6 Immediate Arithmetic/Logic Instructions ...................................... 5-102

5.7.3.7 Binary-Coded Decimal and Extended Instructions ...................... 5-103

5.7.3.8 Single Operand Instructions......................................................... 5-103

5.7.3.9 Shift/Rotate Instructions............................................................... 5-104

5.7.3.10 Bit Manipulation Instructions........................................................ 5-105

5.7.3.11 Conditional Branch Instructions ................................................... 5-105

5.7.3.12 Control Instructions ...................................................................... 5-106

5.7.3.13 Exception-Related Instructions and Operations........................... 5-107

5.7.3.14 Save and Restore Operations...................................................... 5-108

MOTOROLA MC68341 USER'S MANUAL xi

10/31/95 SECTION 1: OVERVIEW UM Rev.1.0

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

Section 6

DMA Controller Module

6.1 DMA Module Overview ........................................................................... 6-2

6.2 DMA Module Signal Definitions............................................................... 6-4

6.2.1 DMA Request (DREQ1, DREQ2)........................................................ 6-4

6.2.2 DMA Acknowledge (DACK1,DACK2).................................................. 6-4

6.2.3 Ready (RDY1, RDY2) ......................................................................... 6-4

6.2.4 DMA Done (DONE1, DONE2)............................................................. 6-4

6.2.5 Data Transfer Complete (DTC ) ........................................................... 6-4

6.3 Transfer Request Generation.................................................................. 6-4

6.3.1 Internal Request Generation ............................................................... 6-5

6.3.1.1 Internal Request, Maximum Rate .................................................... 6-6

6.3.1.2 Internal Request, Limited Rate ........................................................ 6-6

6.3.2 External Request Generation .............................................................. 6-6

6.3.2.1 External Burst Mode ........................................................................ 6-6

6.3.2.2 External Cycle Steal Mode............................................................... 6-6

6.3.2.3 External Request With Other Modules............................................. 6-7

6.4 Data Transfer modes .............................................................................. 6-8

6.4.1 Single-Address Mode .......................................................................... 6-8

6.4.1.1 Single-Address Read....................................................................... 6-8

6.4.1.2 Single-Address Write ....................................................................... 6-11

6.4.2 Dual-Address Mode............................................................................. 6-13

6.4.2.1 Dual-Address Read ......................................................................... 6-13

6.4.2.2 Dual-Address Write.......................................................................... 6-16

6.5 Bus Arbitration ........................................................................................ 6-19

6.6 DMA Channel Operation......................................................................... 6-19

6.6.1 Channel Initialization and Startup........................................................ 6-19

6.6.2 Data Transfers..................................................................................... 6-20

6.6.2.1 Internal Request Transfers .............................................................. 6-20

6.6.2.2 External Request Transfers............................................................. 6-20

6.6.3 Channel Termination ........................................................................... 6-21

6.6.3.1 Channel Termination........................................................................ 6-21

6.6.3.2 Interrupt Operation........................................................................... 6-21

6.6.3.3 Fast Termination Option .................................................................. 6-22

6.7 Register Description................................................................................ 6-23

6.7.1 Byte Transfer Counter Register (BTC) ................................................ 6-25

6.7.2 Channel Control Register (CCR) ......................................................... 6-25

6.7.3 Channel Status Register (CSR) .......................................................... 6-29

6.7.4 Destination Address Register (DAR)................................................... 6-30

6.7.5 Function Code Register (FCR) ............................................................ 6-31

6.7.6 Interrupt Register (INTR) ..................................................................... 6-32

xii MC68341 USER’S MANUAL MOTOROLA

10/31/95 SECTION 1: OVERVIEW UM Rev 1

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

6.7.7 Module Configuration Register (MCR) ................................................ 6-33

6.7.8 Source Address Register (SAR).......................................................... 6-35

6.8 Data Packing........................................................................................... 6-36

6.9 DMA Channel Initialization Sequence..................................................... 6-36

6.9.1 DMA Channel Configuration................................................................ 6-37

6.9.1.1 DMA Channel Operation In Single-Address Mode .......................... 6-38

6.9.1.2 DMA Channel Operation In Dual-Address Mode ............................. 6-39

6.9.2 DMA Channel Example Configuration Code ....................................... 6-40

6.10 MC68341 DMA Enhancements............................................................... 6-47

6.10.1 RDY≈ ................................................................................................... 6-47

6.10.2 Delayed DACK≈ ................................................................................... 6-47

6.10.3 DTC ..................................................................................................... 6-47

6.10.4 Timing Examples ................................................................................. 6-48

Section 7

Serial Module

7.1 Module Overview ................................................................................ 7-2

7.1.1 Serial Communication Channels A and B........................................ 7-3

7.1.2 Baud Rate Generator Logic............................................................. 7-3

7.1.3 Internal Channel Control Logic........................................................ 7-3

7.1.4 Interrupt Control Logic ..................................................................... 7-3

7.1.5 Comparison of the Serial Module to the MC68681.......................... 7-4

7.2 Serial Module Signal Definitions.......................................................... 7-4

7.2.1 Crystal Input or External Clock (X1) ................................................ 7-5

7.2.2 Crystal Output (X2).......................................................................... 7-5

7.2.3 External Input (SCLK) ..................................................................... 7-6

7.2.4 Channel A Transmitter Serial Data Output (TxDA) ......................... 7-6

7.2.5 Channel A Receiver Serial Data Input (RxDA) ............................... 7-6

7.2.6 Channel B Transmitter Serial Data Output (TxDB) ......................... 7-6

7.2.7 Channel B Receiver Serial Data Input (RxDB) ............................... 7-6

7.2.8 Channel A Request-To-Send (RTSA ).............................................. 7-6

7.2.9 Channel B Request-To-Send (RTSB ).............................................. 7-7

7.2.10 Channel A Clear-To-Send (CTSA ) ................................................. 7-7

7.2.11 Channel B Clear-To-Send (CTSB ) ................................................. 7-7

7.2.12 Channel A Transmitter Ready (T≈RDYA ) ........................................ 7-7

7.2.13 Channel A Receiver Ready (R≈RDYA) ............................................ 7-7

7.3 Operation ............................................................................................ 7-8

7.3.1 Baud Rate Generator ...................................................................... 7-8

7.3.2 Transmitter and Receiver Operating Modes.................................... 7-8

7.3.2.1 Transmitter................................................................................... 7-10

7.3.2.2 Receiver....................................................................................... 7-11

7.3.2.3 FIFO Stack ................................................................................... 7-13

MOTOROLA MC68341 USER'S MANUAL xiii

10/31/95 SECTION 1: OVERVIEW UM Rev.1.0

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

7.3.3 Looping Modes................................................................................ 7-14

7.3.3.1 Automatic Echo Mode.................................................................. 7-14

7.3.3.2 Local Loopback Mode.................................................................. 7-14

7.3.3.3 Remote Loopback Mode.............................................................. 7-14

7.3.4 Multidrop Mode................................................................................ 7-15

7.3.5 Bus Operation ................................................................................. 7-17

7.3.5.1 Read Cycles ................................................................................ 7-17

7.3.5.2 Write Cycles................................................................................. 7-17

7.3.5.3 Interrupt Acknowledge Cycles ..................................................... 7-17

7.4 Register Description and Programming .............................................. 7-18

7.4.1 Register Description........................................................................ 7-18

7.4.1.1 Auxiliary Control Register (ACR) ................................................. 7-20

7.4.1.2 Clock-Select Register (CSR) ....................................................... 7-20

7.4.1.3 Command Register (CR) ............................................................. 7-22

7.4.1.4 Input Port Change Register (IPCR) ............................................. 7-25

7.4.1.5 Input Port Register (IP) ................................................................ 7-26

7.4.1.6 Interrupt Enable Register (IER) ................................................... 7-27

7.4.1.7 Interrupt Level Register (ILR) ...................................................... 7-28

7.4.1.8 Interrupt Status Register (ISR)..................................................... 7-28

7.4.1.9 Interrupt Vector Register (IVR) .................................................... 7-30

7.4.1.10 Module Configuration Register (MCR)......................................... 7-31

7.4.1.11 Mode Register 1 (MR1) ............................................................... 7-33

7.4.1.12 Mode Register 2 (MR2) ............................................................... 7-35

7.4.1.13 Output Port Data Register (OP)................................................... 7-37

7.4.1.14 Outport Port Control Register (OPCR)......................................... 7-38

7.4.1.15 Receiver Buffer (RB).................................................................... 7-39

7.4.1.16 Status Register (SR).................................................................... 7-39

7.4.1.17 Transmitter Buffer (TB) ................................................................ 7-41

7.4.2 Programming ................................................................................... 7-42

7.4.2.1 Serial Module Initialization. .......................................................... 7-42

7.4.2.2 I/O Driver Example....................................................................... 7-42

7.4.2.3 Interrupt Handling ........................................................................ 7-42

7.5 Serial Module Initialization Sequence ................................................ 7-48

7.5.1 Serial Module Configuration............................................................ 7-48

7.5.2 Serial Module Example Configuration Code ................................... 7-50

xiv MC68341 USER’S MANUAL MOTOROLA

10/31/95 SECTION 1: OVERVIEW UM Rev 1

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

Section 8

Timer Module

8.1 Module Overview ................................................................................. 8-1

8.1.1 Timer and Counter Functions ........................................................... 8-2

8.1.1.1 Prescaler and Counter.................................................................. 8-2

8.1.1.2 Time-Out Detection....................................................................... 8-2

8.1.1.3 Comparator ................................................................................... 8-2

8.1.1.4 Clock Selection Logic.................................................................... 8-3

8.1.2 Internal Control Logic ....................................................................... 8-3

8.1.3 Interrupt Control Logic ...................................................................... 8-4

8.2 Timer Modules Signal Definitions......................................................... 8-4

8.2.1 Timer Input (TIN) .............................................................................. 8-5

8.2.2 Timer Gate (TGATE) ........................................................................ 8-5

8.2.3 Timer Output (TOUT) ....................................................................... 8-5

8.3 Operating Modes.................................................................................. 8-5

8.3.1 Input Capture/Output Compare ........................................................ 8-5

8.3.2 Square-Wave Generator .................................................................. 8-7

8.3.3 Variable Duty-Cycle Square-Wave Generator.................................. 8-8

8.3.4 Variable-Width Single-Shot Pulse Generator ................................... 8-10

8.3.5 Pulse-Width Measurement ............................................................... 8-11

8.3.6 Period Measurement ........................................................................ 8-12

8.3.7 Event Count...................................................................................... 8-13

8.3.8 Timer Bypass.................................................................................... 8-15

8.3.9 Bus Operation................................................................................... 8-16

8.3.9.1 Read Cycles.................................................................................. 8-16

8.3.9.2 Write Cycles.................................................................................. 8-16

8.3.9.3 Interrupt Acknowledge Cycles ...................................................... 8-16

8.4 Register Description............................................................................. 8-16

8.4.1 Module Configuration Register (MCR) ............................................. 8-17

8.4.2 Interrupt Register (IR) ....................................................................... 8-18

8.4.3 Control Register (CR) ....................................................................... 8-19

8.4.4 Status Register (SR)......................................................................... 8-22

8.4.5 Counter Register (CNTR) ................................................................. 8-24

8.4.6 Preload 1 Register (PREL1) ............................................................. 8-24

8.4.7 Preload 2 Register (PREL2) ............................................................. 8-25

8.4.8 Compare Register (COM)................................................................. 8-25

8.5 Timer Module Initialization Sequence .................................................. 8-26

8.5.1 Timer Module Configuration ............................................................. 8-26

8.5.2 Timer Module Example Configuration Code..................................... 8-27

MOTOROLA MC68341 USER'S MANUAL xv

10/31/95 SECTION 1: OVERVIEW UM Rev.1.0

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

Section 9

Queued Serial Peripheral Module

9.1 Block Diagram..................................................................................... 9-1

9.2 Memory Map ....................................................................................... 9-2

9.3 QSPM Pins ......................................................................................... 9-3

9.4 Registers............................................................................................. 9-4

9.4.1 Overall QSPM Configuration Summary........................................... 9-7

9.4.2 QSPM Global Registers .................................................................. 9-8

9.4.2.1 QSPM Configuration Register (QMCR) ....................................... 9-8

9.4.2.2 QSPM Test Register (QTEST)..................................................... 9-10

9.4.2.3 QSPM Interrupt Level Register (QILR) ........................................ 9-10

9.4.2.4 QSPM Interrupt Vector Register (QIVR)...................................... 9-11

9.4.3 QSPM Pin Control Registers........................................................... 9-11

9.4.3.1 QSPM Port Data Register (QPDR).............................................. 9-12

9.4.3.2 QSPM Pin Assignment Register (QPAR) .................................... 9-12

9.4.3.3 QSPM Data Direction Register (QDDR) ...................................... 9-13

9.5 QSPI Submodule ................................................................................ 9-13

9.5.1 Features .......................................................................................... 9-14

9.5.1.1 Programmable Queue ................................................................. 9-14

9.5.1.2 Programmable Peripheral Chip Selects....................................... 9-14

9.5.1.3 Wraparound Transfer Mode......................................................... 9-14

9.5.1.4 Programmable Transfer Length................................................... 9-15

9.5.1.5 Programmable Transfer Delay..................................................... 9-15

9.5.1.6 Programmable Queue Pointer ..................................................... 9-15

9.5.1.7 Continuous Transfer Mode .......................................................... 9-15

9.5.2 Block Diagram ................................................................................. 9-16

9.5.3 QSPI Pins........................................................................................ 9-16

9.5.4 Programmer's Model and Registers................................................ 9-17

9.5.4.1 QSPI Control Register 0 (SPCR0)............................................... 9-18

9.5.4.2 QSPI Control Register 1 (SPCR1)............................................... 9-20

9.5.4.3 QSPI Control Register 2 (SPCR2)............................................... 9-22

9.5.4.4 QSPI Control Register 3 (SPCR3)............................................... 9-24

9.5.4.5 QSPI Status Register (SPSR) ..................................................... 9-25

9.5.4.6 QSPI RAM ................................................................................... 9-26

9.5.4.6.1 Receive Data RAM (REC.RAM)............................................... 9-27

9.5.4.6.2 Transmit Data RAM (TRAN.RAM)............................................ 9-27

9.5.4.6.3 Command RAM (COMD.RAM) ................................................ 9-27

9.5.5 Operating Modes and Flowcharts ................................................... 9-30

9.5.5.1 Master Mode................................................................................ 9-37

9.5.5.1.1 Master Mode Operation ........................................................... 9-37

9.5.5.1.2 Master Wraparound Mode........................................................ 9-38

xvi MC68341 USER’S MANUAL MOTOROLA

10/31/95 SECTION 1: OVERVIEW UM Rev 1

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

9.5.5.2 Slave Mode .................................................................................. 9-39

9.5.5.2.1 Description of Slave Operation................................................. 9-39

9.5.5.2.2 Slave Wraparound Mode.......................................................... 9-41

Section 10

IEEE 1149.1 Test Access Port

10.1 Overview ............................................................................................. 10-1

10.2 Tap Controller ..................................................................................... 10-2

10.3 Boundary Scan Register ..................................................................... 10-3

10.4 Instruction Register ............................................................................. 10-10

10.4.1 EXTEST (000) ................................................................................. 10-11

10.4.2 Sample/Preload (001)...................................................................... 10-11

10.4.3 BYPASS (X1X, 101) ........................................................................ 10-11

10.4.4 HI-Z (100) ........................................................................................ 10-12

10.5 MC68341 Restrictions......................................................................... 10-12

10.6 Non-IEEE 1149.1 Operation................................................................ 10-13

Section 11

Applications

11.1 Minimum System Configuration .......................................................... 11-1

11.1.1 Processor Clock Circuitry ................................................................ 11-1

11.1.2 Reset Circuitry ................................................................................. 11-3

11.1.3 SRAM Interface ............................................................................... 11-3

11.1.4 ROM Interface ................................................................................. 11-4

11.1.5 Serial Interface ................................................................................ 11-4

11.2 Memory Interface Information ............................................................. 11-5

11.2.1 Using an 8-Bit Boot ROM ................................................................ 11-5

11.2.2 Access Time Calculations................................................................ 11-6

11.2.3 Calculating Frequency-Adjusted Output.......................................... 11-7

11.2.4 Interfacing an 8-Bit Device to 16-Bit Memory Using

Single-Address DMA Mode.......................................................... 11-10

11.3 Power Consumption Considerations................................................... 11-10

11.4 MC68341V (3.3 V)............................................................................... 11-11

MOTOROLA MC68341 USER'S MANUAL xvii

10/31/95 SECTION 1: OVERVIEW UM Rev.1.0

TABLE OF CONTENTS (Concluded)

Paragraph Page

Number Title Number

Section 12

Electrical Characteristics

12.1 Maximum Ratings ............................................................................... 12-1

12.2 Thermal Characteristics ...................................................................... 12-1

12.3 Power Considerations......................................................................... 12-2

12.4 AC Electrical Specification Definitions ................................................ 12-2

12.5 DC Electrical Specifications ................................................................ 12-5

12.6 AC Electrical Specifications Control Timing........................................ 12-6

12.7 AC Timing Specifications .................................................................... 12-7

12.8 DMA Module AC Electrical Specifications .......................................... 12-22

12.9 Timer Module Electrical Specifications ............................................... 12-24

12.10 Serial Module Electrical Specifications ............................................... 12-26

12.11 QSPM Electrical Specifications........................................................... 12-29

12.12 IEEE 1149.1 Electrical Specifications ................................................. 12-32

xviii MC68341 USER’S MANUAL MOTOROLA

10/31/95 SECTION 1: OVERVIEW UM Rev 1

LIST OF ILLUSTRATIONS

Figure Page

Number Title Number

1-1 MC68341 Simplified Block Diagram............................................................. 1-1

2-1 Functional Signal Groups............................................................................. 2-2

3-1 Input Sample Window .................................................................................. 3-3

3-2 MC68341 Interface to Various Port Sizes .................................................... 3-9

3-3 Long-Word Operand Read Timing from 8-Bit Port....................................... 3-13

3-4 Long-Word Operand Write Timing to 8-Bit Port ........................................... 3-14

3-5 Long-Word and Word Read and Write Timing—16-Bit Port......................... 3-15

3-6 Fast Termination Timing............................................................................... 3-17

3-7 Word Read Cycle Flowchart......................................................................... 3-19

3-8 Read Cycle Timing....................................................................................... 3-20

3-9 68000 Word Read Cycle Flowchart ............................................................. 3-21

3-10 68000 Read Cycle Timing............................................................................ 3-23

3-11 Word Write Cycle Flowchart......................................................................... 3-24

3-12 M68300 Write Cycle Timing ......................................................................... 3-25

3-13 68000 Word Write Cycle Flowchart.............................................................. 3-26

3-14 68000 Write Cycle Timing ............................................................................ 3-28

3-15 Read-Modify-Write Cycle Timing ................................................................. 3-29

3-16 CPU Space Address Encoding .................................................................... 3-31

3-17 Breakpoint Operation Flowchart................................................................... 3-33

3-18 Breakpoint Acknowledge Cycle Timing (Opcode Returned) ........................ 3-34

3-19 Breakpoint Acknowledge Cycle Timing (Exception Signaled)...................... 3-35

3-20 Interrupt Acknowledge Cycle Flowchart....................................................... 3-37

3-21 Interrupt Acknowledge Cycle Timing............................................................ 3-38

3-22 Autovector Operation Timing ....................................................................... 3-40

3-23 Bus Error without DSACK≈ ........................................................................... 3-44

3-24 Late Bus Error with DSACK≈ ........................................................................ 3-45

3-25 Retry Sequence ........................................................................................... 3-46

3-26 Late Retry Sequence ................................................................................... 3-47

3-27 HALT Timing................................................................................................. 3-48

3-28 Bus Arbitration Flowchart for Single Request .............................................. 3-50

3-29 Bus Arbitration Timing Diagram—Idle Bus Case ......................................... 3-51

3-30 Bus Arbitration Timing Diagram—Active Bus Case ..................................... 3-51

3-31 Bus Arbitration State Diagram...................................................................... 3-54

3-32 Show Cycle Timing Diagram........................................................................ 3-55

MOTOROLA MC68341 USER'S MANUAL xix

10/31/95 SECTION 1: OVERVIEW UM Rev.1.0

LIST OF ILLUSTRATIONS (Continued)

Figure Page

Number Title Number

3-33 Timing for External Devices Driving Reset .................................................. 3-56

3-34 Power-Up Reset Timing Diagram ............................................................... 3-57

4-1 SIM41 Module Register Block...................................................................... 4-3

4-2 System Configuration and Protection Function............................................ 4-5

4-3 Software Watchdog Block Diagram ............................................................. 4-7

4-4 Clock Block Diagram for Crystal and EXTCLK Operation ........................... 4-10

4-5 MC68341 Crystal Oscillator ......................................................................... 4-10

4-6 Block Diagram for External Clock Operation ............................................... 4-11

5-1 CPU32 Block Diagram................................................................................. 5-3

5-2 Loop Mode Instruction Sequence ................................................................ 5-3

5-3 User Programming Model ............................................................................ 5-6

5-4 Supervisor Programming Model Supplement .............................................. 5-7

5-5 Status Register ............................................................................................ 5-8

5-6 Instruction Word General Format................................................................. 5-11

5-7 Table Example 1.......................................................................................... 5-28

5-8 Table Example 2.......................................................................................... 5-29

5-9 Table Example 3.......................................................................................... 5-31

5-10 Exception Stack Frame................................................................................ 5-39

5-11 Reset Operation Flowchart .......................................................................... 5-42

5-12 Format $0—Four-Word Stack Frame........................................................... 5-58

5-13 Format $2—Six-Word Stack Frame............................................................. 5-58

5-14 Internal Transfer Count Register.................................................................. 5-59

5-15 Format $C—BERR Stack for Prefetches and Operands ............................. 5-60

5-16 Format $C—BERR Stack on MOVEM Operand.......................................... 5-60

5-17 Format $C—Four- and Six-Word BERR Stack ............................................ 5-61

5-18 In-Circuit Emulator Configuration................................................................. 5-62

5-19 Bus State Analyzer Configuration ................................................................ 5-62

5-20 BDM Block Diagram..................................................................................... 5-63

5-21 BDM Command Execution Flowchart .......................................................... 5-66

5-22 Debug Serial I/O Block Diagram.................................................................. 5-68

5-23 Serial Interface Timing Diagram .................................................................. 5-69

5-24 BKPT Timing for Single Bus Cycle .............................................................. 5-70

5-25 BKPT Timing for Forcing BDM..................................................................... 5-70

5-26 BKPT/DSCLK Logic Diagram....................................................................... 5-70

5-27 Command Sequence Diagram..................................................................... 5-73

5-28 Functional Model of Instruction Pipeline ...................................................... 5-86

5-29 Instruction Pipeline Timing Diagram ............................................................ 5-86

5-30 Block Diagram of Independent Resources .................................................. 5-88

5-31 Simultaneous Instruction Execution............................................................. 5-90

5-32 Attributed Instruction Times ......................................................................... 5-90

xx MC68341 USER’S MANUAL MOTOROLA

10/31/95 SECTION 1: OVERVIEW UM Rev 1

LIST OF ILLUSTRATIONS (Continued)

Figure Page

Number Title Number

5-33 Example 1—Instruction Stream ................................................................... 5-93

5-34 Example 2—Branch Taken .......................................................................... 5-93

5-35 Example 2—Branch Not Taken.................................................................... 5-94

5-36 Example 3—Branch Negative Tail ............................................................... 5-94

6-1 DMA Block Diagram ..................................................................................... 6-1

6-2 Single-Address Transfers............................................................................. 6-3

6-3 Dual-Address Transfer ................................................................................. 6-3

6-4 DMA External Connections to Serial Module............................................... 6-7

6-5 Single-Address Read Timing (External Burst).............................................. 6-9

6-6 Single-Address Read Timing (Cycle Steal).................................................. 6-10

6-7 Single-Address Write Timing (External Burst).............................................. 6-11

6-8 Single-Address Write Timing (Cycle Steal) .................................................. 6-12

6-9 Dual-Address Read Timing (External Burst-Source Requesting) ................ 6-14

6-10 Dual-Address Read Timing (Cycle Steal-Source Requesting)..................... 6-15

6-11 Dual-Address Write Timing (External Burst-Destination Requesting).......... 6-17

6-12 Dual-Address Write Timing (Cycle Steal-Destination Requesting) .............. 6-18

6-13 Fast Termination Option Timing (Cycle Steal) ............................................. 6-22

6-14 Fast Termination Option Timing (External Burst–Source Requesting) ........ 6-23

6-15 DMA Module Programming Model ............................................................... 6-24

6-16 Packing and Unpacking of Operands........................................................... 6-36

6-17 M68300 Single Address Read with RDY≈ .................................................... 6-49

6-18 M68300 Single Address Write with RDY≈ .................................................... 6-50

6-19 M68300 Single Address Read with Delayed DACK≈ and RDY≈ .................. 6-51

6-20 M68300 Single Address Write with Delayed DACK≈ and RDY≈ .................. 6-52

6-21 68000 Single Address Read with RDY≈ ....................................................... 6-53

6-22 68000 Single Address Write with RDY≈ ....................................................... 6-54

6-23 68000 Single Address Read with Delayed DACK≈ and RDY≈ ..................... 6-55

6-24 68000 Single Address Write with Delayed DACK≈ and RDY≈ ..................... 6-56

6-25 68000 Single Address Read with Delayed DACK≈ ...................................... 6-57

7-1 Simplified Block Diagram ............................................................................. 7-1

7-2 External and Internal Interface Signals ........................................................ 7-5

7-3 Baud Rate Generator Block Diagram........................................................... 7-8

7-4 Transmitter and Receiver Functional Diagram............................................. 7-9

7-5 Transmitter Timing Diagram......................................................................... 7-10

7-6 Receiver Timing Diagram............................................................................. 7-12

7-7 Looping Modes Functional Diagram............................................................. 7-15

7-8 Multidrop Mode Timing Diagram .................................................................. 7-16

7-9 Serial Module Programming Model Programming Model ............................ 7-19

7-10 Serial Module Programming Flowchart ....................................................... 7-43

MOTOROLA MC68341 USER'S MANUAL xxi

10/31/95 SECTION 1: OVERVIEW UM Rev.1.0

LIST OF ILLUSTRATIONS (Continued)

Figure Page

Number Title Number

8-1 Simplified Block Diagram ............................................................................. 8-1

8-2 Timer Functional Diagram............................................................................ 8-3

8-3 External and Internal Interface Signals ........................................................ 8-4

8-4 Input Capture/Output Compare Mode.......................................................... 8-6

8-5 Square-Wave Generator Mode.................................................................... 8-8

8-6 Variable Duty-Cycle Square-Wave Generator Mode ................................... 8-9

8-7 Variable-Width Single-Shot Pulse Generator Mode..................................... 8-11

8-8 Pulse-Width Measurement Mode................................................................. 8-12

8-9 Period Measurement Mode.......................................................................... 8-13

8-10 Event Count Mode ....................................................................................... 8-14

8-11 Timer Module Programming Model.............................................................. 8-17

9-1 QSPM Block Diagram .................................................................................. 9-1

9-2 QSPM Memory Map .................................................................................... 9-2

9-3 QSPI Submodule Diagram........................................................................... 9-16

9-4 Organization of the QSPI RAM .................................................................... 9-27

9-5 Command RAM............................................................................................ 9-28

9-6 Flowchart of QSPI Initialization Operation ................................................... 9-31

9-7 Flowchart of QSPI Master Operation ........................................................... 9-32

9-8 Flowchart of QSPI Slave Operation ............................................................. 9-35

10-1 Test Access Port Block Diagram ................................................................. 10-2

10-2 TAP Controller State Machine ..................................................................... 10-3

10-3 Output Latch Cell (O.Latch) ......................................................................... 10-7

10-4 Input Pin Cell (I.Pin) ..................................................................................... 10-8

10-5 Active-High Output Control Cell (IO.Ctl1)..................................................... 10-8

10-6 Active-Low Output Control Cell (IO.Ctl0) ..................................................... 10-9

10-7 Bidirectional Data Cell (IO.Cell) ................................................................... 10-9

10-8 General Arrangement for Bidirectional Pins................................................. 10-10

10-9 Bypass Register........................................................................................... 10-12

11-1 Minimum System Configuration Block Diagram........................................... 11-1

11-2 Sample Crystal Circuit ................................................................................. 11-2

11-3 Statek Corporation Crystal Circuit................................................................ 11-2

11-4 XFC and VCCSYN Capacitor Connections.................................................. 11-3

11-5 SRAM Interface............................................................................................ 11-4

11-6 ROM Interface.............................................................................................. 11-4

11-7 Serial Interface............................................................................................. 11-5

11-8 External Circuitry for 8-Bit Boot ROM .......................................................... 11-5

11-9 8-bit Boot ROM Timing ................................................................................ 11-6

11-10 Access Time Computation Diagram ............................................................ 11-6

11-11 Signal Relationships to CLKOUT................................................................. 11-7

xxii MC68341 USER’S MANUAL MOTOROLA

10/31/95 SECTION 1: OVERVIEW UM Rev 1

LIST OF ILLUSTRATIONS (Concluded)

Figure Page

Number Title Number

11-12 Signal Width Specifications.......................................................................... 11-8

11-13 Skew between Two Outputs......................................................................... 11-9

11-14 Circuitry for Interfacing 8-Bit Device to 16-Bit Memory

in Single-Address DMA Mode................................................................... 11-10

12-1 Drive Levels and Test Points for AC Specifications ..................................... 12-4

12-2 M68300 Read Cycle Timing Diagram .......................................................... 12-10

12-3 M68300 Write Cycle Timing Diagram .......................................................... 12-11

12-4 68000 Three-Clock Read Cycle Timing Diagram Using Internal DSACK1.. 12-12
12-5 68000 Three-Clock Write Cycle Timing Diagram Using Internal DSACK1 .. 12-13

12-6 68000 Four-Clock Read Cycle Timing Diagram........................................... 12-14

12-7 68000 Four-Clock 16-Bit Write Timing Diagram........................................... 12-15

12-8 M68300 Fast Termination Read Cycle Timing Diagram .............................. 12-16

12-9 M68300 Fast Termination Write Cycle Timing Diagram............................... 12-17

12-10 Bus Arbitation Timing—Active Bus Case..................................................... 12-18

12-11 Bus Arbitration Timing—Idle Bus Case........................................................ 12-19

12-12 Show Cycle Timing Diagram........................................................................ 12-19

12-13 IACK Cycle Timing Diagram......................................................................... 12-20

12-14 Background Debug Mode Serial Port Timing............................................... 12-21

12-15 Background Debug Mode FREEZE Timing ................................................. 12-21

12-16 DMA Signal Timing Diagram........................................................................ 12-22

12-17 DMA Enhancements Timing Diagram.......................................................... 12-23

12-18 Timer Module Clock Signal Timing Diagram................................................ 12-24

12-19 Timer Module Signal Timing Diagram .......................................................... 12-25

12-20 Serial Module General Timing Diagram ....................................................... 12-27

12-21 Serial Module Asynchronous Mode Timing (X1).......................................... 12-27

12-22 Serial Module Asynchronous Mode Timing (SCLK–16X) ............................ 12-28

12-23 Serial Module Synchronous Mode Timing Diagram..................................... 12-28

12-24 QSPI Timing Master, CPHA 0...................................................................... 12-30

12-25 QSPI Timing Master, CPHA 1...................................................................... 12-30

12-26 QSPI Timing Slave, CPHA 0........................................................................ 12-31

12-27 QSPI Timing Slave, CPHA 1........................................................................ 12-31

12-28 Test Clock Input Timing Diagram................................................................. 12-32

12-29 Boundary Scan Timing Diagram .................................................................. 12-33

12-30 Test Access Port Timing Diagram................................................................ 12-33

MOTOROLA MC68341 USER'S MANUAL xxiii

10/31/95 SECTION 1: OVERVIEW UM Rev.1.0

LIST OF TABLES

Table Page

Number Title Number

2-1 Bus Signal Summary ................................................................................... 2-3

2-2 CPU32 Serial Port........................................................................................ 2-4

2-3 Serial Module ............................................................................................... 2-4

2-4 Queued Serial Module ................................................................................. 2-4

2-5 DMA Module ................................................................................................ 2-4

2-6 Timer Module ............................................................................................... 2-5

2-7 IEEE 1149.1................................................................................................. 2-5

2-8 Power, Clock, and Control ........................................................................... 2-5

2-9 Data Strobe Control of Data Bus ................................................................. 2-7

2-10 SIZx Signal Encoding................................................................................... 2-8

2-11 Address Space Encoding............................................................................. 2-8

2-12 DSACK≈ Encoding....................................................................................... 2-9

3-1 SIZx Signal Encoding ................................................................................... 3-4

3-2 Address Space Encoding............................................................................. 3-5

3-3 DSACK≈ Encoding....................................................................................... 3-8

3-4 DSACK≈ , BERR , and HALT Assertion Results ............................................ 3-42

4-1 Clock Operating Modes................................................................................ 4-9

4-2 System Frequencies from 32.768-kHz Reference....................................... 4-13

4-3 Clock Control Signals................................................................................... 4-15

4-4 Port B Pin Assignment Register................................................................... 4-17

4-5 Port A Pin Assignment Register................................................................... 4-17

4-6 Port B Pin Assignment Register................................................................... 4-18

4-7 SHENx Control Bits...................................................................................... 4-24

4-8 Deriving Software Watchdog Timeout ......................................................... 4-27

4-9 BMTx Encoding............................................................................................ 4-27

4-10 PIRQL Encoding .......................................................................................... 4-28

4-11 DDx Encoding .............................................................................................. 4-34

4-12 PSx Encoding............................................................................................... 4-34

4-13 RIRQL Encoding.......................................................................................... 4-40

xxiv MC68341 USER’S MANUAL MOTOROLA

10/31/95 SECTION 1: OVERVIEW UM Rev 1

LIST OF TABLES (Continued)

Table Page

Number Title Number

5-1 Instruction Set .............................................................................................. 5-9

5-2 Instruction Set Summary.............................................................................. 5-14

5-3 Condition Code Computations ..................................................................... 5-18

5-4 Data Movement Operations ......................................................................... 5-19

5-5 Integer Arithmetic Operations ...................................................................... 5-21

5-6 Logic Operations .......................................................................................... 5-22

5-7 Shift and Rotate Operations......................................................................... 5-23

5-8 Bit Manipulation Operations ......................................................................... 5-23

5-9 Binary-Coded Decimal Operations............................................................... 5-24

5-10 Program Control Operations ........................................................................ 5-24

5-11 System Control Operations.......................................................................... 5-26

5-12 Condition Tests ............................................................................................ 5-27

5-13 Standard Usage Entries ............................................................................... 5-28

5-14 Compressed Table Entries........................................................................... 5-30

5-15 8-Bit Independent......................................................................................... 5-31

5-16 Exception Vector Assignments .................................................................... 5-37

5-17 Exception Priority Groups ............................................................................ 5-40

5-18 Tracing Control............................................................................................. 5-47

5-19 BDM Source Summary ................................................................................ 5-64

5-20 Polling the BDM Entry Source...................................................................... 5-65

5-21 CPU Generated Message Encoding ............................................................ 5-67

5-22 Size Field Encoding ..................................................................................... 5-71

5-23 BDM Command Summary ........................................................................... 5-74

5-24 Register Field for RSREG and WSREG....................................................... 5-76

6-1 SSIZEx Encoding......................................................................................... 6-27

6-2 DSIZEx Encoding......................................................................................... 6-27

6-3 REQx Encoding............................................................................................ 6-28

6-4 BBx Encoding and Bus Bandwidth............................................................... 6-28

6-5 Address Space Encoding............................................................................. 6-31

6-6 FRZx Control Bits......................................................................................... 6-33

7-1 RCSx Control Bits ........................................................................................ 7-21

7-2 TCSx Control Bits......................................................................................... 7-22

7-3 MISCx Control Bits....................................................................................... 7-23

7-4 TCx Control Bits ........................................................................................... 7-24

7-5 RCx Control Bits........................................................................................... 7-25

7-6 FRZx Control Bits......................................................................................... 7-31

7-7 PMx and PT Control Bits.............................................................................. 7-34

7-8 B/Cx Control Bits.......................................................................................... 7-34

7-9 CMx Control Bits .......................................................................................... 7-35

7-10 SBx Control Bits ........................................................................................... 7-36

MOTOROLA MC68341 USER'S MANUAL xxv

10/31/95 SECTION 1: OVERVIEW UM Rev.1.0

LIST OF TABLES (Continued)

Table Page

Number Title Number

8-1 OCx Encoding.............................................................................................. 8-16

8-2 FRZx Control Bits......................................................................................... 8-18

8-3 IEx Encoding................................................................................................ 8-20

8-4 POT Encoding.............................................................................................. 8-21

8-5 MODEx Encoding......................................................................................... 8-21

8-6 OCx Encoding.............................................................................................. 8-21

9-1 QSPM Pin Summary.................................................................................... 9-4

9-2 QSPM Register Summary............................................................................ 9-5

9-3 Bit/Field Quick Reference Guide.................................................................. 9-6

9-4 QSPM Global Registers............................................................................... 9-8

9-5 QSPM Pin Control Registers ....................................................................... 9-11

9-6 External Pin Inputs/Outputs to the QSPI...................................................... 9-17

9-7 QSPI Registers ............................................................................................ 9-17

9.8 Bits per Transfer if Command Control Bit BITSE = 1 ................................... 9-19

9-9 Examples of SCK Frequencies .................................................................... 9-20

10-1 Boundary Scan Control Bits......................................................................... 10-4

10-2 Boundary Scan Bit Definitions ..................................................................... 10-5

10-3 Instructions................................................................................................... 10-10

11-1 Memory Access Times at 16.78 MHz .......................................................... 11-7

11-2 Typical Electrical Characteristics ................................................................. 11-11

xxvi MC68341 USER’S MANUAL MOTOROLA

SECTION 1
DEVICE OVERVIEW

The MC68341 is a member of the M68300 family of integrated processors designed
specifically for the compact disc-interactive (CD-I) market. It improves on the feature set of
the MC68340 for a more complete and cost effective integrated system solution to CD-I's
specific needs.

The MC68341 contains a 68020-based CPU32, a two channel DMA controller, two serial
channels, a timer, and a queued serial peripheral interface. The 68341's system
integration module (SIM41) contains clock circuitry, system protection, external bus
interface, timers, and additional chip selects. New to the SIM is the real time clock and an
MC68000 bus interface. The MC68000 bus interface is dynamically selectable to give a
glueless interface to peripherals and memory designed for the MC68000 while allowing
higher performance transfers using the standard 68300 bus interface. Complete code
compatibility with the MC68000 affords the designer access to a broad base of
established real-time kernels, operating systems, languages, applications, and
development tools—many oriented towards embedded control.

As a low voltage part, the MC68341V can operate with a 3.3-V power supply and is
particularly useful for battery applications. MC68341 is used throughout this document to
refer to both the low voltage and standard 5-V parts since both are functionally equivalent.
Figure 1-1 illustrates a block diagram of the MC68341.

SYSTEM

INTEGRATION MODULE

(SIM41)

TIMER

CPU32
(68000-BASED
PROCESSOR)

QUEUED SERIAL

INTERMODULE BUS

PERIPHERAL

INTERFACE

TWO-CHANNEL

DMA CONTROLLER

TWO-CHANNEL

SERIAL I/O

SYSTEM

PROTECTION

CLOCK

SYNTHESIZER

EXTERNAL

BUS INTERFACE

BUS ARBITRATION

REAL TIME CLOCK

IEEE 1149.1 TEST

32-BIT ADDRESS BUS

16-BIT DATA BUS

Figure 1-1. MC68341 Simplified Block Diagram

MOTOROLA MC68341 USER’S MANUAL 1-1

MC68341 FEATURES

The primary features of the MC68341 are as follows:

• High Performance CPU32 Core Processor
— Upward Object-Code Compatible with MC68000 and MC68010

— Additional 32-Bit MC68020 Instructions and Addressing Modes
— Fast Two-Clock Register Instructions

• High-Speed Dual DMA Controllers for Low-Latency Transfers
— 50-Mbyte/Sec Sustained Transfer Rate

— Dual or Single Address Transfers
— 8-, 16-, or 32-Bit Transfers

• Counter/Timer
— 16-Bit Timer with 8-Bit Prescaler

— Multi-mode Operation
— 80 nS Resolution

• Dual Serial Communication Ports
— Synchronous or Asynchronous Operation

— 3-Mbit/Sec Sustained Transfer Rate
— Modem Control
— Baud Rate Generation
— 68681/261 Compatible

• Queued Serial Peripheral Interface (QSPI)
— Communications with Slow Peripherals without Tying Up the CPU

— Queued Transmit and Receive Buffers
— Programmable for Master or Slave SPI Operation

• System Integration Module for Flexible and Cost-Effective System Interface
— 32-Bit Address Bus; 16-Bit Data Bus with Dynamic Bus Sizing

— System Protection, Reset, and Configuration Control
— Periodic Interrupt/System Timer
— Chip-Select, Wait State Generation, Bus Watchdog
— Interrupt Controller
— IEEE 1149.1 Boundary Scan (JTAG)
— Dual 8-Bit Parallel Ports
— Real Time Clock
— Time and Date with Leap Year Correction
— Programmable Alarm for Interrupt or External Output
— Calibration Register Eliminates Need for Trim Capacitor
— Battery Backup Capability

• Power Management
— 5 V or 3.3 V Operation

— Fully Static HCMOS Technology
— Programmable Clock Synthesizer for Full Frequency Control
— Power-Down/Low Power Stop Capabilities
— Idle Modules Can Be Individually Powered Down

• 0–16 or 25 MHz Operation

• 160-Pin Plastic Quad Flat Pack (QFP)

1-2 MC68341 USER’S MANUAL MOTOROLA

CENTRAL PROCESSING UNIT

The CPU32 is a powerful central processor that supervises system function, makes
decisions, manipulates data, and directs I/O. A special debugging mode simplifies
processor emulation during system debug.

CPU32

The CPU32 is a 68000-based microprocessor that can execute most 32-bit operations in
two clock periods. Additional instructions enhance lookup table interpolation and power
consumption control. In addition to performing basic instruction execution, the CPU32
provides a sophisticated background debug port for non-invasive instrumentation in the
software development and debug environments.

On-Chip Peripherals

To improve total system throughput and reduce part count, board size, and cost of system
implementation, the M68300 family integrates on-chip, intelligent peripheral modules, and
typical glue logic. These functions on the MC68341 include the SIM41, a DMA controller,
a serial module, a queued serial peripheral interface, and a timer.

The IMB is the backbone of the MC68341, and is similar to traditional external buses with
address, data, clock, interrupt, arbitration, and handshake signals. Because bus masters
(like the CPU32 and DMA), peripherals, and the SIM41 are on the same processor, the
IMB ensures that communication between these modules is fully synchronized and that
arbitration and interrupts can be handled in parallel with data transfers, greatly improving
system performance. Internal accesses across the IMB can be monitored from outside of
the processor.

System Integration Module

The MC68341 system integration module (SIM41) handles a wide array of functions,
eliminating the need for much of the glue logic which typically supports the microprocessor
and its interface with peripherals and external memory. The SIM41 includes:

• External Bus Interface—Transfers information between the CPU32 or DMA controller
and external memory or peripherals by providing up to 32 address lines and 16 data
lines. Both the 68300 bus interface and the original MC68000 bus interface are
provided.

• System Configuration and Protection—Achieves maximum system protection by
providing various monitors and timers to prevent system lockup, recover from
catastrophic failure, exit infinite loops, provide refresh, etc.

• Clock Synthesizer—Generates the clock signals used by all internal operations as
well as a clock output used by external devices.

• Chip Select and Wait State Generation—Offers eight programmable chip selects
which provide signals to enable external memory and peripheral circuits and create all
external handshaking and timing signals. Up to six wait states can be automatically
inserted.

MOTOROLA MC68341 USER’S MANUAL 1-3

• Interrupt Control—Provides up to seven discrete interrupt inputs for external devices.

• IEEE 1149.1 Test Access Port (JTAG)—Aids in system diagnostics by providing
dedicated, user-accessible test logic that is fully compliant with the IEEE 1149.1
standard for boundary scan testability.

• Real Time Clock—The real time clock can be sustained on a separate power supply
for battery backup. This simple counter is driven by 32.768 KHz clock for low power
consumption. The real time clock counts seconds, minutes, hours, days, day of the
week, date of the month, and year with leap year compensation. The real time clock
has internal interrupt generation capability and includes a programmable output pin,
which can provide an interrupt or other output signal based upon an alarm or time
matching function. Software calibration eliminates the need for an external trim
capacitor.

Queued Serial Peripheral Interface (QSPI) Module

The QSPI eases peripheral expansion or interprocessor communications. This function
allows interface to and control of other integrated controllers (such as, MC6805 or
MC68HC11 family devices) and peripherals (such as, LCD drivers, A/D–D/A converters,
digital signal processors, EEPROM). The QSPI can handle up to 16 serial transfers of 8 to
16 bits each or transmit a stream of data up to 256 bits long without CPU intervention,
because of a small RAM in the QSPI. A special wrap-around mode allows the QSPI to
continuously sample a serial peripheral, automatically updating the QSPI RAM for efficient
interfacing to serial analog-to-digital converters.

Timer Module

The timer consists of a 16-bit countdown counter with an 8-bit countdown prescaler for a
composite 24-bit resolution. The finest resolution of the timer is 80 ns with a 25-MHz
system clock (125 ns @ 16.78 MHz). The programmable timer operating modes are input
capture, output compare, square-wave generation, variable duty-cycle square-wave
generation, variable-width single-shot pulse generation, event counting, period
measurement, and pulse-width measurement.

POWER CONSUMPTION MANAGEMENT

The MC68341 is very power efficient due to its advanced 0.8-µ HCMOS process
technology and its static logic design. The resulting power consumption is typically
500 mW in full operation—far less than the comparable discrete component
implementation the MC68341 can replace. For applications employing reduced voltage
operation, selection of the MC68341V, which requires only a 3.3-V power supply, reduces
current consumption by 40–60% in all modes of operation (as well as reducing noise
emissions).

1-4 MC68341 USER’S MANUAL MOTOROLA

COMPACT DISC-INTERACTIVE

The MC68341 was designed to meet the needs of many markets, including compact disc­interactive (CD-I). CD-I is an standard for a publishing medium that will bring multimedia to
a broad general audience—the consumer. CD-I players combine television and stereo
systems as output devices, with interactive control using a TV remote-control-like device
to provide a multimedia experience selected from software titles contained in compressed
form on standard compact discs.

The on-chip real-time clock eliminates the need for a separate chip to keep time-of-day.
The 68000 bus interface simplifies the use of existing CD-DA and CD-I peripherals and
ASICs that were designed for use with the 68000.

The highly integrated MC68341 is ideal as the central processor for CD-I players. It
provides the M68000 microprocessor code compatibility and DMA functions required by

CD-I Green Book

the
very cost-effective solution. The extra demands of full-motion video CD-I systems make
the best use of the MC68341 high performance. The MC68341 is CD-I compliant and has
been CD-I qualified. With its low voltage operation, the MC68341V is the only practical
choice for portable CD-I.

specification as well as many other useful on-chip functions for a

MOTOROLA MC68341 USER’S MANUAL 1-5

SECTION 2
SIGNAL DESCRIPTIONS

This section contains brief descriptions of the MC68341 input and output signals in their
functional groups as shown in Figure 2-1.

MOTOROLA MC68341 USER’S MANUAL 2-1

A31/PORT A7/IACK7

A30/PORT A6/IACK6

A29/PORT A5/IACK5
A28/PORT A4/IACK4
A27/PORT A3/IACK3

A26/PORT A2/IACK2

PORT A

TCK

TMS

TDI

TDO

IPIPE/DSO

FREEZE

BKPT/DSCLK

IFETCH/DSI

SCLKX2X1

A25/PORT A1/IACK1

A24/PORT A0

A23–A0

D15–D0

TEST

CPU32

CORE

TWO-CHANNEL

SERIAL

I/O

RxDA
TxDA
CTSA

RxDB

TxDB

CTSB
FC2–FC0
FC3/DTC

RESET

BERR
HALT

AS

DS
R/W
SIZ1
SIZ0

DSACK1

EXTERNAL

BUS

INTERFACE

SYSTEM

INTEGRATION

MODULE

OUTPUT

PORT

IMB

TxRDYA/OP6
RxRDYA/FFULLA/OP4

RTSB/OP1
RTSA/OP0

DSACK0

68KAS

UDS
LDS

UWE
LWE

RMC/RTCOUT

BR

BG

BGACK

BSW

BUS

ARBITRATION

CLOCK

TWO-CHANNEL

DMA

CONTROLLER

TIMER

MODULE

QUEUED
SERIAL
MODULE

MISO
MOSI

PCS1
PCS0

QSCLK

CS7
CS6
CS5
CS4

CS3
CS2

CS1

CHIP

SELECTS

EXTAL

EXTCLK

XTAL

XFC

CLKOUT

DACK1

DREQ1

DONE1

DREQ2

DACK2

DONE2

TOUT

TIN/RDY2

TGATE/RDY1

IRQ7/PORT B7
IRQ6/PORT B6
IRQ5/PORT B5
IRQ4/PORT B4
IRQ3/PORT B3

PORT B

IRQ2/PORT B2
IRQ1/PORT B1

CS0/AVEC

MODCK/PORT B0

Figure 2-1. Functional Signal Groups

2-2 MC68341 USER’S MANUAL MOTOROLA

2.1 SIGNAL INDEX

The input and output signals for the MC68341 are listed in Table 2-1 through 2-8. The
name, mnemonic, and brief functional description are presented. For more detail on each
signal, refer to the signal paragraph. Guaranteed timing specifications for the signals listed
in the following tables can be found in Section 12 Electrical Characteristics.

Table 2-1. Bus Signal Summary

Input/

Signal Name Mnemonic

Address Bus A23–A0 Out
Address Bus/Port A7–A0/ Interrupt

Acknowledge7–1
Data Bus D15–D0 I/O

Function Code 3/DTC, FC3/DTC Out
Function Code 2–0 FC2–FC0 Out
Chip Select 7–1 CS7–CS1 Out
Interrupt Request Level/

Port B7–B1
Chip Select 0/Autovector CS0/AVEC Out/In –
Bus Request BR In –
Bus Grant BG Out No
Bus Grant Acknowledge BGACK In –
Data and Size Acknowledge DSACK1, DSACK0 In –
Read-Modify-Write Cycle/

Real-Time Clock Out
Address Strobe AS Out

Data Strobe DS Out Yes
M68000 Address Strobe 68KAS Out Yes
Upper Data Strobe UDS Out Yes
Lower Data Strobe LDS Out Yes
Upper Write Enable UWE Out Yes
Lower Write Enable LWE Out Yes
Size SIZ1, SIZ0 Out Yes
Read/Write R/W Out Yes
Reset RESET I/O No
Halt HALT I/O No
Bus Error BERR In –

A31–A24/

IACK7–1

IRQ7–1/ B7–B1 In, I/O –

RMC/RTCOUT Out Yes/No

Output

Out/I/O/

Out

Three-State During

Bus Arbitration

Yes
Yes

Yes
Yes
Yes
Yes

Yes

MOTOROLA MC68341 USER’S MANUAL 2-3

Table 2-2. CPU32 Serial Port

Input/

Signal Name Mnemonic

Instruction Fetch/
Development Serial In

Instruction Pipe/
Development Serial Out

Breakpoint/Development Serial Clock BKPT/DSCLK In/—
Freeze FREEZE Out

IFETCH /DSI Out/In

IPIPE/DSO Out/Out

Output

Table 2-3. Serial Module

Input/

Signal Name Mnemonic

Receive Data RxDB, RxDA In
Transmit Data TxDB, TxDA Out
Clear-to-Send CTSB, CTSA In
Request-to-Send/OP1, OP0 RTSB, RTSA Out/Out
Serial Crystal Oscillator X1, X2 In
Serial Clock SCLK In
Transmitter Ready/OP6 T≈RDYA Out/Out
Receiver Ready/FIFO Full/OP4 R≈RDYA Out/Out/

Output

Out

Table 2-4. Queued Serial Module

Input/

Signal Name Mnemonic

QSPI Peripheral Chip Slect PCS1, PCS0 I/O
QSPI Serial Clock QSCLK In
Master-In Slave-Out MISO I/O
Master-Out Slave-In MOSI I/O

Output

Table 2-5. DMA Module

Input/

Signal Name Mnemonic

DMA Request DREQ2,

DREQ1

DMA Acknowledge DACK2

DACK1

DMA Done DONE2, DONE1 I/O
DMA RDY1/Timer Gate TGATE, RDY1 In
DMA RDY2/Timer Input TIN, RDY2 In
DTC/FC3 TIN, RDY2 In

Output

In

Out

2-4 MC68341 USER’S MANUAL MOTOROLA

Table 2-6. Timer Module

Input/

Signal Name Mnemonic

Timer Gate/DMA RDY1 TGATE, RDY1 In
Timer Input/DMA RDY2 TIN, RDY2 In
Timer Output TOUT Out

Output

Table 2-7. IEEE 1149.1

Input/

Signal Name Mnemonic

Test Clock TCK In
Test Mode Select TMS In
Test Data In TDI In
Test Data Out TDO Out

Output

Table 2-8. Power, Clock, and Control

Input/

Signal Name Mnemonic

Clock Mode Select/
Port B0

MODCK/Port B0 In/I/O

Output

Battery Switch BSW
Battery Power In V
System Power Supply and Ground VCC, GND —

System Clock CLKOUT Out
Crystal Oscillator EXTAL, XTAL In, Out
External Clock EXTCLK In
External Filter Capacitor XFC In

BATT

In

NOTE

The terms

assert

and

negate

are used throughout this section
to avoid confusion when dealing with a mixture of active-low
and active-high signals. The term

assert

or

assertion

indicates
that a signal is active or true, independent of the level
represented by a high or low voltage. The term

negation

indicates that a signal is inactive or false.

negate

or

2.2 BUS SIGNALS

The MC68341 can interface using either a 68000 family bus or an MC68341 Family bus.
Many of the signals are common to both bus types. Refer to Section 3 Bus Operation for
more information on the two types of buses.

MOTOROLA MC68341 USER’S MANUAL 2-5

2.2.1 Address Bus

IACK7–IACK1

AS68K

The address bus signals are outputs that define the address of the byte (or the most
significant byte) to be transferred during a bus cycle. The MC68341 places the address on
the bus at the beginning of a bus cycle. The address is valid while AS is asserted.

The address bus consists of the following two groups. Refer to Section 3 Bus Operation
for information on the address bus and its relationship to bus operation.

2.2.1.1 Address Bus (A23–A0). These three-state outputs (along with A31–A24) provide
the address for the current bus cycle, except in the CPU address space.

2.2.1.2 Address Bus (A31–A24). These pins can be programmed as the most significant
eight address bits, port A parallel I/O, or interrupt acknowledge signals. These pins can be
used for more than one of their multiplexed functions as long as the external
demultiplexing circuit properly resolves interaction between the different functions.

A31–A24

These pins can function as the most significant eight address bits.

Port A7–A0

These eight pins can serve as a dedicated parallel I/O port. See Section 4 System
Integration Module for more information on programming these pins.

The MC68341 asserts one of these pins to indicate the level of an external interrupt
during an interrupt acknowledge cycle. Peripherals can use the IACK≈ signals instead of
monitoring the address bus and function codes to determine that an interrupt
acknowledge cycle is in progress and to obtain the current interrupt level.

2.2.2 Address Strobe (AS)

AS is an output timing signal for MC68300 cycles that indicates the validity of both an
address on the address bus and many control signals. AS is asserted approximately one­half clock cycle after the beginning of a bus cycle.

2.2.3 M68000 Address Strobe (

)

AS68K is an output timing signal for MC68000 cycles that indicates that the information on
the address bus is a valid address.

2.2.4 Data Bus (D15–D0)

This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or
from the MC68341. A read or write operation may transfer 8 or 16 bits of data (one or two
bytes) in one bus cycle. During a read cycle, the data is latched by the MC68341 on the
last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus
are driven, regardless of the port width or operand size. The MC68341 places the data on
the data bus approximately one-half clock cycle after AS is asserted in a write cycle.

2-6 MC68341 USER’S MANUAL MOTOROLA

2.2.5 Data Strobe (DS)

UDS, LDS

UDS LDS

W

UWE, LWE

DS is an output timing signal for M68300 transfers that applies to the data bus. For a read
cycle, the MC68341 asserts DS
place data on the bus. For a write cycle, DS signals to the external device that the data to
be written is valid. The MC68341 asserts DS approximately one clock cycle after the
assertion of AS during a write cycle.

and AS simultaneously to signal the external device to

2.2.6 Upper And Lower Data Strobes (

)

These three-state signals and R/ W control the flow of data on the data bus for M68000
transfers. Table 2-9 lists the combinations of these signals and the corresponding data on
the bus. UDS and LDS assert with AS68K for read cycles, and one clock after AS for write
cycles. The equations of the data strobes are as follows:

UDS = A0
LDS =

Table 2-9. Data Strobe Control of Data Bus

Low Low High Valid Data Bits

High Low High No Valid Data Valid Data Bits

Low High High Valid Data Bits

Low Low Low Valid Data Bits

A0 × SIZ1 × SIZ0

R/

D15–D8 D7–D0

15–8

15–8

15–8

Valid Data Bits

7–0

7–0

No Valid Data

Valid Data Bits

7–0

2.2.7 Byte Write Enable (

)

On a write cycle to a 16-bit port, these active-low output signals indicate when the upper
or lower eight bits of the data bus contain valid data. The upper write enable (UWE)
indicates that the upper eight bits of the data bus contain valid data during a write cycle.
The lower write enable (LWE) indicates that the lower eight bits of the data bus contain
valid data during a write cycle. UWE and LWE assert with DS for an MC68300 write and
with UDS/LDS for a 68000 write cycle. The equations of the byte write enables are as
follows:

UWE =
LWE =

R/W + AS + A0

R/W + AS + (A0 × SIZ0)

2.2.8 Read/Write (R/W)

This active-high output signal is driven by the bus master to indicate the direction of a data
transfer on the bus. A logic one indicates a read from a slave device; a logic zero indicates
a write to a slave device.

MOTOROLA MC68341 USER’S MANUAL 2-7

2.2.9 Transfer Size (SIZ1, SIZ0)

(CS7—CS1, CS0/AVEC)

These output signals are driven by the bus master to indicate the number of operand
bytes remaining to be transferred in the current bus cycle as noted in Table 2-10.

Table 2-10. SIZx Signal Encoding

SIZ1 SIZ0 Transfer Size

0 1 Byte
1 0 Word
1 1 Three Byte
0 0 Long Word

2.2.10 Function Codes (FC3–FC0)

These signals are outputs that indicate one of 16 address spaces to which the address
applies. Fifteen of these spaces are designated as either user or supervisor, program or
data, and normal or direct memory access (DMA) spaces. One other address space is
designated as CPU space to allow the CPU32 to acquire specific control information not
normally associated with read or write bus cycles. The function code signals are valid
while AS is asserted. See Table 2-11 for more information.

Table 2-11. Address Space Encoding

Function Code Bits

3210 Address Spaces

0000Reserved (Motorola)
0001User Data Space
0010User Program Space
0011Reserved (User )
0100Reserved (Motorola)
0101Supervisor Data Space
0110Supervisor Program Space
0111CPU Space
1 x x x DMA Space

2.2.11 Chip Selects

The chip select output signals (CS7–CS1) enable peripherals at programmed
addresses. These signals are inactive high (not high impedance) after reset.

CS0 is the chip select for a boot ROM containing the reset vector and initialization
program. It functions as the boot chip select immediately after reset. AVEC requests an
automatic vector during an interrupt acknowledge cycle.

2-8 MC68341 USER’S MANUAL MOTOROLA

2.2.12 Interrupt Request Level

(IRQ7 — IRQ1)

IRQ7

IRQ1

DSACK1, DSACK0

DSACK¯

DSACK1 DSACK0

These pins can be programmed to be either prioritized interrupt request lines or port B
parallel I/O.

–

IRQ7, the highest priority, is nonmaskable. IRQ6–IRQ1 are internally maskable
interrupts. Refer to Section 5 CPU32 for more information on interrupt request lines.

Port B7 – B1

These pins can be used as port B parallel I/O. Refer to Section 4 System Integration
Module for more information on parallel I/O signals.

2.3 BUS CONTROL SIGNALS

These signals control the bus transfer operations of the MC68341. Refer to Section 3
Bus Operation for more information on these signals.

2.3.1 Data and Size Acknowledge (

)

These two active-low input signals allow asynchronous data transfers and dynamic data
bus sizing between the MC68341 and external devices as listed in Table 2-12. During bus
cycles, external devices assert DSACK1 and/or DSACK0 as part of the bus protocol.
During a read cycle, this signals the MC68341 to terminate the bus cycle and to latch the
data. During a write cycle, this indicates that the external device has successfully stored
the data and that the cycle may terminate.

Table 2-12.

Encoding

Result

1 1 Insert Wait States in Current Bus Cycle
1 0 Complete Cycle—Data Bus Port Size Is 8 Bits
0 1 Complete Cycle—Data Bus Port Size Is 16 Bits
0 0 Reserved—Defaults to 16-Bit Port Size. Can Be

Used for 32-Bit DMA Cycles

2.4 BUS ARBITRATION SIGNALS

The following signals are the bus arbitration control signals used to determine the bus
master. Refer to Section 3 Bus Operation for more information on these signals.

2.4.1 Bus Request (BR)

This active-low input signal indicates that an external device needs to become the bus
master.

MOTOROLA MC68341 USER’S MANUAL 2-9

2.4.2 Bus Grant (

BG

(BGACK)

RMC

RESET

HALT

BERR

)

Assertion of this active-low output signal indicates that the MC68341 has relinquished the
bus.

2.4.3 Bus Grant Acknowledge

Assertion of this active-low input indicates that an external device has become the bus
master.

2.4.4 Read-Modify-Write Cycle (

/RTCOUT)

RMC is an output signal that identifies the bus cycle as part of an indivisible read-modify­write operation. It remains asserted during all bus cycles of the read-modify-write
operation to indicate that bus ownership cannot be transferred.

RTCOUT is an output signal from the real-time clock in the SIM41.

2.5 EXCEPTION CONTROL SIGNALS

These signals are used by the MC68341 to recover from an exception.

2.5.1 Reset (

)

This active-low, open-drain, bidirectional signal is used to initiate a system reset. An
external reset signal (as well as a reset from the SIM41) resets the MC68341 and all
external devices. A reset signal from the CPU32 (asserted as part of the RESET
instruction) resets external devices; the internal state of the CPU32 is not affected. The
on-chip modules are reset, except for the SIM41. However, the module configuration
register for each on-chip module is not altered. When asserted by the MC68341, this
signal is guaranteed to be asserted for a minimum of 512 clock cycles. Refer to Section 3
Bus Operation for a description of bus reset operation and Section 5 CPU32 for
information about the reset exception.

2.5.2 Halt (

)

This active-low, open-drain, bidirectional signal is asserted to suspend external bus
activity, to request a retry when used with BERR , or to perform a single-step operation. As
an output, HALT indicates a double bus fault by the CPU32. Refer to Section 3 Bus

Operation for a description of the effects of HALT on bus operation.

2.5.3 Bus Error (

)

This active-low input signal indicates that an invalid bus operation is being attempted or,
when used with HALT, that the processor should retry the current cycle. Refer to Section
3 Bus Operation for a description of the effects of BERR on bus operation.

2-10 MC68341 USER’S MANUAL MOTOROLA

2.6 CLOCK SIGNALS

(IFETCH

These signals are used by the MC68341 for controlling or generating the system clocks.
See Section 4 System Integration Module for more information on the various clocking
methods and frequencies.

2.6.1 System Clock (CLKOUT)

This output signal is the system clock output and is used as the bus timing reference by
external devices. CLKOUT can be varied in frequency or slowed in low power stop mode
to conserve power.

2.6.2 Crystal Oscillator (EXTAL, XTAL)

These two pins are the connections for an external crystal to the internal oscillator circuit.

2.6.3 External Clock (EXTCLK)

This pin used to connect an external clcok source. This input is divided by two until the V ­bit in the SYNCR is set.

2.6.4 External Filter Capacitor (XFC)

This pin is used to add an external capacitor to the filter circuit of the phase-locked loop.
The capacitor should be connected between XFC and VCCSYN.

2.6.5 Clock Mode Select (MODCK, Port B0)

This pin selects the source of the internal system clock during reset. After reset, it can be
programmed to be port B parallel I/O.

MODCK

The state of this active-high input signal during reset selects the source of the internal
system clock. If MODCK is high during reset, the internal voltage-controlled oscillator
(VCO) furnishes the system clock in crystal mode. If MODCK is low during reset, an
external clock source at the EXTCLK pin furnishes the system clock output in external
clock mode.

Port B0

This pin can be used as a port B parallel I/O.

2.7 INSTRUMENTATION AND EMULATION SIGNALS

These signals are used for test or software debugging. See Section 5 CPU32 for more
information on these signals and background debug mode.

2.7.1 Instruction Fetch

/ DSI)

This pin functions as IFETCH in normal operation and as DSI in background debug mode.

MOTOROLA MC68341 USER’S MANUAL 2-11

IFETCH

(IPIPE/

)

IPIPE

(BKPT

)

BKPT

DREQ2, DREQ1

This active-low output signal indicates when the CPU32 is performing an instruction
word prefetch and when the instruction pipeline has been flushed.

DSI

This development serial input signal helps to provide serial communications for
background debug mode.

2.7.2 Instruction Pipe

This pin functions as IPIPE in normal operation and as DSO in background debug mode.

This active-low output signal is used to track movement of words through the instruction
pipeline.

DSO

This development serial output signal helps to provide serial communications for
background debug mode.

2.7.3 Breakpoint

/DSCLK

This pin functions as BKPT in normal operation and as DSCLK in background debug
mode.

This active-low input signal is used to signal a hardware breakpoint to the CPU32.

DSCLK

This development serial clock input helps to provide serial communications for
background debug mode.

DSO

2.7.4 Freeze (FREEZE)

Assertion of this active-high output signal indicates that the CPU32 has acknowledged a
breakpoint and has initiated background mode operation.

2.8 DMA MODULE SIGNALS

The following signals are used by the direct memory access (DMA) controller module to
provide external handshake for either a source or destination. See Section 6 DMA

Module for additional information on these signals.

2.8.1 DMA Request (

)

This active-low input is asserted by a peripheral device to request an operand transfer
between that peripheral and memory. The assertion of DREQ≈ starts the DMA process.

2-12 MC68341 USER’S MANUAL MOTOROLA

The assertion level in external burst mode is level sensitive; in external cycle steal mode,

(DACK2, DACK1)

DONE2, DONE1

DTC

RDY2, RDY1

it is falling-edge sensitive.

2.8.2 DMA Acknowledge

DACK≈ is asserted by the DMA to signal to a peripheral that an operand is being
transferred in response to a previous transfer request. A delayed version of DACK≈ is
provided to allow operation with differing speed memories. The delayed form of DACK2
and DACK1 can be selected by setting bits 4 and 5 in the PPARC (See Section 6 DMA

Controller Module).

2.8.3 DMA Done (

)

This active-low output signal is asserted by the DMA or a peripheral device during any
DMA bus cycle to indicate that the last data transfer is being performed. DONE≈ is an
active input in any mode. As an output, it is only active in external request mode. An
external pullup resistor is required even during operation in the internal request mode.

2.8.4 Data Transfer Complete (

)

This active-low bidirectional signal is asserted on all bus cycles (DMA and CPU initiated)
as an extra signal in standard bus timing. DTC is multiplexed with FC3, and is selected by
setting PPARC bit 3.

2.8.5 DMA Ready (

)

These active-low bidirectional signal is only asserted on DMA single-address transfers to
indicate that the device has supplied data or is ready to receive data from memory. RDY2
is multiplexed with TIN, and RDY1 is multiplexed with TGATE. RDY2 is selected by setting
PPARC bit 0, and RDY1 is selected by setting PPARC bit 1.

2.9 SERIAL MODULE SIGNALS

The following signals are used by the serial module for data and clock signals. See

Section 7 Serial Module for more information on these signals.

2.9.1 Serial Crystal Oscillator (X2, X1)

These pins furnish the connection to a crystal or external clock, which must be supplied
when using the baud rate generator. An external clock can be connected to the X1 pin; X2
is left floating in this case.

2.9.2 Serial External Clock Input (SCLK)

This input can be used as the external clock input for channel A or channel B, bypassing
the baud rate generator.

MOTOROLA MC68341 USER’S MANUAL 2-13

2.9.3 Receive Data (RxDA, RxDB)

(CTSA, CTSB)

(RTSA

, RTSB

/

)

RTSB, RTSA

(T¯RDYA /

)

T¯RDYA

(R¯RDYA/

FFULLA/

OP4)

These signals are the receiver serial data input for each channel. Data received on this
signal is sampled on the rising edge of the clock source, with the least significant bit
received first.

2.9.4 Transmit Data (TxDA, TxDB)

These signals are the transmitter serial data output for each channel. The output is held
high ('mark' condition) when the transmitter is disabled, idle, or operating in the local
loopback mode. Data is shifted out on this signal at the falling edge of the clock source,
with the least significant bit transmitted first.

2.9.5 Clear to Send

These active-low signals can be programmed as the clear-to-send inputs for each
channel.

2.9.6 Request to Send

These active-low signals can be programmed as request-to-send outputs or used as
discrete outputs.

When used for this function, these signals function as the request-to-send outputs.

OP1, OP0

When used for this function, these outputs are controlled by the value of bit 1 and bit 0,
respectively, in the output port data registers.

2.9.7 Transmitter Ready

This active-low output can be programmed as the channel A transmitter ready status
indicator or used as a discrete output.

When used for this function, this signal reflects the complement of the status of bit 2 of
the channel A status register. This signal can be used to control parallel data flow by
acting as an interrupt to indicate when the transmitter contains a character.

/OP0

OP6

OP1

OP6

When used for this function, this output is controlled by bit 6 in the output port data
registers.

2.9.8 Receiver Ready

This active-low output signal can be programmed as the channel A receiver ready,
channel A FIFO full indicator, or a dedicated parallel output.

2-14 MC68341 USER’S MANUAL MOTOROLA

R¯RDYA

FFULLA

PCS1, PCS0

TGATE 2

When used for this function, this signal reflects the complement of the status of bit 1 of
the interrupt status register. This signal can be used to control parallel data flow by
acting as an interrupt to indicate when the receiver contains a character.

When used for this function, this signal reflects the complement of the status of bit 1 of
the interrupt status register. This signal can be used to control parallel data flow by
acting as an interrupt to indicate when the receiver FIFO is full.

OP4

When used for this function, this output is controlled by bit 4 in the output port data
registers.

2.10 QUEUED SERIAL MODULE SIGNALS

The following external signals are used by the queued serial peripheral module. See

Section 9 QSPM for additional information on these signals.

2.10.1 Master In Slave Out (MISO)

This bidirectional signal can be the serial data input to the QSPI when the QSPI is the
master device, or the the serial data output when using an external master.

2.10.2 Master Out Slave In (MOSI)

This bidirectional signal can be the serial data input to the QSPI when using an external
master, or the the serial data output when the QSPI is the master device.

2.10.3 QSPI Serial Clock (QSCLK)

This input is the external clock input for the QSPI.

2.10.4 QSPI Peripheral Chip Select (

)

These output signals are the chip selects for the QSPI.

2.11 TIMER SIGNALS

The following external signals are used by the timer modules. See Section 8 Timer
Modules for additional information on these signals.

2.11.1 Timer Gate (

)

This active-low input can be programmed to enable and disable the counters and
prescalers. TGATE can also be programmed as a simple input.

MOTOROLA MC68341 USER’S MANUAL 2-15

2.11.2 Timer Input (TIN)

BSW

This input can be programmed as a clock that causes events to occur in the counters and
prescalers.

2.11.3 Timer Output (TOUT)

This output drives the various output waveforms generated by the timers.

2.12 TEST SIGNALS

The following signals are used with the on-board test logic defined by the IEEE 1149.1
standard. See Section 10 IEEE 1149.1 Test Access Port for more information on the use
of these signals.

2.12.1 Test Clock (TCK)

This input provides a clock for on-board test logic defined by the IEEE 1149.1 standard.

2.12.2 Test Mode Select (TMS)

This input controls test mode operations for on-board test logic defined by the IEEE

1149.1 standard.

2.12.3 Test Data In (TDI)

This input is used for serial test instructions and test data for on-board test logic defined
by the IEEE 1149.1 standard.

2.12.4 Test Data Out (TDO)

This output is used for serial test instructions and test data for on-board test logic defined
by the IEEE 1149.1 standard.

2.13 REAL TIME CLOCK SIGNALS

2.13.1 Battery Switch (

)

This signal determines whether the entire chip is powered from VCC or only the real-time
clock is powered from V
more information.

2.13.2 Battery Voltage (V

This pin supplies power to maintain the real-time clock when the rest of the chip is
powered down. See Section 4 System Integration Module for more information.

BATT or VCC

BATT

. See Section 4 System Integration Module for

)

2-16 MC68341 USER’S MANUAL MOTOROLA

2.13.3 Real Time Clock Output (

RMC

/RTCOUT)

RTCOUT is an output signal that is selected by setting PPARC bit 2. The function is
defined by RCR bits 3 and 4.

2.14 SYSTEM POWER AND GROUND (V

These pins provide system power and ground to the MC68341. Multiple pins are provided
for adequate current capability. All power supply pins must have adequate bypass
capacitance for high-frequency noise suppression.

AND GND)

CC

MOTOROLA MC68341 USER’S MANUAL 2-17

SECTION 3
BUS OPERATION

This section provides a functional description of the bus, the signals that control it, and the
bus cycles provided for data transfer operations. It also describes the error and halt
conditions, bus arbitration, and reset operation. Operation of the external bus is the same
whether the MC68341 or an external device is the bus master; the names and
descriptions of bus cycles are from the viewpoint of the bus master. For exact timing
specifications, refer to Section 12 Electrical Characteristics.

The MC68341 architecture supports byte, word, and long-word operands allowing access
to 8- and 16-bit data ports through the use of asynchronous cycles controlled by the
SIZ1/SIZ0 outputs and DSACK1/DSACK0 inputs. The MC68341 requires word and long­word operands to be located in memory on word boundaries. The only type of transfer that
can be performed to an odd address is a single-byte transfer, referred to as an odd-byte
transfer. For an 8-bit port, multiple bus cycles may be required for an operand transfer due
to either misalignment or a word or long-word operand.

The MC68341 also supports basic MC68000 bus interface timing compatibility, in addition
to the normal M68300 bus interface timing used by other members of the M68300 family
such as the MC68332 and MC68340. This 68000 bus support allows ASICs and other
custom logic developed for MC68000-style buses to more easily migrate to the MC68341.
In this section, reference to 68000 bus timing refers to bus cycle timing used by the
MC68000, MC68EC000, MC68HC000, MC68HC001, MC68008, and MC68010.

3.1 68000 BUS MODE

The MC68341 bus interface is dynamically selectable between M68300 and 68000 bus
timing , and is individually controlled for each chip select by programming the Bus Select
Register (BSR) in the SIM41. Accesses which match a chip select configured for 68000
bus timing cause an 68000 bus access. All other accesses use normal M68300 bus cycle
signals and timing.

NOTE

Bus cycle examples in this section show normal M68300 bus
cycle timing unless specifically noted as an 68000 bus cycle.

The three strobe signals AS68K, UDS, and LDS are dedicated for 68000 bus cycles.
These signals assert only for 68000 bus cycles, while AS and DS assert only for M68300
bus cycles. The timing of shared signals CS≈, UWE, and LWE is modified depending on

MOTOROLA MC68341 USER’S MANUAL 3-1

selection of the bus cycle type. All other bus interface signals retain the same timing and
functionality between the two bus timing modes.

The dual nature of the MC68341 bus interface can result in 68000 bus functionality which
is not supported by the original MC68000. Designs which are intended to provide reverse
compatibility to the MC68000 should not utilize this superset functionality. The following
list notes differences between the 68000 bus timing implemented on the MC68341 and
bus timing on the MC68000.

• Address strobe AS68K negates between the read and write cycles of a read-modify­write operation.

•R/W transitions with address timing instead of with address strobe, and does not
negate between writes.

• On write cycles, the data bus is driven 1/2 clock sooner (during S2 rather than S3).

• DSACK≈ and BERR can be recognized on the falling edge of state S2 (one clock
earlier than on the MC68000), allowing a three clock 68000 bus cycle.

• Data strobes and write enables are asserted for aproximately one-half clock for a
three-clock write cycle.

• 68000 chip selects can be programmed for zero wait-state (three clock bus cycles)
internal termination. Programming a 68000 chip select for fast termination (two clock
bus cycles) results in undefined strobe timing.

• The MC68341 recognizes late bus error and late retry on 68000 accesses.

• The MC68341 supports dynamic bus sizing on 68000 accesses, allowing both 8-bit
(DSACK0 termination) and 16-bit (DSACK1 termination) port sizes. For an 8-bit port,
UDS and LDS must be combined externally to obtain a single 68000 data strobe
signal, since DS does not assert for 68000 bus accesses.

• 68000 chip selects are programmed with AS68K timing instead of UDS /LDS . These
selects contain the byte address information of UDS /LDS .

• Upper and lower write enables (UWE and LWE) are provided to support a glueless
interface to external SRAM.

• DACK≈ asserts with AS timing for both M68300 and 68000 bus cycles.

3.2 BUS TRANSFER SIGNALS

The bus transfers information between the MC68341 and external memory or a peripheral
device. External devices can accept or provide 8 bits or 16 bits in parallel and must follow
the handshake protocol described in this section. The maximum number of bits accepted
or provided during a bus transfer is defined as the port width. The MC68341 contains an
address bus that specifies the address for the transfer and a data bus that transfers the
data. Control signals indicate the beginning and type of the cycle as well as the address
space and size of the transfer. The selected device then controls the length of the cycle
with the signal(s) used to terminate the cycle. Strobe signals, one for the address bus and
another for the data bus, indicate the validity of the address and provide timing information
for the data. Both asynchronous and synchronous operation is possible for any port width.

3-2 MC68341 USER’S MANUAL MOTOROLA

In asynchronous operation, the bus and control input signals are internally synchronized to
the MC68341 clock, introducing a delay. This delay is the time required for the MC68341
to sample an input signal, synchronize the input to the internal clocks, and determine
whether it is high or low. In synchronous mode, the bus and control input signals must be
timed to setup and hold times. Since no synchronization is needed, bus cycles can be
completed in three clock cycles in this mode. Additionally, using the fast-termination option
of the chip select signals, two-clock operation is possible.

Furthermore, for all inputs, the MC68341 latches the level of the input during a sample
window around the falling edge of the clock signal. This window is illustrated in Figure 3-1,
where tsu and th are the input setup and hold times, respectively. To ensure that an input
signal is recognized on a specific falling edge of the clock, that input must be stable during
the sample window. If an input makes a transition during the window time period, the level
recognized by the MC68341 is not predictable; however, the MC68341 always resolves
the latched level to either a logic high or low before using it. In addition to meeting input
setup and hold times for deterministic operation, all input signals must obey the protocols
described in this section.

t

su

t

h

CLKOUT

EXT

SAMPLE WINDOW

Figure 3-1. Input Sample Window

NOTE

The terms

assert

and

negate

are used throughout this section
to avoid confusion when dealing with a mixture of active-low
and active-high signals. The term

assert

or

assertion

indicates
that a signal is active or true independent of the level
represented by a high or low voltage. The term

negation

3.2.1 Bus Control Signals

indicates that a signal is inactive or false.

negate

or

The MC68341 initiates a bus cycle by driving the A31–A0, SIZx, FCx, and R/W outputs. At
the beginning of a bus cycle, SIZ1 and SIZ0 are driven with FC3–FC0. SIZ1 and SIZ0
indicate the number of bytes remaining to be transferred during an operand cycle
(consisting of one or more bus cycles). Table 3-1 lists the encoding of the SIZx signal.
These signals are valid while AS or AS68K is asserted. The R/ W signal determines the

MOTOROLA MC68341 USER’S MANUAL 3-3

direction of the transfer during a bus cycle. Driven at the beginning of a bus cycle, R/ W is
valid while AS or AS68K is asserted. R/ W only transitions when a write cycle is preceded
by a read cycle or vice versa. The signal may remain low for consecutive write cycles. The
RMC signal is asserted at the beginning of the first bus cycle of a read-modify-write
operation and remains asserted until completion of the final bus cycle of the operation.

Table 3-1. SIZx Signal Encoding

SIZ1 SIZ0 Transfer Size

0 1 Byte
1 0 Word
1 1 Three Bytes
0 0 Long Word

3.2.2 Function Code Signals

FC3–FC0 are outputs that indicate one of 16 address spaces to which the address
applies. Fifteen of these spaces are designated as either user or supervisor, program or
data, and normal or direct memory access (DMA) spaces. One other address space is
designated as CPU space to allow the CPU32 to acquire specific control information not
normally associated with read or write bus cycles. FC3–FC0 are valid while AS or AS68K
is asserted.

Function codes (see Table 3-2) can be considered as extensions of the 32-bit address
that can provide up to 16 different 4-Gbyte address spaces. Function codes are
automatically generated by the CPU32 to select address spaces for data and program at
both user and supervisor privilege levels, a CPU address space for processor functions,
and an alternate master address space. User programs access only their own program
and data areas to increase protection of system integrity and can be restricted from
accessing other information. The S-bit in the CPU32 status register is set for supervisor
accesses and cleared for user accesses to provide differentiation. Refer to 3.5 CPU
Space Cycles for more information.

Function code FC3 is multiplexed with DTC, and the ability to use FC3 is lost if DTC is
selected. If DMA transfers are programmed with FC3 set, this signal can be used
externally to distinguish DMA bus activity from CPU accesses.

3-4 MC68341 USER’S MANUAL MOTOROLA

Table 3-2. Address Space Encoding

AS68K

Function Code Bits

3210 Address Spaces

0000Reserved (Motorola)
0001User Data Space
0010User Program Space
0011Reserved (User )
0100Reserved (Motorola)
0101Supervisor Data Space
0110Supervisor Program Space
0111CPU Space
1 x x x DMA Space

3.2.3 Address Bus (A31–A0)

These signals are outputs that define the address of the byte (or the most significant byte)
to be transferred during a bus cycle. The MC68341 places the address on the bus at the
beginning of a bus cycle. The address is valid while AS or AS68K is asserted.

3.2.4 Address Strobe (AS)

This output timing signal indicates the validity of many control signals and the address on
the address bus. AS is asserted for M68300 bus cycles approximately one-half clock cycle
after the beginning of a bus cycle. AS remains negated for a 68000 bus cycle.

3.2.5 68000 Address Strobe (

)

AS68K is asserted for 68000 bus cycles approximately one clock cycle after the beginning
of a bus cycle. AS68K remains negated for normal M68300 bus cycles.

3.2.6 Data Bus (D15–D0)

This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or
from the MC68341. A read or write operation may transfer 8 or 16 bits of data (one or two
bytes) in one bus cycle. During a read cycle, the data is latched by the MC68341 on the
last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus
are driven, regardless of the port width or operand size. The MC68341 places the data on
the data bus approximately one-half clock cycle after AS is asserted in a write cycle, or at
the same time as AS68K is asserted.

3.2.7 Data Strobe (DS)

DS is an M68300 output timing signal that applies to the data bus. For an M68300 read
cycle, the MC68341 asserts DS

and AS simultaneously to signal the external device to

place data on the bus. For an M68300 write cycle, DS signals to the external device that
the data to be written is valid. The MC68341 asserts DS approximately one clock cycle

MOTOROLA MC68341 USER’S MANUAL 3-5

after the assertion of AS during a write cycle. DS remains negated during 68000 bus

UDS

LDS

UWE

LWE

DTC

DSACK1

DSACK0

cycles.

3.2.8 Upper and Lower Data Strobes (

UDS and LDS are asserted for the active bytes of a 68000 bus cycle, one-half clock later
than DS on the corresponding M68300 bus cycle. UDS is asserted to select the upper 8
bits of the data bus (D15-D0) and LDS is asserted for the lower 8 bits (D8-D0). UDS and
LDS remain negated for normal M68300 bus cycles.

3.2.9 Upper and Lower Write Enables (

On a write cycle to a 16-bit port, these active-low output signals indicate when the upper
or lower eight bits of the data bus contain valid data. The upper write enable (UWE )
indicates that the upper eight bits of the data bus contain valid data during a write cycle.
The lower write enable (LWE) indicates that the lower eight bits of the data bus contain
valid data during a write cycle. The equations of the byte write enables are as follows:

68300 bus cycle

68000 bus cycle

3.2.10 Data Transfer Complete (

: UWE = R/W + DS + A0

LWE =

: UWE = R/W + UDS

LWE =

R/W + DS + (A0 • SIZ0)

R/W + LDS

)

and

and

)

)

This active-low output signal indicates the last clock of a normally terminated bus cycle.
DTC does not assert for bus cycles terminated with normal bus error or normal retry
terminations, but does assert for late bus error and late retry.

3.2.11 Bus Cycle Termination Signals

The following signals can terminate a bus cycle.

3.2.11.1 DATA TRANSFER AND SIZE ACKNOWLEDGE SIGNALS (

). During bus cycles, external devices assert DSACK1 and/or DSACK0 as part of

the bus protocol. During a read cycle, this signals the MC68341 to terminate the bus cycle
and to latch the data. During a write cycle, this indicates that the external device has
successfully stored the data and that the cycle may terminate. These signals also indicate
to the MC68341 the size of the port for the bus cycle just completed (see Table 3-3). Refer
to 3.4.1 Read Cycle for timing relationships of DSACK1 and DSACK0.

Additionally, the system integration module (SIM41) chip select address mask register can
be programmed to internally generate DSACK1 and DSACK0 for external accesses,
eliminating logic required to generate these signals. However, if external DSACK≈ signals
are returned earlier than indicated by the EDS and DD bits in the chip select address
mask register, the cycle will terminate sooner than programmed. Refer to Section 4
System Integration Module for additional information. The SIM41 can alternatively be

3-6 MC68341 USER’S MANUAL MOTOROLA

AND

programmed to generate a fast termination cycle, providing a two-cycle external access.

BERR

AVEC

Refer to 3.3.6 Fast Termination Cycles for additional information on these cycles.

3.1.11.2 BUS ERROR (

can be used in the absence of DSACK≈ to indicate a bus error condition. BERR can also
be asserted in conjunction with DSACK≈ to indicate a bus error condition, provided it
meets the appropriate timing described in this section and in Section 12 Electrical
Characteristics. Additionally, BERR and HALT can be asserted together to indicate a
retry termination. Refer to 3.6 Bus Exception Control Cycles for additional information
on the use of these signals.

The internal bus monitor can be used to generate an internal bus error signal for internal
and internal-to-external transfers. If the bus cycles of an external bus master are to be
monitored, external BERR generation must be provided since the internal bus error
monitor has no information about transfers initiated by an external bus master.

3.2.11.3 AUTOVECTOR (

acknowledge cycles, indicating that the MC68341 should internally generate a vector
(autovector) number to locate an interrupt handler routine. AVEC can be generated either
externally or internally by the SIM41 (see Section 4 System Integration Module for
additional information). AVEC is ignored during all other bus cycles.

). This signal is also a bus cycle termination indicator and

).This signal can be used to terminate interrupt

3.3 DATA TRANSFER MECHANISM

The MC68341 supports byte, word, and long-word operands, allowing access to 8- and
16-bit data ports through the use of asynchronous cycles controlled by DSACK1 and
DSACK0. The MC68341 also supports byte, word, and long-word operands, allowing
access to 8- and 16-bit data ports through the use of synchronous cycles controlled by the
fast termination capability of the SIM41.

3.3.1 Dynamic Bus Sizing

The MC68341 dynamically interprets the port size of the addressed device during each
bus cycle, allowing operand transfers to or from 8- and 16-bit ports. During an operand
transfer cycle, the slave device signals its port size (byte or word) and indicates
completion of the bus cycle to the MC68341 through the use of the DSACK≈ inputs. Refer
to Table 3-3 for DSACK≈ encoding.

MOTOROLA MC68341 USER’S MANUAL 3-7

Table 3-3.

DSACK¯

DSACK1 DSACK0

Encoding

Result

1

(Negated)1(Negated) Insert Wait States in Current Bus Cycle

1

(Negated)0(Asserted) Complete Cycle—Data Bus Port Size Is 8 Bits

0

(Asserted)1(Negated) Complete Cycle—Data Bus Port Size Is 16 Bits

0

(Asserted)0(Asserted)

Reserved—Defaults to 16-Bit Port Size Can Be
Used for 32-Bit DMA cycles

For example, if the MC68341 is executing an instruction that reads a long-word operand
from a 16-bit port, the MC68341 latches the 16 bits of valid data and runs another bus
cycle to obtain the other 16 bits. The operation from an 8-bit port is similar, but requires
four read cycles. The addressed device uses DSACK≈ to indicate the port width. For
instance, a 16-bit device always returns DSACK≈ for a 16-bit port (regardless of whether
the bus cycle is a byte or word operation).

Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from
a particular port size be fixed. A 16-bit port must reside on data bus bits 15–0, and an 8-bit
port must reside on data bus bits 15–8. This requirement minimizes the number of bus
cycles needed to transfer data to 8- and 16-bit ports and ensures that the MC68341
correctly transfers valid data.

The MC68341 always attempts to transfer the maximum amount of data on all bus cycles;
for a word operation, it always assumes that the port is 16 bits wide when beginning the
bus cycle. The bytes of operands are designated as shown in Figure 3-2. The most
significant byte of a long-word operand is OP0, and OP3 is the least significant byte. The
two bytes of a word-length operand are OP0 (most significant) and OP1. The single byte
of a byte-length operand is OP0. These designations are used in the figures and
descriptions that follow.

Figure 3-2 shows the required organization of data ports on the MC68341 bus for both
8- and 16-bit devices. The four bytes shown in Figure 3-2 are connected through the
internal data bus and data multiplexer to the external data bus. The data multiplexer
establishes the necessary connections for different combinations of address and data
sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their
required positions. The positioning of bytes is determined by the SIZ1/SIZ0 and A0
outputs. The SIZ1/SIZ0 outputs indicate the number of bytes to be transferred during the
current bus cycle (see Table 3-1). The number of bytes transferred during a read or write
bus cycle is equal to or less than the size indicated by the SIZ1/SIZ0 outputs, depending
on port width. For example, during the first bus cycle of a long-word transfer to a word
port, the size outputs indicate that four bytes are to be transferred although only two bytes
are moved on that bus cycle.

The address line A0 also affects the operation of the data multiplexer. During an operand
transfer, A31–A1 indicate the word base address of that portion of the operand to be

3-8 MC68341 USER’S MANUAL MOTOROLA

accessed, and A0 indicates the byte offset from the base (i.e., either odd or even byte).
Figure 3-2 lists the bytes required on the data bus for read cycles. The entries shown as
OPn are portions of the requested operand that are read or written during that bus cycle
and are defined by SIZ1/SIZ0 and A0 for the bus cycle.

OPERAND

31

23

OP1OP0
OP0

OP2
OP1
OP0

15

OP3
OP2
OP1
OP0

70

Transfer Case

Case

A0SIZ0SIZ1

(a)

Byte to Byte

(b)

Byte to Word (Even)

(c)

Byte to Word (Odd)

(d)

Word to Byte (Aligned)

(e)

Word to Word (Aligned)

(f)

Long Word to Byte (Aligned)

(g)

Long Word to Word (Aligned)

NOTES: 

1. Operands in parentheses are ignored by the MC68340 during read cycles.

2. A 3-byte to byte transfer does occur as the second byte transfer of a long-word to byte port transfer.

01X10
0100X
0110X
10010
1000X
00010
0000X

DSACK0DSACK1

Data Bus

D15 D7

D8
OP0
OP0

(OP0)

OP0
OP0
OP0
OP0 OP1

D0

(OP0)
(OP0)

OP0

(OP1)

OP1

(OP1)

Figure 3-2. MC68341 Interface to Various Port Sizes

3.3.2 Misaligned Operands

In this architecture, the basic operand size is 16 bits. Operand misalignment refers to
whether an operand is aligned on a word boundary or overlaps the word boundary,
determined by address line A0. When A0 is low, the address is even and is a word and
byte boundary. When A0 is high, the address is odd and is a byte boundary only. A byte
operand is properly aligned at any address; a word or long-word operand is misaligned at
an odd address.

At most, each bus cycle can transfer a word of data aligned on a word boundary. If the
MC68341 transfers a long-word operand over a 16-bit port, the most significant operand
word is transferred on the first bus cycle, and the least significant operand word is
transferred on a following bus cycle.

The CPU32 restricts all operands (both data and instructions) to be aligned. That is, word
and long-word operands must be located on a word or long-word boundary, respectively.
The only type of transfer that can be performed to an odd address is a single-byte
transfer, referred to as an odd-byte transfer. If a misaligned access is attempted, the
CPU32 generates an address error exception , and enters exception processing. Refer to
Section 5 CPU32 for more information on exception processing.

MOTOROLA MC68341 USER’S MANUAL 3-9

3.3.3 Operand Transfer Cases

The following cases are examples of the allowable alignments of operands to ports.

3.3.3.1 BYTE OPERAND TO 8-BIT PORT, ODD OR EVEN (A0 = X). The MC68341
drives the address bus with the desired address and the SIZx pins to indicate a single ­byte operand.

BYTE OPERAND

DATA BUS

CYCLE 1

OP0

7

0

D0D8D15 D7

(OP0)OP0

01X10

DSACK0DSACK1A0SIZ0SIZ1

For a read operation, the slave responds by placing data on bits 15–8 of the data bus,
asserting DSACK0 and negating DSACK1 to indicate an 8-bit port. The MC68341 then
reads the operand byte from bits 15–8 and ignores bits 7–0.

For a write operation, the MC68341 drives the single-byte operand on both bytes of the
data bus because it does not know the port size until the DSACK≈ signals are read. The
slave device reads the byte operand from bits 15–8 and places the operand in the
specified location. The slave then asserts DSACK0 to terminate the bus cycle.

3.3.3.2 BYTE OPERAND TO 16-BIT PORT, EVEN (A0 = 0) . The MC68341 drives the
address bus with the desired address and the SIZx pins to indicate a single-byte operand.

BYTE OPERAND

OP0

7

0

DATA BUS

CYCLE 1

OP0

(OP0)

D0D8D15 D7

0100X

DSACK0DSACK1A0SIZ0SIZ1

For a read operation, the slave responds by placing data on bits 15–8 of the data bus and
asserting DSACK1 to indicate a 16-bit port. The MC68341 then reads the operand byte
from bits 15–8 and ignores bits 7–0.

For a write operation, the MC68341 drives the single-byte operand on both bytes of the
data bus because it does not know the port size until the DSACK≈ signals are read. The
slave device reads the operand from bits 15–8 of the data bus and uses the address to
place the operand in the specified location. The slave then asserts DSACK1 to terminate
the bus cycle.

3-10 MC68341 USER’S MANUAL MOTOROLA

3.3.3.3 BYTE OPERAND TO 16-BIT PORT, ODD (A0 = 1). The MC68341 drives the
address bus with the desired address and the SIZx pins to indicate a single-byte operand.

BYTE OPERAND

DATA BUS

CYCLE 1

(OP0) OP0

OP0

7

0

D0D8D15 D7

0110X

DSACK0DSACK1A0SIZ0SIZ1

For a read operation, the slave responds by placing data on bits 7–0 of the data bus and
asserting DSACK1 to indicate a 16-bit port. The MC68341 then reads the operand byte
from bits 7–0 and ignores bits 15–8.

For a write operation, the MC68341 drives the single-byte operand on both bytes of the
data bus because it does not know the port size until the DSACK≈ signals are read. The
slave device reads the operand from bits 7–0 of the data bus and uses the address to
place the operand in the specified location. The slave then asserts DSACK1 to terminate
the bus cycle.

3.3.3.4 WORD OPERAND TO 8-BIT PORT, ALIGNED. The MC68341 drives the address
bus with the desired address and the SIZx pins to indicate a word operand.

WORD OPERAND

OP0 OP1

15 7 0

8

DATA BUS

CYCLE 1
CYCLE 2

OP0
OP1

(OP1)
(OP1)

D0D8D15 D7

10010
01110

DSACK0DSACK1A0SIZ0SIZ1

For a read operation, the slave responds by placing the most significant byte of the
operand on bits 15–8 of the data bus and asserting DSACK0 to indicate an 8-bit port. The
MC68341 reads the most significant byte of the operand from bits 15–8 and ignores bits
7–0. The MC68341 then decrements the transfer size counter, increments the address,
and reads the least significant byte of the operand from bits 15–8 of the data bus.

For a write operation, the MC68341 drives the word operand on bits 15–0 of the data bus.
The slave device then reads the most significant byte of the operand from bits 15–8 of the
data bus and asserts DSACK0 to indicate that it received the data but is an 8-bit port. The
MC68341 then decrements the transfer size counter, increments the address, and writes
the least significant byte of the operand to bits 15–8 of the data bus.

MOTOROLA MC68341 USER’S MANUAL 3-11

3.3.3.5 WORD OPERAND TO 16-BIT PORT, ALIGNED. The MC68341 drives the
address bus with the desired address and the size pins to indicate a word operand.

WORD OPERAND

DATA BUS

CYCLE 1

OP0 OP1

15 0

D0D8D15 D7

OP0 OP1

DSACK0DSACK1A0SIZ0SIZ1

1000X

For a read operation, the slave responds by placing the data on bits 15–0 of the data bus
and asserting DSACK1 to indicate a 16-bit port. When DSACK1 is asserted, the MC68341
reads the data on the data bus and terminates the cycle.

For a write operation, the MC68341 drives the word operand on bits 15–0 of the data bus.
The slave device then reads the entire operand from bits 15–0 of the data bus and asserts
DSACK1 to terminate the bus cycle.

3.3.3.6 LONG-WORD OPERAND TO 8-BIT PORT, ALIGNED. The MC68341 drives the
address bus with the desired address and the SIZx pins to indicate a long-word operand.

LONG-WORD OPERAND

DATA BUS

CYCLE 1
CYCLE 2
CYCLE 3
CYCLE 4

OP0

31 23 15 7

D15

OP0
OP1
OP2
OP3

D8

D7

OP1

(OP1)
(OP1)
(OP3)
(OP3)

OP2 OP3

0

DSACK0DSACK1A0SIZ0SIZ1D0
00010
11110
10010
01110

For a read operation, shown in Figure 3-3, the slave responds by placing the most
significant byte of the operand on bits 15–8 of the data bus and asserting DSACK0 to
indicate an 8-bit port. The MC68341 reads the most significant byte of the operand (byte

0) from bits 15–8 and ignores bits 7–0. The MC68341 then decrements the transfer size
counter, increments the address, initiates a new cycle, and reads byte 1 of the operand
from bits 15–8 of the data bus. The MC68341 repeats the process of decrementing the
transfer size counter, incrementing the address, initiating a new cycle, and reading a byte
to transfer the remaining two bytes.

For a write operation, shown in Figure 3-4, the MC68341 drives the two most significant
bytes of the operand on bits 15–0 of the data bus. The slave device then reads only the
most significant byte of the operand (byte 0) from bits 15–8 of the data bus and asserts
DSACK0 to indicate reception and an 8-bit port. The MC68341 then decrements the
transfer size counter, increments the address, and writes byte 1 of the operand to bits
15–8 of the data bus. The MC68341 continues to decrement the transfer size counter,
increment the address, and write a byte to transfer the remaining two bytes to the slave
device.

3-12 MC68341 USER’S MANUAL MOTOROLA

S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4

CLKOUT

A31–A0

FC3–FC0

R/W

AS

DS

SIZ0

4 BYTES 3 BYTES 2 BYTES 1 BYTE

SIZ1

DSACK0

DSACK1

D15–D8

OP0

OP1

OP2

OP3

D7–D0

BYTE
READ

BYTE

READ

BYTE
READ

BYTE
READ

LONG-WORD OPERAND READ FROM 8-BIT BUS

Figure 3-3. Long-Word Operand Read Timing from 8-Bit Port

MOTOROLA MC68341 USER’S MANUAL 3-13

CLKOUT

A31–A0

FC3–FC0

R/W

AS

DS

SIZ0

SIZ1

DSACK0

DSACK1

S0

S2 S4

4 BYTES

S0 S2 S4 S0 S2 S4 S0 S2 S4

3 BYTES

2 BYTES

1 BYTE

D15–D8

D7–D0

OP0

(OP1)

WRITE WRITE WRITE WRITE

LONG-WORD OPERAND WRITE TO 8-BIT BUS

OP1

(OP1)

OP2 OP3

(OP3) (OP3)

Figure 3-4. Long-Word Operand Write Timing to 8-Bit Port

3.3.3.7 LONG-WORD OPERAND TO 16-BIT PORT, ALIGNED . Figure 3-5 shows both

long-word and word read and write timing to a 16-bit port.

LONG-WORD OPERAND

DATA BUS

CYCLE 1
CYCLE 2

31 23 15 7 0

OP0 OP1
OP2

OP1OP0 OP2 OP3

D0D8D15 D7

0000X

OP3

1000X

DSACK0DSACK1A0SIZ0SIZ1

3-14 MC68341 USER’S MANUAL MOTOROLA

CLKOUT

A31–A0

FC3–FC0

R/W

AS

DS

SIZ0

SIZ1

DSACK0

DSACK1

S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2

4 BYTES

2 BYTES

2 BYTES

4 BYTES

2 BYTES 2 BYTES

S4

D15–D8

D7–D0

OP0

OP1

LONG WORD READ

FROM 16-BIT BUS

OP2

OP3

OP0

OP1

WORD READ

FROM 16-BIT BUS

OP0

OP1

LONG WORD WRITE TO

16-BIT BUS

OP2

OP0

OP1OP3

WORD
WRITE TO
16-BIT BUS

Figure 3-5. Long-Word and Word Read and Write Timing—16-Bit Port

The MC68341 drives the address bus with the desired address and drives the SIZx pins to
indicate a long-word operand. For a read operation, the slave responds by placing the two
most significant bytes of the operand on bits 15–0 of the data bus and asserting DSACK1
to indicate a 16-bit port. The MC68341 reads the two most significant bytes of the operand
(bytes 0 and 1) from bits 15–0. The MC68341 then decrements the transfer size counter
by 2, increments the address by 2, initiates a new cycle, and reads bytes 2 and 3 of the
operand from bits 15–0 of the data bus.

For a write operation, the MC68341 drives the two most significant bytes of the operand
on bits 15–0 of the data bus. The slave device then reads the two most significant bytes of
the operand (bytes 0 and 1) from bits 15–0 of the data bus and asserts DSACK1 to
indicate reception and a 16-bit port. The MC68341 then decrements the transfer size
counter by 2, increments the address by 2, and writes bytes 2 and 3 of the operand to bits
15–0 of the data bus.

MOTOROLA MC68341 USER’S MANUAL 3-15

3.3.4 Bus Operation

DSACK¯

The MC68341 bus is asynchronous, allowing external devices connected to the bus to
operate at clock frequencies different from the clock for the MC68341. Bus operation uses
the handshake lines (AS, DS, DSACK1/DSACK0 , BERR , and HALT) to control data
transfers. AS signals a valid address on the address bus, and DS is used as a condition
for valid data on a write cycle. Decoding the SIZx outputs and lower address line A0
provides strobes that select the active portion of the data bus. The slave device (memory
or peripheral) responds by placing the requested data on the correct portion of the data
bus for a read cycle or by latching the data on a write cycle; the slave asserts the
DSACK1/ DSACK0 combination that corresponds to the port size to terminate the cycle.
Alternatively, the can be programmed to assert the DSACK1/ DSACK0 combination
internally and respond for the slave. If no slave responds or the access is invalid, external
control logic may assert BERR to abort the bus cycle or BERR with HALT to retry the bus
cycle.

DSACK≈ can be asserted before the data from a slave device is valid on a read cycle. The
length of time that DSACK≈ may precede data must not exceed a specified value in any
asynchronous system to ensure that valid data is latched into the MC68341. (See
Section 12 Electrical Characteristics for timing parameters.) Note that no maximum
time is specified from the assertion of AS to the assertion of DSACK≈ . Although the
MC68341 can transfer data in a minimum of three clock cycles when the cycle is
terminated with DSACK≈, the MC68341 inserts wait cycles in clock-period increments until

DSACK≈ is recognized. BERR and/or HALT can be asserted after DSACK≈ is asserted.
BERR and or HALT must be asserted within the time specified after DSACK≈

in any asynchronous system. If this maximum delay time is violated, the MC68341 may
exhibit erratic behavior.

is asserted

3.3.5 Synchronous Operation with

Although cycles terminated with DSACK≈ are classified as asynchronous, cycles
terminated with DSACK≈ can also operate synchronously in that signals are interpreted
relative to clock edges. The devices that use these cycles must synchronize the response
to the MC68341 clock (CLKOUT) to be synchronous. Since the devices terminate bus
cycles with DSACK≈ , the dynamic bus sizing capabilities of the MC68341 are available.
The minimum cycle time for these cycles is also three clocks. To support systems that use
the system clock to generate DSACK≈ and other asynchronous inputs, the asynchronous
input setup time and the asynchronous input hold time are given. If the setup and hold
times are met for the assertion or negation of a signal such as DSACK≈, the MC68341 is
guaranteed to recognize that signal level on that specific falling edge of the system clock.
If the assertion of DSACK≈ is recognized on a particular falling edge of the clock, valid
data is latched into the MC68341 (for a read cycle) on the next falling clock edge if the
data meets the data setup time. In this case, the parameter for asynchronous operation
can be ignored. The timing parameters are described in Section 12 Electrical
Characteristics.

If a system asserts DSACK≈ for the required window around the falling edge of S2 and
obeys the proper bus protocol by maintaining DSACK≈ (and/or BERR/HALT) until and

3-16 MC68341 USER’S MANUAL MOTOROLA

throughout the clock edge that negates AS (with the appropriate asynchronous input hold
time), no wait states are inserted. The bus cycle runs at its maximum speed for bus cycles
terminated with DSACK≈ (three clocks per cycle). When BERR (or BERR and HALT

) is

asserted after DSACK≈ , BERR (and HALT) must meet the appropriate setup time prior to
the falling clock edge one clock cycle after DSACK≈ is recognized. This setup time is
critical, and the MC68341 may exhibit erratic behavior if it is violated. When operating
synchronously, the data-in setup and hold times for synchronous cycles may be used
instead of the timing requirements for data relative to DS.

3.3.6 Fast Termination Cycles

With an external device that has a fast access time, the fast termination capability of the
chip select circuit can provide a two-clock external bus transfer. Since the chip select
circuits are driven from the system clock, the bus cycle termination is inherently
synchronized with the system clock. Refer to Section 4 System Integration Module for
more information on chip selects. Fast termination can only be used for M68300 bus
cycles. To use the fast termination option, an external device should be fast enough to
have data ready, within the specified setup time, by the falling edge of S4. Figure 3-6
shows the DSACK≈ timing for a read with two wait states, followed by a fast termination
read and write. When using the fast termination option, DS
cycle, not in a write cycle.

is asserted only in a read

CLKOUT

AS

DS

UWE, LWE

R/W

DSACKx

D15–D0

DTC

S0 S2 SW SW S4 S0 S4 S0 S4 S0

S1 S3 S5 S1 S5 S1 S5SW*SW

TWO WAIT STATES IN READ

*

FAST

TERMINATION

READ

FAST

TERMINATION

WRITE

* DSACKx only internally asserted for fast termination cycles.

Figure 3-6. Fast Termination Timing

MOTOROLA MC68341 USER’S MANUAL 3-17

3.4 DATA TRANSFER CYCLES

The transfer of data between the MC68341 and other devices involves the following
signals:

• Address Bus A31–A0

• Data Bus D15–D0

• Control Signals

The address bus and data bus are parallel, nonmultiplexed buses. The bus master moves
data on the bus by issuing control signals, and the bus uses a handshake protocol to
ensure correct movement of the data. In all bus cycles, the bus master is responsible for
de-skewing all signals it issues at both the start and end of the cycle. In addition, the bus
master is responsible for de-skewing the acknowledge and data signals from the slave
devices. The following paragraphs define read, write, and read-modify-write cycle
operations. Each bus cycle is defined as a succession of states that apply to the bus
operation. These states are different from the MC68341 states described for the CPU32.
The clock cycles used in the descriptions and timing diagrams of data transfer cycles are
independent of the clock frequency. Bus operations are described in terms of external bus
states.

3.4.1 M68300 Read Cycle

During a read cycle, the MC68341 receives data from a memory or peripheral device. If
the instruction specifies a long-word or word operation, the MC68341 attempts to read two
bytes at once. For a byte operation, the MC68341 reads one byte. The section of the data
bus from which each byte is read depends on the operand size, address signal A0, and
the port size. Refer to 3.3.1 Dynamic Bus Sizing and 3.3.2 Misaligned Operands for
more information. Figure 3-7 is a flowchart of a word read cycle. Figure 3-8 is an example
of a functional timing diagram of a read bus cycle specified in terms of clock periods.

3-18 MC68341 USER’S MANUAL MOTOROLA

BUS MASTER

ADDRESS DEVICE

1. SET R/W TO READ

2. DRIVE ADDRESS ON A31–A0

3. DRIVE FUNCTION CODE ON FC3–FC0

4. DRIVE SIZE PINS FOR OPERAND SIZE

5. ASSERT AS AND DS

ACQUIRE DATA

1. LATCH DATA

2. NEGATE AS AND DS

START NEXT CYCLE

1. DECODE ADDRESS

2. PLACE DATA ON D15–D0

3. DRIVE DSACKx SIGNALS

1. REMOVE DATA FROM D15–D0

2. NEGATE DSACKx

SLAVE

PRESENT DATA

TERMINATE CYCLE

Figure 3-7. Word Read Cycle Flowchart

State 0—The read cycle starts in state 0 (S0). During S0, the MC68341 places a valid
address on A31–A0 and valid function codes on FC3–FC0. The function codes select the
address space for the cycle. The MC68341 drives R/ W high for a read cycle. SIZ1/SIZ0
become valid, indicating the number of bytes requested for transfer.

State 1—One-half clock later, in state 1 (S1), the MC68341 asserts AS indicating a valid
address on the address bus. The MC68341 also asserts DS during S1. The selected
device uses R/W, SIZ1 or SIZ0, A0, and DS to place its information on the data bus. One
or both of the bytes (D15–D8 and D7–D0) are selected by SIZ1/SIZ0 and A0.

State 2—As long as at least one of the DSACK≈ signals is recognized on the falling edge
of S2 (meeting the asynchronous input setup time requirement), data is latched on the
falling edge of S4, and the cycle terminates.

State 3—If DSACK≈ is not recognized by the start of state 3 (S3), the MC68341 inserts
wait states instead of proceeding to states 4 and 5. To ensure that wait states are
inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous
input setup and hold times around the end of S2. If wait states are added, the MC68341
continues to sample DSACK≈ on the falling edges of the clock until one is recognized.

State 4—DTC asserts during S4 to indicate the end of the current bus cycle. At the falling
edge of state 4 (S4), the MC68341 latches the incoming data and samples DSACK≈ to get
the port size.

State 5—The MC68341 negates AS and DS during state 5 (S5), and negates DTC after
the rising edge of S5. It holds the address valid during S5 to provide address hold time for
memory systems. R/W, SIZ1 and SIZ0, and FC3–FC0 also remain valid throughout S5.
The external device keeps its data and DSACK≈ signals asserted until it detects the
negation of AS or DS (whichever it detects first). The device must remove its data and

MOTOROLA MC68341 USER’S MANUAL 3-19

negate DSACK≈ within approximately one clock period after sensing the negation of AS or
DS. DSACK≈ signals that remain asserted beyond this limit may be prematurely detected
for the next bus cycle.

S0 S2 S4 S0

CLKOUT

A31–A2

A1

A0

FC3–FC0

SIZ1

WORD

SIZ0

R/W

AS

CSx

S2

BYTE

S4

S0 S2 S4

DS

AS68K

UDS, LDS

UWE, LWE

DSACK

DTC

D15–D8

D7–D0

OP2

OP3

WORD READ

BYTE READ

Figure 3-8. Read Cycle Timing

OP3

OP3

BYTE READ

3-20 MC68341 USER’S MANUAL MOTOROLA

3.4.2 68000 Read Cycle

During a 68000 read cycle, the 68000 strobes AS68K, UDS , and LDS are asserted instead
of AS and DS, with timing compatible with MC68000 bus cycles. Although the dynamic
bus sizing capability of the MC68341 allows assertion of either DSACK1 or DSACK0 to
terminate the bus cycle as a 16-bit or 8-bit access, UDS and LDS will always assert for a
16-bit bus. UDS and LDS must be combined into a single data strobe externally when
used with an 8-bit 68000 bus. Figure 3-9 is a flowchart of a 68000 word read cycle. Figure
3-10 is an example of a functional timing diagram of a 68000 read bus cycle specified in
terms of clock periods.

BUS MASTER

ADDRESS DEVICE

1. SET R/W TO READ

2. DRIVE ADDRESS ON A31–A0

3. DRIVE FUNCTION CODE ON FC3–FC0

4. DRIVE SIZE PINS FOR OPERAND SIZE

5. ASSERT AS68K AND UDS, LDS

ACQUIRE DATA

1. LATCH DATA

2. NEGATE AS68K AND UDS, LDS

START NEXT CYCLE

1. DECODE ADDRESS

2. PLACE DATA ON D15–D0

3. DRIVE DSACKx SIGNALS

1. REMOVE DATA FROM D15–D0

2. NEGATE DSACKx

SLAVE

PRESENT DATA

TERMINATE CYCLE

Figure 3-9. 68000 Word Read Cycle Flowchart

State 0—The read cycle starts in state 0 (S0). During S0, the MC68341 places a valid
address on A31–A0 and valid function codes on FC3–FC0. The function codes select the
address space for the cycle. The MC68341 drives R/ W high for a read cycle. SIZ1/SIZ0
become valid, indicating the number of bytes requested for transfer.

State 1—The MC68341 issues no new control signals during S1.
State 2—In state 2 (S2), the MC68341 asserts AS68K indicating a valid address on the

address bus. The MC68341 also asserts UDS/LDS during S2. The selected device uses
R/W, UDS , and LDS to place its information on the data bus. The upper byte (D15–D8)
and lower byte (D7–D0) are selected by assertion of UDS and LDS , respectively. If
DSACK≈ is recognized on the falling edge of S2 (meeting the asynchronous input setup
time requirement), data is latched on the falling edge of S4, and the cycle terminates as a
three clock bus cycle.

State 3—If DSACK≈ is not recognized by the start of state 3 (S3), the MC68341 inserts
wait states instead of proceeding to states 4 and 5. To ensure that wait states are
inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous

MOTOROLA MC68341 USER’S MANUAL 3-21

input setup and hold times around the end of S2. If wait states are added, the MC68341
continues to sample DSACK≈ on the falling edges of the clock until one is recognized.

State 4—DTC asserts during S4 to indicate the end of the current bus cycle. At the falling
edge of state 4 (S4), the MC68341 latches the incoming data and samples DSACK≈ to get
the port size.

State 5—The MC68341 negates AS68K and UDS/LDS during state 5 (S5), and negates
DTC after the rising edge of S5. It holds the address valid during S5 to provide address
hold time for memory systems. R/W, SIZ1 and SIZ0, and FC3–FC0 also remain valid
throughout S5. The external device keeps its data and DSACK≈ signals asserted until it
detects the negation of AS68K or UDS/LDS (whichever it detects first). The device must
remove its data and negate DSACK≈

within approximately one clock period after sensing

the negation of AS68K or UDS/LDS . DSACK≈ signals that remain asserted beyond this
limit may be prematurely detected for the next bus cycle.

3-22 MC68341 USER’S MANUAL MOTOROLA

S2

CLKOUT

A31–A2

FC3–FC0

SIZ1

SIZ0

A1

A0

S0 S2 S4 S0

WORD

BYTE

S4

S0 S2 S4

R/W

CSx

DSACK1

DSACK0

D31–D24

D23–D16

D15–D8

D7–D0

AS

DS

WORD READ

OP2

OP3

BYTE READ

OP3

OP3

BYTE READ

Figure 3-10. 68000 Read Cycle Timing

3.4.3 M68300 Write Cycle

During a write cycle, the MC68341 transfers data to memory or a peripheral device. Figure
3-11 is a flowchart of a word write cycle. Figure 3-12 is an example of a functional timing
diagram of a write bus cycle specified in terms of clock periods.

MOTOROLA MC68341 USER’S MANUAL 3-23

BUS MASTER SLAVE

ADDRESS DEVICE

1. SET R/W TO WRITE

2. DRIVE ADDRESS ON A31–A0

3. DRIVE FUNCTION CODE ON FC3–FC0

4. DRIVE SIZE PINS FOR OPERAND SIZE

5. ASSERT AS

6. PLACE DATA ON D15–D0

7. ASSERT DS AND UWE/LWE

TERMINATE OUTPUT TRANSFER

1. NEGATE AS, DS, AND UWE/LWE

2. REMOVE DATA FROM D15–D0

START NEXT CYCLE

1. DECODE ADDRESS

2. LATCH DATA FROM D15–D0

3. ASSERT DSACKx SIGNALS

1. NEGATE DSACKx

ACCEPT DATA

TERMINATE CYCLE

Figure 3-11 Word Write Cycle Flowchart

State 0—The write cycle starts in S0. During S0, the MC68341 places a valid address on
A31–A0 and valid function codes on FC3–FC0. The function codes select the address
space for the cycle. The MC68341 drives R/W low for a write cycle. SIZ1/SIZ0 become
valid, indicating the number of bytes to be transferred.

State 1—One-half clock later during S1, the MC68341 asserts AS

, indicating a valid

address on the address bus.
State 2—During S2, the MC68341 places the data to be written onto D15–D0, and

samples DSACK≈ at the end of S2.
State 3—The MC68341 asserts DS during S3, indicating that data is stable on the data

bus. Write enable strobes UWE and LWE for the active bytes of the data bus are also
asserted during S3. As long as at least one of the DSACK≈ signals is recognized by the
end of S2 (meeting the asynchronous input setup time requirement), the cycle terminates
one clock later. If DSACK≈ is not recognized by the start of S3, the MC68341 inserts wait
states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both
DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup
and hold times around the end of S2. If wait states are added, the MC68341 continues to
sample DSACK≈ on the falling edges of the clock until one is recognized. The selected
device uses R/W, SIZ1/SIZ0, and A0 to latch data from the appropriate byte(s) of D15–D8
and D7–D0. SIZ1/SIZ0 and A0 select the bytes of the data bus. If it has not already done
so, the device asserts DSACK≈ to signal that it has successfully stored the data.

State 4—DTC asserts during S4 to indicate the end of the current bus cycle.
State 5—The MC68341 negates AS and DS during S5, and negates DTC after the rising

edge of S5. It holds the address and data valid during S5 to provide address hold time for
memory systems. R/W, SIZ1/SIZ0, and FC3–FC0 also remain valid throughout S5. The

3-24 MC68341 USER’S MANUAL MOTOROLA

external device must keep DSACK≈ asserted until it detects the negation of AS or DS
(whichever it detects first). The device must negate DSACK≈ within approximately one
clock period after sensing the negation of AS or DS. DSACK≈ signals that remain asserted
beyond this limit may be prematurely detected for the next bus cycle.

S0 S2 S4 S0

CLKOUT

A31–A2

A1

A0

FC3–FC0

SIZ1

WORD

SIZ0

R/W

AS

CSx

S2

BYTE

S4

S0 S2 S4

DS

AS68K

UDS, LDS

UWE

LWE

DSACK

DTC

D15–D8

D7–D0

WORD WRITE

OP2

OP3

BYTE WRITE

OP3

Figure 3-12. M68300 Write Cycle Timing

OP3

BYTE WRITE

MOTOROLA MC68341 USER’S MANUAL 3-25

3.4.4 68000 Write Cycle

During a 68000 write cycle, the 68000 strobes AS68K , UDS, and LDS are asserted
instead of AS and DS, with timing compatible with MC68000 bus cycles. Although the
dynamic bus sizing capability of the MC68341 allows assertion of either DSACK1 or
DSACK0 to terminate the bus cycle as a 16-bit or 8-bit access, UDS and LDS will always
assert for a 16-bit bus. UDS and LDS must be combined into a single data strobe
externally when used with an 8-bit 68000 bus. Figure 3-13 is a flowchart of a 68000 word
write cycle. Figure 3-14 is an example of a functional timing diagram of a 68000 write bus
cycle specified in terms of clock periods.

BUS MASTER SLAVE

ADDRESS DEVICE

1. SET R/W TO WRITE

2. DRIVE ADDRESS ON A31–A0

3. DRIVE FUNCTION CODE ON FC3–FC0

4. DRIVE SIZE PINS FOR OPERAND SIZE

5. ASSERT AS68K

6. PLACE DATA ON D15–D0

7. ASSERT UDS/LDS AND UWE/LWE

TERMINATE OUTPUT TRANSFER

1. DECODE ADDRESS

2. LATCH DATA FROM D15–D0

3. ASSERT DSACKx SIGNALS

ACCEPT DATA

1. NEGATE AS68K, UDS/LDS AND UWE/LWE

2. REMOVE DATA FROM D15–D0

1. NEGATE DSACKx

START NEXT CYCLE

TERMINATE CYCLE

Figure 3-13. 68000 Word Write Cycle Flowchart

State 0—The write cycle starts in S0. During S0, the MC68341 places a valid address on
A31–A0 and valid function codes on FC3–FC0. The function codes select the address
space for the cycle. The MC68341 drives R/W low for a write cycle. SIZ1/SIZ0 become
valid, indicating the number of bytes to be transferred.

State 1—The MC68341 issues no new control signals during S1.
State 2—In S2, the MC68341 asserts AS68K indicating a valid address on the address

bus. During S2, the MC68341 places the data to be written onto D15–D0, and samples
DSACK≈ at the end of S2.

State 3—The MC68341 asserts UDS /LDS after the rising edge of S3, indicating that data
is stable on the data bus. Write enable strobes UWE and LWE for the active bytes of the
data bus are also asserted after the rising edge of S3. As long as DSACK≈ is recognized
by the end of S2 (meeting the asynchronous input setup time requirement), the cycle
terminates one clock later. If DSACK≈ is not recognized by the start of S3, the MC68341
inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are

3-26 MC68341 USER’S MANUAL MOTOROLA

inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous
input setup and hold times around the end of S2. If wait states are added, the MC68341
continues to sample DSACK≈ on the falling edges of the clock until one is recognized. The
selected device uses R/ W, UDS , and LDS (or UWE and LWE) to latch data from the
appropriate byte(s) of D15–D8 and D7–D0. If it has not already done so, the device
asserts DSACK≈ to signal that it has successfully stored the data.

State 4—DTC asserts during S4 to indicate the end of the current bus cycle.
State 5—The MC68341 negates AS68K and UDS/LDS during S5, and negates DTC after

the rising edge of S5. It holds the address and data valid during S5 to provide address
hold time for memory systems. R/W, SIZ1/SIZ0, and FC3–FC0 also remain valid
throughout S5. The external device must keep DSACK≈ asserted until it detects the
negation of AS68K or UDS/LDS (whichever it detects first). The device must negate

DSACK≈ within approximately one clock period after sensing the negation of AS68K or
UDS/LDS . DSACK≈ signals that remain asserted beyond this limit may be prematurely

detected for the next bus cycle.

MOTOROLA MC68341 USER’S MANUAL 3-27

S0 S2 S4 S0

S2

S4

S0 S2 S4

CLKOUT

A31–A2

A1

A0

FC3–FC0

SIZ1

WORD

BYTE

SIZ0

R/W

AS68K

CSx

DS

AS

UDS

LDS

UWE

LWE

DSACK

DTC

D15–D8

D7–D0

WORD WRITE

OP2

OP3

BYTE WRITE

OP3

OP3

BYTE WRITE

Figure 3-14. 68000 Write Cycle Timing

3-28 MC68341 USER’S MANUAL MOTOROLA

3.4.5 Read-Modify-Write Cycle

The read-modify-write cycle performs a read, conditionally modifies the data in the
arithmetic logic unit, and may write the data out to memory. In the MC68341, this
operation is indivisible, providing semaphore capabilities for multiprocessor systems.
During the entire read-modify-write sequence, the MC68341 asserts RMC to indicate that
an indivisible operation is occurring. The MC68341 does not issue a BG signal in
response to a BR signal during this operation. Figure 3-15 is an example of a functional
timing diagram of an M68300 read-modify-write instruction specified in terms of clock
periods.

S0 S2 S4 S2 S4 S0

CLK

OUT

A31–A30

FC3–FC0

SIZ1–SIZ0

R/W

RMC

AS

DS

DSACKx

D15–D0

S0

READ

INDIVISIBLE

CYCLE

WRITE

Figure 3-15. Read-Modify-Write Cycle Timing

State 0—The MC68341 asserts RMC in S0 to identify a read-modify-write cycle. The
MC68341 places a valid address on A31–A0 and valid function codes on FC3–FC0. The
function codes select the address space for the operation. SIZ1/SIZ0 become valid in S0
to indicate the operand size. The MC68341 drives R/W high for the read cycle.

State 1—One-half clock later during S1, the MC68341 asserts AS indicating a valid
address on the address bus. The MC68341 also asserts DS during S1.

MOTOROLA MC68341 USER’S MANUAL 3-29

State 2—The selected device uses R/ W, SIZ1/SIZ0, A0, and DS to place information on
the data bus. Either or both of the bytes (D15–D8 and D7–D0) are selected by SIZ1/SIZ0
and A0. Concurrently, the selected device may assert DSACK≈.

State 3—As long as at least one of the DSACK≈ signals is recognized by the end of S2
(meeting the asynchronous input setup time requirement), data is latched on the next
falling edge of the clock, and the cycle terminates. If DSACK≈ is not recognized by the
start of S3, the MC68341 inserts wait states instead of proceeding to S4 and S5. To
ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated
throughout the asynchronous input setup and hold times around the end of S2. If wait
states are added, the MC68341 continues to sample the DSACK≈ signals on the falling
edges of the clock until one is recognized.

State 4—At the end of S4, the MC68341 latches the incoming data.
State 5—The MC68341 negates AS and DS during S5. If more than one read cycle is

required to read in the operand(s), S0–S5 are repeated for each read cycle. When
finished reading, the MC68341 holds the address, R/W, and FC3–FC0 valid in preparation
for the write portion of the cycle. The external device keeps its data and DSACK≈ signals
asserted until it detects the negation of AS or DS (whichever it detects first). The device
must remove the data and negate DSACK≈ within approximately one clock period after
sensing the negation of AS or DS. DSACK≈ signals that remain asserted beyond this limit
may be prematurely detected for the next portion of the operation.

Idle States—The MC68341 does not assert any new control signals during the idle states,
but it may internally begin the modify portion of the cycle at this time. S0–S5 are omitted if
no write cycle is required. If a write cycle is required, R/W remains in the read mode until
S0 to prevent bus conflicts with the preceding read portion of the cycle; the data bus is not
driven until S2.

State 0—The MC68341 drives R/W low for a write cycle. Depending on the write operation
to be performed, the address lines may change during S0.

State 1—In S1, the MC68341 asserts AS, indicating a valid address on the address bus.
State 2—During S2, the MC68341 places the data to be written onto D15–D0.
State 3—The MC68341 asserts DS during S3, indicating stable data on the data bus. As

long as at least one of the DSACK≈ signals is recognized by the end of S2 (meeting the
asynchronous input setup time requirement), the cycle terminates one clock later. If
DSACK≈ is not recognized by the start of S3, the MC68341 inserts wait states instead of
proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and
DSACK0 must remain negated throughout the asynchronous input setup and hold times
around the end of S2. If wait states are added, the MC68341 continues to sample
DSACK≈ on the falling edges of the clock until one is recognized. The selected device
uses R/W, DS, SIZ1/SIZ0, and A0 to latch data from the appropriate section(s) of D15–D8
and D7–D0. SIZ1/SIZ0 and A0 select the data bus sections. If it has not already done so,
the device asserts DSACK≈ when it has successfully stored the data.

3-30 MC68341 USER’S MANUAL MOTOROLA

State 4—The MC68341 issues no new control signals during S4.
State 5—The MC68341 negates AS and DS during S5. It holds the address and data valid

during S5 to provide address hold time for memory systems. R/W and FC3–FC0 also
remain valid throughout S5. If more than one write cycle is required, states S0–S5 are
repeated for each write cycle. The external device keeps DSACK≈ asserted until it detects
the negation of AS or DS (whichever it detects first). The device must remove its data and
negate DSACK≈ within approximately one clock period after sensing the negation of AS or
DS.

3.5 CPU SPACE CYCLES

FC3–FC0 select user and supervisor program and data areas. The area selected by FC3–
FC0 = $7 is classified as the CPU space. The breakpoint acknowledge, LPSTOP
broadcast, module base address register access, and interrupt acknowledge cycles
described in the following paragraphs use CPU space. The CPU space type, which is
encoded on A19–A16 during a CPU space operation, indicates the function that the
MC68341 is performing. On the MC68341, four of the encodings are implemented as
shown in Figure 3-16. All unused values are reserved by Motorola for additional CPU
space types.

CPU SPACE CYCLES

FUNCTION

CODE

BREAKPOINT

ACKNOWLEDGE

LOW-POWER

STOP BROADCAST

MODULE BASE

ADDRESS

REGISTER ACCESS

INTERRUPT

ACKNOWLEDGE

3
0

3

0

3

0

3

0

111

111

11 1

111

31

0

00000000

0

31

00000000

31

0

00000000

31

0

ADDRESS BUS

19 16

0000000000000000000 T0BKPT#

19 16 0

0

00000

000000111111111100000000

111111111111

111111111111111110

19

16

19 16

1111111111111111 1

CPU SPACE
TYPE FIELD

LEVEL

0

0

0

Figure 3-16. CPU Space Address Encoding

3.5.1 Breakpoint Acknowledge Cycle

The breakpoint acknowledge cycle allows external hardware to insert an instruction
directly into the instruction pipeline as the program executes. The breakpoint acknowledge
cycle is generated by the execution of a breakpoint instruction (BKPT) or the assertion of
the BKPT pin. The T-bit state (shown in Figure 3-16) differentiates a software breakpoint
cycle (T = 0) from a hardware breakpoint cycle (T = 1).

MOTOROLA MC68341 USER’S MANUAL 3-31

When a BKPT instruction is executed (software breakpoint), the MC68341 performs a
word read from CPU space, type 0, at an address corresponding to the breakpoint number
(bits [2–0] of the BKPT opcode) on A4–A2, and the T-bit (A1) is cleared. If this bus cycle is
terminated with BERR (i.e., no instruction word is available), the MC68341 then performs
illegal instruction exception processing. If the bus cycle is terminated by DSACK≈, the
MC68341 uses the data on D15–D0 (for 16-bit ports) or two reads from D15–D8 (for 8-bit
ports) to replace the BKPT instruction in the internal instruction pipeline and then begins
execution of that instruction.

When the CPU32 acknowledges a BKPT pin assertion (hardware breakpoint) with
background mode disabled, the CPU32 performs a word read from CPU space, type 0, at
an address corresponding to all ones on A4–A2 (BKPT#7), and the T-bit (A1) is set. If this
bus cycle is terminated by BERR , the MC68341 performs hardware breakpoint exception
processing. If this bus cycle is terminated by DSACK≈ , the MC68341 ignores data on the
data bus and continues execution of the next instruction.

NOTE

The BKPT pin is sampled on the same clock phase as data
and is latched with data as it enters the CPU32 pipeline. If
BKPT is asserted for only one bus cycle and a pipeline flush
occurs before BKPT is detected by the CPU32, BKPT is
ignored. To ensure detection of BKPT by the CPU32, BKPT
can be asserted until a breakpoint acknowledge cycle is
recognized.

The breakpoint operation flowchart is shown in Figure 3-17. Figures 3-18 and 3-19 show
the timing diagrams for the breakpoint acknowledge cycle with instruction opcodes
supplied on the cycle and with an exception signaled, respectively.

3.5.2 LPSTOP Broadcast Cycle

The low power stop (LPSTOP) broadcast cycle is generated by the CPU32 executing the
LPSTOP instruction. Since the external bus interface must get a copy of the interrupt
mask level from the CPU32, the CPU32 performs a CPU space type 3 write with the mask
level encoded on the data bus, as shown in the following figure. The CPU space type 3
cycle waits for the bus to be available, and is shown externally to indicate to external
devices that the MC68341 is going into LPSTOP mode. If an external device requires
additional time to prepare for entry into LPSTOP mode, entry can be delayed by asserting
HALT. The SIM41 provides internal DSACK≈ response to this cycle. For more information
on how the SIM41 responds to LPSTOP mode, see Section 4 System Integration
Module.

1514131211109876543210
—————————————I2 I1 I0

I2–I0—Interrupt Mask Level

The interrupt mask level is encoded on bits 2–0 of the data bus during an LPSTOP
broadcast.

3-32 MC68341 USER’S MANUAL MOTOROLA

BREAKPOINT OPERATION FLOW

EXTERNAL DEVICE

PROCESSOR

ACKNOWLEDGE BREAKPOINT

IF BREAKPOINT INSTRUCTION EXECUTED:

1. SET R/W TO READ

2. SET FUNCTION CODE TO CPU SPACE

3. PLACE CPU SPACE TYPE 0 ON A19–A16

4. PLACE BREAKPOINT NUMBER ON A2–A4

5. CLEAR T-BIT (A1)

6. SET SIZE TO WORD

7. ASSERT AS AND DS
IF BKPT PIN ASSERTED:

1. SET R/W TO READ

2. SET FUNCTION CODE TO CPU SPACE

3. PLACE CPU SPACE TYPE 0 ON A19–A16

4. PLACE ALL ONE'S ON A4–A2

5. SET T-BIT (A-1) TO ONE

6. SET SIZE TO WORD

7. ASSERT AS AND DS

IF BREAKPOINT INSTRUCTION EXECUTED:

1. PLACE REPLACEMENT OPCODE ON DATA BUS

2. ASSERT DSACKx

-OR-

1. ASSERT BERR TO INITIATE EXCEPTION PROCESSING
IF BKPT PIN ASSERTED:

1. ASSERT DSACKx

-OR-

IF BREAKPOINT INSTRUCTION EXECUTED AND

1. ASSERT BERR TO INITIATE EXCEPTION PROCESSING

DSACKx IS ASSERTED:

1. LATCH DATA

2. NEGATE AS AND DS

3. GO TO (A)
IF BKPT PIN ASSERTED AND DSACKx IS ASSERTED:

1. NEGATE AS AND DS

2. GO TO (A)
IF BERR ASSERTED:

1. NEGATE AS AND DS

2. GO TO (B)

(A) (B)

IF BREAKPOINT INSTRUCTION EXECUTED:

1. PLACE LATCHED DATA IN INSTRUCTION PIPELINE

2. CONTINUE PROCESSING
IF BKPT PIN ASSERTED:

1. CONTINUE PROCESSING

IF BREAKPOINT INSTRUCTION EXECUTED:

1. INITIATE ILLEGAL INSTRUCTION PROCESSING
IF BKPT PIN ASSERTED:

1. INITIATE HARDWARE BREAKPOINT PROCESSING

Figure 3-17. Breakpoint Operation Flowchart

1. NEGATE DSACKx or BERR

MOTOROLA MC68341 USER’S MANUAL 3-33

CLKOUT

A31–A20

S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5

S0

S1 S2 S3 S4 S5 S0

A19–A16

A4–A1

A15–A5,A0

FC3–FC0

BREAKPOINT ENCODING (0000)

BREAKPOINT NUMBER/T-BIT

CPU SPACE

SIZ0

SIZ1

AS

DS

R/W

DSACKx

D7–D0

D15–D8

BERR

HALT

BKPT

FETCHED

INSTRUCTION

BREAKPOINT

OCCURS

READ

BREAKPOINT

ACKNOWLEDGE

INSTRUCTION WORD FETCH

EXECUTION

Figure 3-18. Breakpoint Acknowledge Cycle Timing (Opcode Returned)

3-34 MC68341 USER’S MANUAL MOTOROLA

CLKOUT

A31–A20

S0 S1 S2 S3 S4 S5

S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0

A19–A16

A4–A1

A15–A5, A0

FC3–FC0

BREAKPOINT ENCODING (0000)

BREAKPOINT NUMBER/T-BIT

CPU SPACE

SIZ0

SIZ1

AS

DS

R/W

DSACKx

D7–D0

D15–D8

BERR

HALT

BKPT

BREAKPOINT

OCCURS

READ

BREAKPOINT

ACKNOWLEDGE

BUS ERROR ASSERTED

EXCEPTION

STACKING

Figure 3-19. Breakpoint Acknowledge Cycle Timing (Exception Signaled)

MOTOROLA MC68341 USER’S MANUAL 3-35

3.5.3 Module Base Address Register Access

All internal module registers, including the SIM41, occupy a single 4-Kbyte block that is
relocatable along 4-Kbyte boundaries. The location is fixed by writing the desired base
address of the SIM41 block to the module base address register using the MOVES
instruction. The module base address register is only accessible in CPU space at address
$0003FF00. The SFC or DFC register must indicate CPU space (FC3–FC0 = $7), using
the MOVEC instruction, before accessing the module base address register. Refer to
Section 4 System Integration Module for additional information on the module base
address register.

3.5.4 Interrupt Acknowledge Bus Cycles

The CPU32 makes an interrupt pending in three cases. The first case occurs when a
peripheral device signals the CPU32 (with IRQ7–IRQ1) that the device requires service
and the internally synchronized value on these signals indicates a higher priority than the
interrupt mask in the status register. The second case occurs when a transition has
occurred in the case of a level 7 interrupt. A recognized level 7 interrupt must be removed
for one clock cycle before a second level 7 can be recognized. The third case occurs if,
upon returning from servicing a level 7 interrupt, the request level stays at 7 and the
processor mask level changes from 7 to a lower level, a second level 7 is recognized. The
CPU32 takes an interrupt exception for a pending interrupt within one instruction boundary
(after processing any other pending exception with a higher priority). The following
paragraphs describe the types of interrupt acknowledge bus cycles that can be executed
as part of interrupt exception processing.

3.5.4.1 INTERRUPT ACKNOWLEDGE CYCLE—TERMINATED NORMALLY. When the
CPU32 processes an interrupt exception, it performs an interrupt acknowledge cycle to
obtain the number of the vector that contains the starting location of the interrupt service
routine. Some interrupting devices have programmable vector registers that contain the
interrupt vectors for the routines they use. The following paragraphs describe the interrupt
acknowledge cycle for these devices. Other interrupting conditions or devices that cannot
supply a vector number will use the autovector cycle described in 3.5.4.2 Autovector
Interrupt Acknowledge Cycle.

3-36 MC68341 USER’S MANUAL MOTOROLA

The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in

3.4.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences
are as follows:

1. FC3–FC0 are set to $7 (FC3/FC2/FC1/FC0 = 0111) for CPU address space.

2. A3, A2, and A1 are set to the interrupt request level, and the IACK≈ strobe
corresponding to the current interrupt level is asserted. (Either the function codes
and address signals or the IACK≈ strobes can be monitored to determine that an
interrupt acknowledge cycle is in progress and the current interrupt level.)

3. The CPU32 space type field (A19–A16) is set to $F (interrupt acknowledge).

4. Other address signals (A31–A20, A15–A4, and A0) are set to one.

5. The SIZ0/SIZ1 and R/W signals are driven to indicate a single-byte read cycle.
The responding device places the vector number on the least significant byte
of its data port (for an 8-bit port, the vector number must be on D15–D8; for a
16-bit port, the vector must be on D7–D0) during the interrupt acknowledge cycle.
The cycle is then terminated normally with DSACK≈.

Figure 3-20 is a flowchart of the interrupt acknowledge cycle; Figure 3-21 shows the
timing for an interrupt acknowledge cycle terminated with DSACK≈ .

MC68340INTERRUPTING DEVICE

REQUEST INTERRUPT

1. SYNCHRONIZE IRQ7–IRQ1

2. COMPARE IRQ1–IRQ7 TO MASK LEVEL AND
WAIT FOR INSTRUCTION TO COMPLETE

3. PLACE INTERRUPT LEVEL ON A3–A1;
TYPE FIELD (A19–A16) = $F

4. SET R/W TO READ

5. SET FC3–FC0 TO 0111

PROVIDE VECTOR NUMBER

1. PLACE VECTOR NUMBER ON LEAST
SIGNIFICANT BYTE OF DATA BUS

2. ASSERT DSACKx (OR AVEC IF NO VECTOR
NUMBER)

RELEASE

1. NEGATE DSACKx

6. DRIVE SIZE PINS TO INDICATE A ONE-BYTE
TRANSFER

7. ASSERT AS AND DS

8. ASSERT THE CORRESPONDING IACKx STROBE.

1. LATCH VECTOR NUMBER

2. NEGATE DS AND AS

GRANT INTERRUPT

ACQUIRE VECTOR NUMBER

START NEXT CYCLE

Figure 3-20. Interrupt Acknowledge Cycle Flowchart

MOTOROLA MC68341 USER’S MANUAL 3-37

S0 S2 S4 S2 S4 S0

CLKOUT

A31–A4

0–2 CLOCKS*

S0 S1 S2

A3–A1

A0

FC3–FC0

SIZ0

SIZ1

R/W

AS

DS

DSACKx

INTERRUPT LEVEL

CPU SPACE

1 BYTE

VECTOR FROM 16-BIT PORT

VECTOR FROM 8-BIT PORT

D7–D0

D15–D8

IRQ7–IRQ1

IACK7–IACK1

*Internal Arbitration may take between 0–2 clock cycles.

READ

CYCLE

INTERNAL

ARBITRATION

WRITE
STACK

IACK CYCLE

Figure 3-21. Interrupt Acknowledge Cycle Timing

3.5.4.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE . When the interrupting

device cannot supply a vector number, it requests an automatically generated vector
(autovector). Instead of placing a vector number on the data bus and asserting DSACK≈,
the device asserts AVEC to terminate the cycle. If the DSACK≈ signals are asserted
during an interrupt acknowledge cycle terminated by AVEC, the DSACK≈ signals and data

3-38 MC68341 USER’S MANUAL MOTOROLA

will be ignored if AVEC is asserted before or at the same time as the DSACK≈ signals.
The vector number supplied in an autovector operation is derived from the interrupt level
of the current interrupt. When AVEC is asserted instead of DSACK≈ during an interrupt
acknowledge cycle, the MC68341 ignores the state of the data bus and internally
generates the vector number (the sum of the interrupt level plus 24 ($18)).

AVEC

is multiplexed with CS0 . The FIRQ bit in the SIM41 module configuration register

controls whether the AVEC/CS0 pin is used as an autovector input or as CS0 (refer to
Section 4 System Integration Module for additional information). AVEC is only sampled
during an interrupt acknowledge cycle. During all other cycles, AVEC is ignored.
Additionally, AVEC can be internally generated for external devices by programming the
autovector register. Seven distinct autovectors can be used, corresponding to the seven
levels of interrupt available with signals IRQ7

–IRQ1. Figure 3-22 shows the timing for an

autovector operation.

3.5.4.3 SPURIOUS INTERRUPT CYCLE. Requested interrupts, whether internal or
external, are arbitrated internally. When no internal module (including the SIM41, which
responds for external requests) responds during an interrupt acknowledge cycle by
arbitrating for the interrupt acknowledge cycle internally, the spurious interrupt monitor
generates an internal bus error signal to terminate the vector acquisition. The MC68341
automatically generates the spurious interrupt vector number (24) instead of the interrupt
vector number in this case. When an external device does not respond to an interrupt
acknowledge cycle with AVEC or DSACK≈, a bus monitor must assert BERR, which
results in the CPU32 taking the spurious interrupt vector. If HALT is also asserted, the
MC68341 retries the interrupt acknowledge cycle instead of using the spurious interrupt
vector.

MOTOROLA MC68341 USER’S MANUAL 3-39

S0 S2 S4 S2 S4

0–2 CLOCKS*

S1

S0S0

S2

CLKOUT

A31–A4

A3–A1

INTERRUPT LEVEL

A0

FC3–FC0

CPU SPACE

SIZ0

1 BYTE

SIZ1

R/W

AS

DS

DSACKx

D15–D0

AVEC

IRQ7–IRQ1

IACK7–IACK1

CYCLE

READ

INTERNAL

ARBITRATION

IACK

WRITE
STACK

CYCLE

* Internal Arbitration may take between 0–2 clocks.

Figure 3-22 Autovector Operation Timing

3-40 MC68341 USER’S MANUAL MOTOROLA

3.6 BUS EXCEPTION CONTROL CYCLES

The bus architecture requires assertion of DSACK≈ from an external device to signal that
a bus cycle is complete. Neither DSACK≈ nor AVEC is asserted in the following cases:

• DSACK≈ /AVEC is programmed to respond internally.

• The external device does not respond.

• Various other application-dependent errors occur.

The MC68341 provides BERR when no device responds by asserting DSACK≈/AVEC
within an appropriate period of time after the MC68341 asserts AS. This mechanism
allows the cycle to terminate and the MC68341 to enter exception processing for the error
condition. HALT is also used for bus exception control. This signal can be asserted by an
external device for debugging purposes to cause single bus cycle operation, or, in
combination with BERR , a retry of a bus cycle in error. To properly control termination of a
bus cycle for a retry or a bus error condition, DSACK≈, BERR , and HALT can be asserted
and negated with the rising edge of the MC68341 clock. This assures that when two
signals are asserted simultaneously, the required setup and hold time for both is met for
the same falling edge of the MC68341 clock. This or an equivalent precaution should be
designed into the external circuitry to provide these signals. Alternatively, the internal bus
monitor could be used. The acceptable bus cycle termination s for asynchronous cycles
are summarized in relation to DSACK≈ assertion as follows (case numbers refer to Table
3-4):

• Normal Termination: DSACK≈ is asserted; BERR and HALT remain negated (case 1).

• Halt Termination: HALT is asserted at the same time as or before DSACKx, and

BERR remains negated (case 2).

• Bus Error Termination: BERR is asserted in lieu of, at the same time as, or before

DSACK≈ (case 3) or after DSACK≈ (case 4), and HALT remains negated; BERR is
negated at the same time as or after DSACK≈ .

• Retry Termination: HALT and BERR are asserted in lieu of, at the same time as, or

before DSACK≈ (case 5) or after DSACK≈ (case 6); BERR is negated at the same
time as or after DSACK≈ , and HALT may be negated at the same time as or after
BERR .

Table 3-4 lists various combinations of control signal sequences and the resulting bus
cycle terminations. To ensure predictable operation, BERR and HALT should be negated
according to the specifications given in Section 12 Electrical Characteristics. DSACK≈
BERR , and HALT may be negated after AS. If DSACK≈ or BERR remain asserted into S2
of the next bus cycle, that cycle may be terminated prematurely.

EXAMPLE A: A system uses a bus monitor timer to terminate accesses to an unpopulated
address space. The timer asserts BERR after timeout (case 3).

MOTOROLA MC68341 USER’S MANUAL 3-41

EXAMPLE B: A system uses error detection and correction on RAM contents. The

DSACK¯, BERR

HALT

designer may:

1. Delay DSACK≈ until data is verified and assert BERR and HALT simultaneously to
indicate to the MC68341 to automatically retry the error cycle (case 5), or if data is
valid, assert DSACK≈ (case 1).

2. Delay DSACK≈ until data is verified and assert BERR with or without DSACK≈ if data
is in error (case 3). This initiates exception processing for software handling of the
condition.

3. Return DSACK≈ prior to data verification; if data is invalid, BERR is asserted on the
next clock cycle (case 4). This initiates exception processing for software handling of
the condition.

4. Return DSACK≈ prior to data verification; if data is invalid, assert BERR and HALT
on the next clock cycle (case 6). The memory controller can then correct the RAM
prior to or during the automatic retry.

Table 3-4.

Case
Num

1 DSACK≈

2 DSACK≈

3 DSACK≈

4 DSACK≈

5 DSACK≈

6 DSACK≈

Control

Signal N N + 2 Result

BERR

HALT

BERR

HALT

BERR

HALT

BERR

HALT

BERR

HALT

BERR

HALT

Asserted on Rising

Edge of State

A
NA
NA

A
NA

A/S

NA/A

A
NA

A
NA
NA

NA/A

A

A/S

A
NA
NA

S

NA

X
S

NA

S
X

S
X

X
A

NA

X
S
S

X
A
A

, and

Assertion Results

Normal cycle terminate and continue.

Normal cycle terminate and halt; continue
when HALT negated.

Terminate and take bus error exception,
possibly deferred.

Terminate and take bus error exception,
possibly deferred.

Terminate and retry when HALT negated.

Terminate and retry when HALT negated.

NOTES:

N — Number of the current even bus state (e.g., S2, S4, etc.)
A — Signal is asserted in this bus state

NA — Signal is not asserted in this state

X — Don't care
S — Signal was asserted in previous state and remains asserted in this state

3-42 MC68341 USER’S MANUAL MOTOROLA

3.6.1 Bus Errors

BERR can be used to abort the bus cycle and the instruction being executed. BERR takes
precedence over DSACK≈ provided it meets the timing constraints described in Section
12 Electrical Characteristics . If BERR does not meet these constraints, it may cause
unpredictable operation of the MC68341. If BERR remains asserted into the next bus
cycle, it may cause incorrect operation of that cycle. When BERR is issued to terminate a
bus cycle, the MC68341 can enter exception processing immediately following the bus
cycle, or it can defer processing the exception.

The instruction prefetch mechanism requests instruction words from the bus control ler
before it is ready to execute them. If a bus error occurs on an instruction fetch, the
MC68341 does not take the exception until it attempts to use that instruction word. Should
an intervening instruction cause a branch or should a task switch occur, the bus error
exception does not occur. The bus error condition is recognized during a bus cycle in any
of the following cases:

• DSACK≈ and HALT are negated, and BERR is asserted.

• HALT and BERR are negated, and DSACK≈ is asserted. BERR is then asserted
within one clock cycle (HALT remains negated).

• BERR and HALT are asserted simultaneously, indicating a retry.

When the MC68341 recognizes a bus error condition, it terminates the current bus cycle in
the normal way. Figure 3-23 shows the timing of a bus error for the case in which DSACK≈
is not asserted. Figure 3-24 shows the timing for a bus error that is asserted after
DSACK≈ . Exceptions are taken in both cases. Refer to Section 5 CPU32 for details of bus
error exception processing.

In the second case, in which BERR is asserted after DSACK≈ is asserted, BERR must be
asserted within the time specified for purely asynchronous operation, or it must be
asserted and remain stable during the sample window around the next falling edge of the
clock after DSACK≈ is recognized. If BERR is not stable at this time, the MC68341 may
exhibit erratic behavior. BERR has priority over DSACK≈. In this case, data may be
present on the bus, but it may not be valid. This sequence can be used by systems that
have memory error detection and correction logic and by external cache memories.

MOTOROLA MC68341 USER’S MANUAL 3-43

S0 S2

DSACK¯

CLKOUT

A31–A0

FC3–FC0

R/W

AS

DS

DSACKx

BERR

DTC

S0 S2SW S4SW S4

D15–D0

READ CYCLE WITH BUS

ERROR

INTERNAL

PROCESSING

STACK

WRITE

Figure 3-23. Bus Error without

3-44 MC68341 USER’S MANUAL MOTOROLA

CLKOUT

DSACK¯

A31–A0

FC3–FC0

R/W

AS

DS

DSACKx

BERR

DTC

S0 S2 S4 S0 S2 S4

D15–D0

WRITE

CYCLE

INTERNAL

PROCESSING

STACK
WRITE

Figure 3-24. Late Bus Error with

3.6.2 Retry Operation

When both BERR and HALT are asserted by an external device during a bus cycle, the
MC68341 enters the retry sequence shown in Figure 3-25. A delayed retry, which is
similar to the delayed BERR signal described previously, can also occur (see Figure 3-

26). The MC68341 terminates the bus cycle, places the control signals in their inactive
state, and does not begin another bus cycle until the BERR and HALT signals are negated
by external logic. After a synchronization delay, the MC68341 retries the previous cycle
using the same access information (address, function code, size, etc.). BERR should be
negated before S2 of the retried cycle to ensure correct operation of the retried cycle.

MOTOROLA MC68341 USER’S MANUAL 3-45

CLKOUT

A31–A0

FC3–FC0

R/W

AS

DS

DSACKx

BERR

S0 S2 S0 S2SW S4SW S4

HALT

DTC

D15–D0

DATA

IGNORED

READ RERUNHALTREAD CYCLE WITH

RETRY

Figure 3-25. Retry Sequence

The MC68341 retries any read or write cycle of a read-modify-write operation separately;
RMC remains asserted during the entire retry sequence. Asserting BR along with BERR
and HALT provides a relinquish and retry operation. The MC68341 does not relinquish the
bus during a read-modify-write operation. Any device that requires the MC68341 to give
up the bus and retry a bus cycle during a read-modify-write cycle must assert only BERR
and BR (HALT must not be included). The bus error handler software should examine the
read-modify-write bit in the special status word (see Section 5 CPU32) and take the
appropriate action to resolve this type of fault when it occurs.

3-46 MC68341 USER’S MANUAL MOTOROLA

S0 S2 S4 S0 S2 S4

CLKOUT

A31–A0

FC3–FC0

R/W

AS

DS

DSACKx

BERR

HALT

DTC

D15–D10

WRITE
CYCLE

HALT

WRITE

RERUN

Figure 3-26. Late Retry Sequence

3.6.3 Halt Operation

When HALT is asserted and BERR is not asserted, the MC68341 halts external bus
activity at the next bus cycle boundary (see Figure 3-27). HALT by itself does not
terminate a bus cycle. Negating and reasserting HALT in accordance with the correct
timing requirements provides a single-step (bus cycle to bus cycle) operation. Since HALT
affects external bus cycles only, a program that does not require use of the external bus
may continue executing. The single-cycle mode allows the user to proceed through (and
debug) external MC68341 operations, one bus cycle at a time. Since the occurrence of a
bus error while HALT is asserted causes a retry operation, the user must anticipate retry
cycles while debugging in the single-cycle mode. The single-step operation and the
software trace capability allow the system debugger to trace single bus cycles, single
instructions, or changes in program flow.

When the MC68341 completes a bus cycle with HALT asserted, D15–D0 is placed in the
high-impedance state, and bus control signals are negated (not high-impedance state);
the A31–A0, FCx, SIZx, and R/W signals remain in the same state. The halt operation has
no effect on bus arbitration (see 3.7 Bus Arbitration). When bus arbitration occurs while
the MC68341 is halted, the address and control signals are also placed in the high­impedance state. Once bus mastership is returned to the MC68341, if HALT is still

MOTOROLA MC68341 USER’S MANUAL 3-47

asserted, the A31–A0, FCx, SIZx, and R/W signals are again driven to their previous

HALT

states. The MC68341 does not service interrupt requests while it is halted.

S0 S2 S4

CLKOUT

A31–A0

FC3–FC0

R/W

AS

DS

DSACKx

D15–D10

HALT

BR

S0 S2 S4

S0

BG

BGACK

READ

Figure 3-27.

(ARBITRATION PERMITTED

HALT

WHILE THE PROCESSOR IS

HALTED)

Timing

READ

3.6.4 Double Bus Fault

A double bus fault results when a bus error or an address error occurs during the
exception processing sequence for any of the following:

• A previous bus error

• A previous address error

• A reset

For example, the MC68341 attempts to stack several words containing information about
the state of the machine while processing a bus error exception . If a bus error exception

3-48 MC68341 USER’S MANUAL MOTOROLA

occurs during the stacking operation, the second error is considered a double bus fault.
When a double bus fault occurs, the MC68341 halts and asserts HALT. Only a reset
operation can restart a halted MC68341. However, bus arbitration can still occur (see 3.7
Bus Arbitration). A second bus error or address error that occurs after exception
processing has completed (during the execution of the exception handler routine or later)
does not cause a double bus fault. A bus cycle that is retried does not constitute a bus
error or contribute to a double bus fault. The MC68341 continues to retry the same bus
cycle as long as the external hardware requests it.

Reset can also be generated internally by the halt monitor (see Section 5 CPU32).

3.7 BUS ARBITRATION

The bus design of the MC68341 provides for a single bus master at any one time, either
the MC68341 or an external device. One or more of the external devices on the bus can
have the capability of becoming bus master for the external bus, but not the MC68341
internal bus. Bus arbitration is the protocol by which an external device becomes bus
master; the bus controller in the MC68341 manages the bus arbitration signals so that the
MC68341 has the lowest priority. External devices that need to obtain the bus must assert
the bus arbitration signals in the sequences described in the following paragraphs.
Systems having several devices that can become bus master require external circuitry to
assign priorities to the devices so that, when two or more external devices attempt to
become bus master at the same time, the one having the highest priority becomes bus
master first. The sequence of the protocol is as follows:

1. An external device asserts BR.

2. The MC68341 asserts BG to indicate that the bus is available.

3. The external device asserts BGACK to indicate that it has assumed bus mastership.

NOTE

The MC68341 does not place CS3–CS0 in a high-impedance
state after reset or when the bus is granted to an external
master.

BR may be issued any time during a bus cycle or between cycles. BG is asserted in
response to BR. To guarantee operand coherency, BG is only asserted at the end of an
operand transfer. Additionally, BG is not asserted until the end of a read-modify-write
operation (when RMC is negated) in response to a BR signal. When the requesting device
receives BG and more than one external device can be bus master, the requesting device
should begin whatever arbitration is required. When the external device assumes bus
mastership, it asserts BGACK and maintains BGACK during the entire bus cycle (or
cycles) for which it is bus master. The following conditions must be met for an external
device to assume mastership of the bus through the normal bus arbitration procedure: 1) it
must have received BG through the arbitration process, and 2) BGACK must be inactive,
indicating that no other bus master has claimed ownership of the bus.

MOTOROLA MC68341 USER’S MANUAL 3-49

Figure 3-28 is a flowchart showing bus arbitration for a single device. This technique
allows processing of bus requests during data transfer cycles. Refer to Figures 3-29 and
3-30 for bus arbitration timing diagrams.

BR is negated at the time that BGACK is asserted. This type of operation applies to a
system consisting of the MC68341 and one device capable of bus mastership. In a system
having a number of devices capable of bus mastership, BR from each device can be wire­ORed to the MC68341. In such a system, more than one bus request could be asserted
simultaneously. BG is negated a few clock cycles after the transition of BGACK. However,
if bus requests are still pending after the negation of BG , the MC68341 asserts another
BG within a few clock cycles after it was negated. This additional assertion of BG allows
external arbitration circuitry to select the next bus master before the current bus master
has finished using the bus. The following paragraphs provide additional information about
the three steps in the arbitration process. Bus arbitration requests are recognized during
normal processing, HALT assertion, and a CPU32 halt caused by a double bus fault.

PROCESSOR REQUESTING DEVICE

REQUEST THE BUS

GRANT BUS ARBITRATION

1. ASSERT BG

TERMINATE ARBITRATION

1. NEGATE BG (AND WAIT FOR
BGACK TO BE NEGATED)

RE-ARBITRATE OR RESUME

PROCESSOR OPERATION

1. ASSERT BR

ACKNOWLEDGE BUS MASTERSHIP

1. EXTERNAL ARBITRATION DETERMINES
NEXT BUS MASTER

2. NEXT BUS MASTER WAITS FOR BGACK
TO BE NEGATED

3. NEXT BUS MASTER ASSERTS BGACK
TO BECOME NEW MASTER

4. BUS MASTER NEGATES BR

OPERATE AS BUS MASTER

1. PERFORM DATA TRANSFERS (READ AND
WRITE CYCLES) ACCORDING TO THE
SAME RULES THE PROCESSOR USES

RELEASE BUS MASTERSHIP

1. NEGATE BGACK

Figure 3-28. Bus Arbitration Flowchart for Single Request

3-50 MC68341 USER’S MANUAL MOTOROLA