Motorola MC33349N-4, MC33349N-3, MC33349N-1, MC33349N-10, MC33349N-2 Datasheet
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SEMICONDUCTOR
TECHNICAL DATA
LITHIUM BATTERY
PROTECTION CIRCUIT
FOR
ONE CELL
SMART BATTERY PACKS
N SUFFIX
PLASTIC PACKAGE
CASE 1262
(SOT–23)
Order this document by MC33349PP/D
6
1
16
4
2
3
(Top View)
DO
P–
CO
Gnd
C
t
PIN CONNECTIONS
5
V
cell
1
MOTOROLA ANALOG IC DEVICE DATA
The MC33349 is a monolithic lithium battery protection circuit that is
designed to enhance the useful operating life of a one cell rechargeable
battery pack. Cell protection features consist of internally trimmed charge
and discharge voltage limits, charge and discharge current limit detection,
and a virtually zero current sleepmode state when the cell is discharged.
This protection circuit requires a minimum number of external components
and is targeted for inclusion within the battery pack. This MC33349 is
available in the SOT–23 6 lead surface mount package.
• Internally Trimmed Charge and Discharge Voltage Limits
• Charge and Discharge Current Limit Detection
• Virtually Zero Current Sleepmode State when Cells are Discharged
• Dedicated for One Cell Applications
• Minimum Components for Inclusion within the Battery Pack
• Available in a Low Profile Surface Mount Package
Ordering Information shown on following page.
Typical One Cell Smart Battery Pack
This device contains 264 active transistors.
132
5
6
4
MC33349
0.1 µF
0.1
µ
F
0.01
µ
F
100
Ω
1.0 k
Ω
This document contains information on a product under development. Motorola reserves the
right to change or discontinue this product without notice.
Motorola, Inc. 1998 Rev 0
MC33349
2
MOTOROLA ANALOG IC DEVICE DATA
ORDERING INFORMATION
Device
Charge
Overvoltage
Threshold (V)
Charge
Overvoltage
Hysteresis (mV)
Discharge
Undervoltage
Threshold (V)
Current Limit
Threshold (mV)
Operating
Temperature Range
Package
MC33349N–1 4.2
150
MC33349N–2 4.2
75
MC33349N–3 4.25
150
MC33349N–4 4.25
75
MC33349N–5 4.3
150
–
°
–
MC33349N–6 4.3
200
2.3
75
T
A
= –40 to
85°C
SOT–23
MC33349N–7 4.35 150
MC33349N–8 4.35 75
MC33349N–9 4.65 150
MC33349N–10
4.65 75
MAXIMUM RATINGS
Ratings Symbol Value Unit
Input Voltage
V
IR
V
Discharge Gate Drive Output (Pin 1) to Gnd (Pin 6) 5.0 to –1.0
Charge Gate Drive Common/Current Limit (Pin 2) to V
cell
(Pin 5)
1.0 to –18
Charge Gate Drive Output (Pin 3) to V
cell
(Pin 5) 1.0 to –18
Overvoltage Delay Capacitor (Pin 4) to Gnd (Pin 6) 5.0 to –1.0
Cell Voltage (Pin 5) to Gnd (Pin 6) 5.0 to –1.0
ББББББББББББББ
Thermal Resistance, Junction–to–Air
ÁÁ
R
θJA
ÁÁÁ
Á
°C/W
N Suffix, SOT–23 Plastic Package, Case 1262 TBD
Operating Junction Temperature (Note 1)
T
J
–40 to 85
°C
Storage Temperature
T
stg
–55 to 125
°C
MC33349
3
MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS (C
t
= 0.01 µF, TA = 25°C, for min/max values TA is the operating junction temperature range
that applies, unless otherwise noted.)
Characteristic
Symbol Min Typ Max Unit
VOLTAGE SENSING
Cell Charging Cutoff (Pin 5 to Pin 6)
ÁÁÁÁ
ÁÁÁ
Overvoltage Threshold, V
Cell
Increasing V
th(OV)
V
–1, –3 Suffix – 4.35 –
–2, –4 Suffix – 4.25 –
Overvoltage Hysteresis V
Cell
Decreasing V
H
– 200 – mV
Cell Discharging Cutoff (Pin 5 to Pin 6)
ÁÁÁÁ
ÁÁÁ
Undervoltage Threshold, V
Cell
Decreasing V
th(UV)
V
–1, –3 Suffix – 2.30 –
–2, –4 Suffix – 2.28 –
Input Bias Current During Cell Voltage Sample (Pin 5)
ÁÁÁÁ
I
IIB
–
20
–
ÁÁÁ
µA
Overvoltage Delay Time (V
cell
= 4.5 V) t
(ovd)
– 75 – ms
Unervoltage Delay Time (V
cell
= 2.1 V) t
(uvd)
– 13 – ms
Cell Voltage Sampling Period
ÁÁÁÁ
t
(smpl)
–
2.0
–
ÁÁÁ
ms
Cell Voltage Sampling Repitition Period t
(rep)
– 26 – ms
CURRENT SENSING
Discharge/Charge Current Limit (Pin 2 to Pin 6)
ÁÁÁÁ
ÁÁÁ
Discharge Threshold Voltage V
th(dschg)
mV
–1, –2 Suffix – 150 –
–3, –4 Suffix – 75 –
Discharge Current Hysteresis DCH – 50 – %
Charge Threshold Voltage V
th(chg)
mV
–1. –2 Suffix – –150 –
–3, –4 Suffix – –75 –
Charge Current Hysteresis CCH – 25 – %
Current Limit Delay Time (1.0 nF load @ CO & DO; to VDD/2)
Charge Gate Drive Output (Pin 3) t
(ccld)
– 10 – µs
Discharge Gate Drive Output (Pin 1) t
(dcld)
– 2.0 – µs
OUTPUTS
Charge Gate Drive Output Low (Pin 3 to Pin 2 @ IO = 50 µA)
ÁÁÁÁ
V
olc
–
0.2
–
ÁÁÁ
V
Charge Gate Drive Output High (Pin 5 to Pin 3 @ IO = –50 µA)
ÁÁÁÁ
V
ohc
–
0.1
–
ÁÁÁ
V
Discharge Gate Drive Output Low (Pin 1 to Pin 6 @ IO = 50 µA)
ÁÁÁÁ
V
old
–
0.2
–
ÁÁÁ
V
Discharge Gate Drive Output High (Pin 5 to Pin 1 @ IO = –50 µA)
ÁÁÁÁ
V
ohd
–
0.2
–
ÁÁÁ
V
TOTAL DEVICE
Average Cell Current
ÁÁÁÁ
I
cell
ÁÁÁ
Operating (V
cell
= 3.9 V) – 8.5 – µA
Sleepmode (V
cell
= 2.0 V) – 4.0 – nA
Minimum Operating Cell Voltage
ÁÁÁÁ
V
cell
–
1.5
–
ÁÁÁ
V
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