Datasheet MC33179D, MC33179DR2, MC33178D, MC33178DR2, MC33179P Datasheet (Motorola)

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Order this document by MC33178/D
T
40° to +85°C

         
The MC33178/9 series is a family of high quality monolithic amplifiers employing Bipolar technology with innovative high performance concepts for quality audio and data signal processing applications. This device family incorporates the use of high frequency PNP input transistors to produce amplifiers exhibiting low input offset voltage, noise and distortion. In addition, the amplifier provides high output current drive capability while consuming only 420 µA of drain current per amplifier. The NPN output stage used, exhibits no deadband crossover distortion, large output voltage swing, excellent phase and gain margins, low open–loop high frequency output impedance, symmetrical source and sink AC frequency performance.
The MC33178/9 family offers both dual and quad amplifier versions, tested over the vehicular temperature range, and are available in DIP and SOIC packages.
600 Output Drive Capability
Large Output Voltage Swing
Low Offset Voltage: 0.15 mV (Mean)
Low T.C. of Input Offset Voltage: 2.0 µV/°C
Low Total Harmonic Distortion: 0.0024% (@ 1.0 kHz w/600 Load)
High Gain Bandwidth: 5.0 MHz
High Slew Rate: 2.0 V/µs
Dual Supply Operation: ±2.0 V to ±18 V
ESD Clamps on the Inputs Increase Ruggedness
without Affecting Device Performance

HIGH OUTPUT CURRENT
LOW POWER, LOW NOISE
OPERATIONAL AMPLIFIERS
DUAL
P SUFFIX
PLASTIC PACKAGE
8
1
8
1
PIN CONNECTIONS
Output 1
Inputs 1
V
EE
1 2 3 4
CASE 626
D SUFFIX
PLASTIC PACKAGE
CASE 751
8
V
CC
7
+
Output 2
6
Inputs 2
5
– +
(Top View)
V
CC
Vin –
V
EE
Op Amp
Function
Dual
Quad
Representative Schematic Diagram (Each Amplifier)
I
I
ref
Vin +
ref
C
C
C
M
ORDERING INFORMATION
Fully
Compensated
MC33178D MC33178P
MC33179D MC33179P
Operating
Temperature Range
°
A
= –
°
Package
SO–8
Plastic DIP
SO–14
Plastic DIP
QUAD
P SUFFIX
14
1
V
O
14
1
PLASTIC PACKAGE
CASE 646
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
PIN CONNECTIONS
Output 1
Inputs 1
V
CC
Inputs 2
Output 2
1
2
––
1
++
3
4 5
++
23
––
6
78
(Top View)
14
Output 4
13
4
Inputs 4
12
11
V
EE
10
Inputs 3
9
Output 3
MOTOROLA ANALOG IC DEVICE DATA
Motorola, Inc. 1996 Rev 0
1
MC33178 MC33179
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (VCC to V Input Differential Voltage Range V Input Voltage Range V Output Short Circuit Duration (Note 2) t Maximum Junction Temperature T Storage Temperature Range T Maximum Power Dissipation P
NOTES: 1.Either or both input voltages should not exceed VCC or VEE.
2.Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. (See power dissipation performance characteristic, Figure 1.)
EE)
V
IDR
IR
SC
stg
S
Indefinite sec
J
–60 to +150 °C
D
+36 V (Note 1) V (Note 1) V
+150 °C
(Note 2) mW
DC ELECTRICAL CHARACTERISTICS (V
Characteristics Figure Symbol Min Typ Max Unit
Input Offset Voltage (RS = 50 , VCM = 0 V, VO = 0 V)
(VCC = +2.5 V, VEE = –2.5 V to VCC = +15 V, VEE = –15 V)
TA = +25°C TA = –40° to +85°C
Average Temperature Coefficient of Input Of fset Voltage
(RS = 50 , VCM = 0 V, VO = 0 V)
TA = –40° to +85°C
Input Bias Current (VCM = 0 V, VO = 0 V)
TA = +25°C TA = –40° to +85°C
Input Offset Current (VCM = 0 V, VO = 0 V)
TA = +25°C TA = –40° to +85°C
Common Mode Input Voltage Range
(VIO = 5.0 mV, VO = 0 V)
Large Signal Voltage Gain (VO = –10 V to +10 V, RL = 600 )
TA = +25°C TA = –40° to +85°C
Output Voltage Swing (VID = ±1.0 V)
(VCC = +15 V, VEE = –15 V)
RL = 300 RL = 300 RL = 600 RL = 600 RL = 2.0 k RL = 2.0 k
(VCC = +2.5 V, VEE = –2.5 V)
RL = 600
RL = 600 Common Mode Rejection (Vin = ±13 V) 11 CMR 80 110 dB Power Supply Rejection
VCC/VEE = +15 V/ –15 V, +5.0 V/ –15 V, +15 V/ –5.0 V
Output Short Circuit Current (VID = ±1.0 V , Output to Ground)
Source (VCC = 2.5 V to 15 V) Sink (VEE = –2.5 V to –15 V)
Power Supply Current (VO = 0 V)
(VCC = 2.5 V, VEE = –2.5 V to VCC = +15 V, VEE = –15 V)
MC33178 (Dual)
TA = +25°C TA = –40° to +85°C
MC33179 (Quad)
TA = +25°C TA = –40° to +85°C
= +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
CC
2 |VIO|
2 VIO/T
3, 4 I
5 V
6, 7 A
8, 9, 10
12 PSR 80 110 dB
13, 14 I
15 I
IB
|IIO|
ICR
VOL
VO+ VO– VO+ VO– VO+ VO–
VO+ VO–
SC
D
— —
2.0
— —
— —
–13
50 k 25 k
— —
+12
+13
1.1 —
+50 –50
— —
— —
0.15 —
100
5.0 —
–14 +14
200 k
+12 –12
+13.6
–13 +14
–13.8
1.6
–1.6
+80
–100
— —
1.7 —
3.0
4.0
500 600
50 60
+13
— —
— — —
–12
–13
–1.1
— —
1.4
1.6
2.4
2.6
mV
µV/°C
nA
nA
V
V/V
V
mA
mA
2
MOTOROLA ANALOG IC DEVICE DATA
MC33178 MC33179
AC ELECTRICAL CHARACTERISTICS (V
Characteristics Figure Symbol Min Typ Max Unit
Slew Rate
(Vin = –10 V to +10 V, RL = 2.0 k, CL = 100 pF, AV = +1.0 V) Gain Bandwidth Product (f = 100 kHz) 17 GBW 2.5 5.0 MHz AC Voltage Gain (RL = 600 , VO = 0 V, f = 20 kHz) 18, 19 A Unity Gain Frequency (Open–Loop) (RL = 600 , CL = 0 pF) f Gain Margin (RL = 600 , CL = 0 pF) 20, 22, 23 A Phase Margin (RL = 600 , CL = 0 pF) 21, 22, 23 φ
Channel Separation (f = 100 Hz to 20 kHz) 24 CS –120 dB Power Bandwidth (VO = 20 V Distortion (RL = 600 ,, VO = 2.0 Vpp, AV = +1.0 V)
(f = 1.0 kHz)
(f = 10 kHz)
(f = 20 kHz) Open Loop Output Impedance
(VO = 0 V, f = 3.0 MHz, AV = 10 V) Differential Input Resistance (VCM = 0 V) R Differential Input Capacitance (VCM = 0 V) C Equivalent Input Noise Voltage (RS = 100 ,)
f = 10 Hz
f = 1.0 kHz Equivalent Input Noise Current
f = 10 Hz
f = 1.0 kHz
= 600 , THD 1.0%) BW
pp, RL
= +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
CC
16, 31 SR 1.2 2.0 V/µs
VO
U
m
m
p
25 THD
26 |ZO| 150
in in
27 e
28 i
n
n
50 dB — 3.0 MHz — 15 dB — 60 Degree
32 kHz
0.0024 — —
200 k 10 pF
— —
— —
0.014
0.024
8.0
7.5
0.33
0.15
— — —
nV/ Hz
— —
pA/ Hz
— —
s
%
Figure 1. Maximum Power Dissipation
versus T emperature
2400
2000
MC33178P/9P
1600
MC33179D
1200
800
MC33178D
400
D
0
P (MAX), MAXIMUM POWER DISSIPATION (mW)
–60 –40 –20 0 20 40 60 80 100 120 180160140
TA, AMBIENT TEMPERATURE (°C)
MOTOROLA ANALOG IC DEVICE DATA
Figure 2. Input Offset Voltage versus
T emperature for 3 Typical Units
4.0
3.0
2.0
1.0 0
–1.0 –2.0 –3.0
IO
V , INPUT OFFSET VOLTAGE (mV)
–4.0
–55 –25 0 25 50 75 100 125
Unit 1 Unit 2
Unit 3
TA, AMBIENT TEMPERATURE (°C)
VCC = +15 V VEE = –15 V RS = 10 VCM = 0 V
3
MC33178 MC33179
Figure 3. Input Bias Current
versus Common Mode V oltage
160 140 120 100
80
VCC = +15 V
60
VEE = –15 V
40
IB
I , INPUT BIAS CURRENT (nA)
20
0
–15 –10 –5.0 0 5.0 10 15
TA = 25
°
C
VCM, COMMON MODE VOLTAGE (V)
Figure 5. Input Common Mode V oltage
Range versus T emperature
V
CC
VCC –0.5 V VCC –1.0 V
VCC –1.5 V VCC –2.0 V
VEE +1.0 V VEE +0.5 V
, INPUT COMMON MODE VOL TAGE RANGE (V)
V
EE
ICR
V
–55 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
VCC = +5.0 V to +18 V VEE = –5.0 V to –18 V
VIO = 5.0 mV
Figure 4. Input Bias Current
versus T emperature
120
VCC = +15 V
110
VEE = –15 V VCM = 0 V
100
90
80
IB
70
I , INPUT BIAS CURRENT (nA)
60
–55 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (
°
C)
Figure 6. Open Loop Voltage Gain
versus T emperature
250
200
150
VCC = +15 V
100
VEE = –15 V f = 10 Hz
VO = 10 V to +10 V
50
, OPEN LOOP VOL TAGE GAIN (kV/V)
VOL
A
0
–55 –25 0 25 50 75 100 125
RL = 600
TA, AMBIENT TEMPERATURE (
°
C)
Figure 7. V oltage Gain and Phase
versus Frequency
50 40
30 20 10
0 –10 –20
1A) Phase (RL = 600 Ω)
–30
2A) Phase (RL = 600
VOL
1B) Gain (RL = 600
–40
A , OPEN LOOP VOL TAGE GAIN (dB)
2B) Gain (RL = 600
–50
2 3 4 5 6 7 8 9 10 20
Ω,
CL = 300 pF)
)
, CL = 300 pF)
f, FREQUENCY (Hz)
VCC = +15 V VEE = –15 V VO = 0 V TA = 25
2A
4
1B
2B
1A
Figure 8. Output Voltage Swing
versus Supply V oltage
80 100 120 140
°
C
160 180 200 220
, EXCESS PHASE (DEGREES)
φ
240 260
280
40 35
pp
30 25
20 15 10
, OUTPUT VOLTAGE (V )
O
V
5.0 0
0 5.0 10 15 20
TA = 25°C
VCC, |V
RL = 10 k
SUPPLY VOLTAGE (V)
EE|,
RL = 600
MOTOROLA ANALOG IC DEVICE DATA
MC33178 MC33179
Figure 9. Output Saturation Voltage
versus Load Current
V
CC
TA = +125°C
Source
VCC –1.0 V
TA = –55°C
VCC –2.0 V
VEE +2.0 V
Sink
TA = –55°C
VEE +1.0 V
, OUTPUT SA TURATION VOLTAGE (V)
sat
V
TA = +125°C
V
EE
0 5.0 10 15 20
VCC = +5.0 V to +18 V VEE = –5.0 V to –18 V
IL, LOAD CURRENT (±mA)
Figure 11. Common Mode Rejection
versus Frequency Over T emperature
120
O
VCC = +15 V VEE = –15 V VCM = 0 V
VCM = ±1.5 V
°
to +125°C
TA = –55
100
80
60
A
V
40
CM
20
CMR = 20 Log
CMR, COMMON MODE REJECTION (dB)
0
DM
+
V
V
CM
x A
DM
V
O
10 100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz)
Figure 10. Output Voltage
versus Frequency
28 24
pp
20
16
VCC = +15 V
12
VEE = –15 V
8.0
, OUTPUT VOLTAGE (V )
O
4.0
V
RL = 600 AV = +1.0 V
1.0%
THD =
°
C
TA = 25
0
1.0 k 10 k 100 k 1.0 M f, FREQUENCY (Hz)
Figure 12. Power Supply Rejection
versus Frequency Over T emperature
120
VO/A
V
V
+PSR
–PSR
O
DM
CC
100
80
V
60
40
20
PSR, POWER SUPPLY REJECTION (dB)
0
A
DM
+
V
PSR = 20 Log
CC
EE
10 100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz)
TA = –55° to +125°C VCC = +15 V VEE = –15 V
VCC = ±1.5 V
Figure 13. Output Short Circuit Current
versus Output Voltage
100
Source
80
Sink
60
40
VCC = +15 V VEE = –15 V
±
1.0 V
20
0
SC
I , OUTPUT SHORT CIRCUIT CURRENT (mA)
–15 –9.0 –3.0 0 3.0 9.0 15
VID =
VO, OUTPUT VOLTAGE (V)
MOTOROLA ANALOG IC DEVICE DATA
Figure 14. Output Short Circuit Current
versus T emperature
100
90
Sink
80
Source
70
60
50
SC
I , OUTPUT SHORT CIRCUIT CURRENT (mA)
–55 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
VCC = +15 V VEE = –15 V
±
1.0 V
VID =
RL < 10
5
MC33178 MC33179
Figure 15. Supply Current versus Supply
V oltage with No Load
625
µ
500
375
250
125
CC
I , SUPPLY CURRENT/AMPLIFIER ( A)
0
0 2.0 4.0 6.0 8.0 10 12 14 16 18
TA = +125°C
TA = +25
°
C
TA = –55
°
C
V
|VEE| , SUPPLY VOLTAGE (V)
CC,
Figure 17. Gain Bandwidth Product
versus T emperature
10
8.0
6.0
4.0
2.0
GBW, GAIN BANDWIDTH PRODUCT (MHz)
0
–55 –25 0 25 50 75 100 125
VCC = +15 V VEE = –15 V f = 100 kHz
RL = 600 CL = 0 pF
TA, AMBIENT TEMPERATURE (
°
C)
Figure 16. Normalized Slew Rate
versus T emperature
1.15
1.10
VCC = +15 V VEE = –15 V
1.05
Vin = 20 V
1.00
0.95
0.90
0.85
SR, SLEW RATE (NORMALIZED)
0.80
0.75 –55 –25 0 25 50 75 100 125
pp
– +
V
in
TA, AMBIENT TEMPERATURE (°C)
600
Figure 18. V oltage Gain and Phase
versus Frequency
50 40 30 20 10
0
–10 –20
V
A , VOLTAGE GAIN (dB)
–30 –40 –50
100 k
VCC = +15 V VEE = –15 V RL = 600 TA = 25°C CL = 0 pF
Phase
Gain
1.0 M 10 M 100 M f, FREQUENCY (Hz)
V
O
100 pF
80 100 120 140 160 180 200 220 240
, EXCESS PHASE (DEGREES)
φ
260 280
Figure 19. V oltage Gain and Phase
versus Frequency
50 40 30 20 10
0 –10 –20
1A) Phase VCC =18 V, VEE = –18 V
V
A , VOLTAGE GAIN (dB)
2A) Phase VCC 1.5 V, VEE = –1.5 V
–30
1B) Gain VCC = 18 V, VEE = –18 V
–40
2B) Gain VCC = 1.5 V, VEE = –1.5 V
–50
100 k
1.0 M 10 M 100 M
6
1B
2B
f, FREQUENCY (Hz)
1A
2A
°
C
TA = 25
RL = CL = 0 pF
80 100 120 140 160 180 200
, PHASE (DEGREES)
220
φ
240 260 280
Figure 20. Open Loop Gain Margin
versus T emperature
15
CL = 10 pF
12
CL = 100 pF
9.0 CL = 300 pF
6.0
VCC = +15 V VEE = –15 V
3.0
m
A , OPEN LOOP GAIN MARGIN (dB)
0
–55 –25 0 25 50 75 100 125
RL = 600
TA, AMBIENT TEMPERATURE (°C)
MOTOROLA ANALOG IC DEVICE DATA
MC33178 MC33179
Figure 21. Phase Margin
versus T emperature
60
50
40
30
20
, PHASE MARGIN (DEGREES)
m
10
φ
0
–55 –25 0 25 50 75 100 125
VCC = +15 V VEE = –15 V
RL = 600
TA, AMBIENT TEMPERATURE (
CL = 10 pF
CL = 100 pF
CL = 300 pF
°
C)
Figure 23. Open Loop Gain Margin and Phase
Margin versus Output Load Capacitance
18
Phase Margin
Gain Margin
V
O
C
L
15
12
9.0
6.0
3.0
m
A , OPEN LOOP GAIN MARGIN (dB)
0
10 100 1.0 k
V
in
+
600
CL, OUTPUT LOAD CAPACITANCE (pF)
VCC = +15 V VEE = –15 V VO = 0 V
Figure 22. Phase Margin and Gain Margin
12
10
VCC = +15 V VEE = –15 V
8.0 RT = R1+R VO = 0 V
6.0
TA = 25
4.0
m
A , GAIN MARGIN (dB)
V
2.0
in
0
100 1.0 k 10 k 100 k
60 50
40
30
20
, PHASE MARGIN (DEGREES)
m
10
φ
0
150
140
130
120
110
CS, CHANNEL SEPARATION (dB)
100
100 1.0 k 10 k 100 k 1.0 M
versus Differential Source Resistance
Gain Margin
2
°
C
R
1
– +
R
2
RT, DIFFERENTIAL SOURCE RESISTANCE (Ω)
V
O
Phase Margin
Figure 24. Channel Separation
versus Frequency
Drive Channel VCC = +15 V CEE = –15 V RL = 600 TA = 25°C
f, FREQUENCY (Hz)
60
50
40
30
20
, PHASE MARGIN (DEGREES)
m
10
φ
0
Figure 25. T otal Harmonic Distortion
versus Frequency
10
VCC = +15 V VO = 2.0 V VEE = –15 V TA = 25
RL = 600
1.0
0.1
THD, TOT AL HARMONIC DISTORTION (%)
0.01 10 100 1.0 k 10 k 100 k
pp
°
C
f, FREQUENCY (Hz)
AV = 1000
AV = 100
AV = 10
AV = 1.0
MOTOROLA ANALOG IC DEVICE DATA
Figure 26. Output Impedance
versus Frequency
500
|Z |, OUTPUT IMPEDANCE ( )
O
400
300
200
100
1. AV = 1.0
2. AV = 10
3. AV = 100
4. AV = 1000
3
0
1.0 k 10 k 100 k 1.0 M 10 M
4
f, FREQUENCY (Hz)
21
VCC = +15 V VEE = –15 V VO = 0 V
°
C
TA = 25
7
MC33178 MC33179
Figure 27. Input Referred Noise V oltage
versus Frequency
20 18
nV/ Hz
16 14 12 10
8.0
6.0
4.0
2.0
n
e , INPUT REFERRED NOISE VOL TAGE ( )
VCC = +15 V VEE = –15 V
°
C
TA = 25
0
10 100 1.0 k 10 k 10 k
f, FREQUENCY (Hz)
Input Noise Voltage Test Circuit
+ –
Figure 29. Percent Overshoot versus
Load Capacitance
100
90
VCC = +15 V VEE = –15 V
80 70 60 50 40 30 20
PERCENT OVERSHOOT (%)
10
0
10 100 1.0 k 10 k
TA = 25
°
C
RL = 600
CL, LOAD CAPACITANCE (pF)
RL = 2.0 k
Figure 28. Input Referred Noise Current
versus Frequency
0.5
pA/ Hz
V
O
0.4
0.3
0.2
VCC = +15 V
0.1
VEE = –15 V
°
C
TA = 25
0
10 100 1.0 k 10 k 100 k
n
i , INPUT REFERRED NOISE CURRENT ( )
f, FREQUENCY (Hz)
Input Noise Current Test Circuit
+
R
S
(RS = 10 k
)
V
O
Figure 30. Noninverting Amplifier Slew Rate
VCC = +15 V VEE = –15 V AV = +1.0
RL = 600 CL = 100 pF
°
C
TA = 25
, OUTPUT VOLTAGE (5.0 V/DIV)
O
t, TIME (2.0 µs/DIV)
Figure 31. Small Signal Transient Response Figure 32. Large Signal Transient Response
µ
s/DIV)
VCC = +15 V VEE = –15 V AV = +1.0 RL = 600 CL = 100 pF TA = 25
, OUTPUT VOLTAGE (50 mV/DIV)
O
V
8
VCC = +15 V VEE = –15 V AV = +1.0 RL = 600 CL = 100 pF TA = 25
t, TIME (2.0 ns/DIV)
°
C
, OUTPUT VOLTAGE (5.0 V/DIV) V
O
V
t, TIME (5.0
MOTOROLA ANALOG IC DEVICE DATA
°
C
MC33178 MC33179
Figure 33. T elephone Line Interface Circuit
10 k
To
Receiver
From
Microphone
120 k
2.0 k A2 –
+
V
R
A1
– +
10 k
1.0
200 k
820
10 k
– +
0.05
A3
10 k
300
V
R
10 k
µ
F
µ
F
Tip
1N4678
Phone Line
Ring
APPLICATION INFORMA TION
This unique device uses a boosted output stage to combine a high output current with a drain current lower than similar bipolar input op amps. Its 60° phase margin and 15 dB gain margin ensure stability with up to 1000 pF of load capacitance (see Figure 23). The ability to drive a minimum 600 load makes it particularly suitable for telecom applications. Note that in the sample circuit in Figure 33 both A2 and A3 are driving equivalent loads of approximately 600 Ω.
The low input offset voltage and moderately high slew rate and gain bandwidth product make it attractive for a variety of other applications. For example, although it is not single supply (the common mode input range does not include ground), it is specified at +5.0 V with a typical common mode rejection of 1 10 dB. This makes it an excellent choice for use with digital circuits. The high common mode rejection, which is stable over temperature, coupled with a low noise figure and low distortion, is an ideal op amp for audio circuits.
The output stage of the op amp is current limited and therefore has a certain amount of protection in the event of a short circuit. However, because of its high current output, it is especially important not to allow the device to exceed the maximum junction temperature, particularly with the MC33179 (quad op amp). Shorting more than one amplifier
could easily exceed the junction temperature to the extent of causing permanent damage.
Stability
As usual with most high frequency amplifiers, proper lead dress, component placement, and PC board layout should be exercised for optimum frequency performance. For example, long unshielded input or output leads may result in unwanted input/output coupling. In order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. This not only minimizes the input pole frequency for optimum frequency response, but also minimizes extraneous “pick up” at this node. Supplying decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature.
Additional stability problems can be caused by high load capacitances and/or a high source resistance. Simple compensation schemes can be used to alleviate these effects.
MOTOROLA ANALOG IC DEVICE DATA
9
MC33178 MC33179
If a high source of resistance is used (R1 > 1.0 k), a compensation capacitor equal to or greater than the input capacitance of the op amp (10 pF) placed across the feedback resistor (see Figure 34) can be used to neutralize that pole and prevent outer loop oscillation. Since the closed loop transient response will be a function of that capacitance, it is important to choose the optimum value for that capacitor. This can be determined by the following Equation:
CC = (1 +[R1/R2])2 CL (ZO/R2)
(1)
where: ZO is the output impedance of the op amp.
Figure 34. Compensation for
High Source Impedance
R2
C
C
For moderately high capacitive loads (500 pF < C < 1500 pF) the addition of a compensation resistor on the order of 20 between the output and the feedback loop will help to decrease miller loop oscillation (see Figure 35). For high capacitive loads (CL > 1500 pF), a combined compensation scheme should be used (see Figure 36). Both the compensation resistor and the compensation capacitor affect the transient response and can be calculated for optimum performance. The value of CC can be calculated using Equation (1). The Equation to calculate RC is as follows:
RC = ZO R1/R2
(2)
Figure 35. Compensation Circuit for
Moderate Capacitive Loads
R2
L
R1
R1
+
Z
L
+
R
C
C
L
Figure 36. Compensation Circuit for
High Capacitive Loads
R2
C
C
R1
+
R
C
C
L
10
MOTOROLA ANALOG IC DEVICE DATA
NOTE 2
–T–
SEATING PLANE
H
MC33178 MC33179
OUTLINE DIMENSIONS
58
–B–
14
F
–A–
C
N
D
G
0.13 (0.005) B
K
M
T
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
L
J
M
M
A
M
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400 B 6.10 6.60 0.240 0.260 C 3.94 4.45 0.155 0.175 D 0.38 0.51 0.015 0.020
F 1.02 1.78 0.040 0.070 G 2.54 BSC 0.100 BSC H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012 K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC M ––– 10 ––– 10 N 0.76 1.01 0.030 0.040
INCHESMILLIMETERS
__
C
A
B
A1
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
ISSUE R
D
58
0.25MB
E
1
H
4
e
M
h
X 45
_
q
C
A
SEATING PLANE
0.10
L
B
SS
A0.25MCB
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
DIM MIN MAX
A 1.35 1.75
A1 0.10 0.25
B 0.35 0.49 C 0.18 0.25 D 4.80 5.00 E
3.80 4.00
1.27 BSCe
H 5.80 6.20 h
0.25 0.50
L 0.40 1.25
0 7
q
__
MOTOROLA ANALOG IC DEVICE DATA
11
–T–
SEATING PLANE
MC33178 MC33179
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
14 8
B
17
A F
N
SEATING
HG D
PLANE
–A–
14 8
–B–
P 7 PL
71
G
C
D 14 PL
0.25 (0.010) A
K
M
S
B
T
C
K
0.25 (0.010) B
S
L
J
M
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14) ISSUE F
M
X 45
R
_
M
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
4. ROUNDED CORNERS OPTIONAL.
DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L 0.300 BSC 7.62 BSC M 0 10 0 10
____
N 0.015 0.039 0.39 1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
M
F
J
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009
M 0 7 0 7
____
P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019
MILLIMETERSINCHES
INCHESMILLIMETERS
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12
MOTOROLA ANALOG IC DEVICE DATA
MC33178/D
*MC33178/D*
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