Motorola MC145745FW Datasheet

MC145745MOTOROLA

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The MC145745 is a selectable modem chip compatible with ITU V.21 (300 baud full duplex asynchronous) and V.23 mode 2 (1200 baud half duplex asynchronous). The built–in differential line driver has the capability of driving 0 dBm into a 600 Ω load with a 5 V single power supply. This device also includes a DTMF generator, DTMF receiver, call–progress tone detector, answer tone generator, and a receive timing control circuit.

Besides having a clock generator with a crystal oscillator connected to it, the device has a divider circuit to which input of a double frequency clock is possible from external sources, such as from a microcontroller unit (MCU). The serial control port (SCP) permits the MCU to access internal registers for exercising the built–in features.

A low consumption device, the MC145745 integrates various functions in a small package. This modem IC is best suited for telemeter and other applications of this type.

• Conforms to ITU V.21 and V.23 Recommendations

• DTMF Generator and Receiver for all 16 Standard Digits

• Capable of Driving 0 dBm into a 600 Ω Load (VCC = 5 V)

• Automatic Gain Control (AGC) Amplifier for the DTMF Receiver

• Call–Progress Tone Detector

• Four–Wire Serial Data Interface (SCP)

• Programmable Transmission and Carrier Detection Levels

• FSK/DTMF Analog Loopback Self–Test Function

• Crystal Oscillator (3.579545 MHz) and Half Divider Circuit (7.159090 MHz)

for External Inputs

• Operates in the Voltage Range of 3.3 – 5.5 V

• Power Down Mode (ICC < 1 µA)

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

Order this document

by MC145745/D

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SEMICONDUCTOR TECHNICAL DATA

PIN ASSIGNMENT



FW SUFFIX

SOIC

CASE 751M

ORDERING INFORMATION

MC145745FW SOIC

11 12 13 14

18 17 16 15

GND

ref

CDA

TLA

TEST 1

RxD TxD

CLKO

X1 X2

ECLK

PB0

GND

RxA TxA1 TxA2 TEST 2 SCPEN SCPCLK SCP Rx SCP Tx RESET PB3 PB2 PB1 V

 Motorola, Inc. 1996

REV 0 7/96

MC145745 MOTOROLA 2

BLOCK DIAGRAM

RxA

CDA

ref

TxA2 TxA1

CLKO

PB0 – PB3

TxD

RxD

RESET

X1 X2 ECLK TLA VCCGND SCP Tx SCP Rx SCPEN SCPCLK

Rx AMP

AND AGC

CONTROL

LOOPBACK

PATH

SMOOTHING

FILTER

AND

Tx GAIN

CONTROL

TONE

GENERATOR

ANTI–ALIAS

AND

LOW–PASS

FILTER

CLOCK

GENERATOR

1/2

DTMF

RECEIVER

CPT

DETECTOR

FSK

CARRIER

DETECTOR

FSK V.21

MODEM

FSK V.23

MODEM

– +

TIMING

CONTROL

CIRCUIT

MC145745MOTOROLA

PIN DESCRIPTIONS

Location

Symbol Type Description

1, 14 GND — Ground — These are the ground pins of the digital and the analog circuits. The 0 V potential of the

device is determined by the input voltage at these pins.

2 V

ref

— Reference Analog Ground — This pin provides the analog ground voltage VCC/2, which is regulated

internally . This pin should be decoupled to GND with 0.1 µF and 100 µF capacitors.

3 CDA — Carrier Detect Level Adjustment — The detection level for FSK/call–progress tone is determined

according to the voltage at this pin. When VCC = 5 V and the carrier detection level bit (BR3:b1) of the SCP register is 0, or when VCC = 3.6 V and (BR3:b1) is 1, the CDA voltage is set to 1.25 V by the internal divider. This voltage sets the detection levels at ON to OFF: – 44 dBm (typ) and OFF to ON: – 47 dBm (typ). This high impedance pin should be decoupled to GND with a 0.1 µF capacitor. The carrier detection level is proportional to the terminal voltage at this pin. An external voltage may be applied to this pin to adjust the carrier detect threshold. The following equations may be used to find the CDA voltage requirements for a given threshold voltage.

CDA

= 256 x V

CDA

= 362 x V

off

4 TLA — Transmit Level Adjustment — This pin is used to adjust the transmit carrier level which is determined

by the resistor (RTLA) connected between this pin and GND. The maximum level is obtained when this pin is shorted to GND (RTLA = 0).

5, 24 TEST 1,

TEST 2

I/O Test Pins 1 and 2 — These test pins are for manufacturer’s use only. These pins should be left open in

normal operation.

6 RxD O Receive Data Output — This pin is the receive data output. When the device is in the FSK mode, logic

high on this pin indicates that the mark carrier frequency has been received from RxA, and the logic low indicates that the space carrier frequency has been received.

7 TxD I Transmit Data Input — This pin is the transmit data input. When the device is in the FSK mode, logic

high on this pin generates the mark frequency at TxA1 and TxA2 output, and logic low generates the space frequency.

8 CD O Carrier Detect Output — This pin outputs at low level if a valid FSK, DTMF, or CPTD signal is

received. If the pin is at high level, the receive data output pin (RxD) is internally clamped at high level to avoid erroneous output of received data caused by line noise.

9 CLKO O Clock Output — This pin provides a buffered 3.58 MHz clock output that can drive one CMOS device

such as the MC74HC04.

10 X1 O Crystal Oscillator Circuit Output — A 3.579545 MHz ± 0.1% crystal oscillator is tied to this pin with the

other end connected to X2.

11 X2 I Crystal Oscillator Circuit Input — A 3.579545 MHz ± 0.1% crystal oscillator is tied to this pin with the

other end connected to X1. X2 may be driven directly from an appropriate external clock source.

12 ECLK I External Clock Input — ECLK is the input of double frequency, 7.159090 MHz ± 0.1%, of the reference

clock. This pin must be connected to GND when not in use.

13 PB0 O DTMF Receive Data Parallel Output 0 (LSB) — Pins 13, 16, 17, and 18 are the DTMF receive data

parallel output occurring together with the CD

(Pin 8) data valid output. The outputs of these pins are

valid as long as the CD

pin is low. In power down modes 1 and 2, the DTMF receiver is disabled and

these pins are in high impedance.

15, 28 V

— Positive Power Supply — These are the power supply pins for the digital and the analog circuits.

These pins should be decoupled to GND with 0.1 µF and 100 µF capacitors.

—

16, 17, 18

PB1, PB2

DTMF Receive Data Parallel Outputs 1, 2, and 3 (MSB)

—

These pins are the DTMF receiver data

PB3

parallel outputs. See pin 13 for more details.

19 RESET I Reset — A high to low trigger pulse applied to this pin sets all the registers in the default state. It

should remain at high during normal operations. 20 SCP Tx O SCP Output Transmit — Refer to Serial Control Port (SCP Interface) for additional information. 21 SCP Rx I SCP Receive Input — Refer to Serial Control Port (SCP Interface) for additional information. 22 SCPCLK I SCP Clock — Refer to Serial Control Port (SCP Interface) for additional information. 23 SCPEN I SCP Enable — Refer to Serial Control Port (SCP Interface) for additional information.

MC145745 MOTOROLA 4

PIN DESCRIPTIONS (continued)

Location

DescriptionTypeSymbol

25 TxA2 O Transmit Buffer Output 2 (Inverting) — This pin is the inverting output of the line driver. When VCC =

5 V , + 7 dBm (typ), differential output voltage (V

TxA1

– V

TxA2

), can be obtained with a load of 1.2 kΩ between pins TxA1 and TxA2. In typical applications, the output level on the telephone line will be half of the differential output (refer to Application Circuit).

26 TxA1 O Transmit Buffer Output 1 (Non–Inverting) — This pin is the non–inverting output of the line driver.

Refer to TxA2.

27 RxA I Receive Signal Input — This pin is the analog signal input which has 500 kΩ input resistance (typ).

ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit

DC Supply Voltage V

– 0.5 to + 7.0 V

DC Input Voltage V

– 0.5 to VCC + 0.5 V

DC Output Voltage V

out

– 0.5 to VCC + 0.5 V

DC Input Current I

± 20 mA

DC Output Current I

out

± 25 mA

Power Dissipation P

500 mW

Storage Temperature Range T

stg

– 65 to + 150 °C

RECOMMENDED OPERATIONAL CONDITIONS

Parameter Symbol Min Typ Max Unit

DC Supply Voltage V

3.3 5.0 5.5 V

DC Input Voltage V

0 — V

DC Output Voltage V

out

0 — V

Crystal Oscillation Frequency f

osc

— 3.579545 — MHz External Input Frequency (ECLK) — 7.15909 — Operating Temperature Range T

– 30 25 + 85 °C

DC ELECTRICAL CHARACTERISTICS (V

= + 3.3 to + 5.5 V, TA = – 30 to + 85°C)

Characteristic

Symbol Conditions Min Typ Max Unit

Input Voltage (TxD, ECLK, RESET

High Level V

0.7 x V

— —

(

SCP Rx, SCPCLK, SCPEN

)

Low Level V

— — 1.1

Output Voltage

High Level V

Vin = VIH or VIL, I

out

= 20 µA VCC – 0.1 VCC – 0.01 — (RxD, CD, CLKO, PB0–3, SCP Tx)

Low Level V

Vin = VIH or V

out

= 20 µA

out

= 2 mA

— —

0.01 —

0.1

0.4

Input Leakage Current (TxD, ECLK, RESET

, SCP Rx,

SCPCLK, SCPEN

)

Vin = VCC or GND — ± 1.0 ± 10.0 µA

Quiescent Supply Current

VCC = 5 V I

FSK Mode, RTLA = 0 TxA1 and TxA2 open

— 7 —

DTMF Receive Mode, no input — 9 —

VCC = 3.6 V I

FSK Mode, RTLA = 0 TxA1 and TxA2 open

— 6 —

DTMF Receive Mode, no input — 8 —

Power–Down Supply Current I

Power–Down Mode 1 — — 500 µA Power–Down Mode 2 — — 1.0 µA

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, it is recommended that Vin and V

out

be constrained to the range GND v (Vin or

out

) v VCC.

Reliability of operation is enhanced if unused logic inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC).

MC145745MOTOROLA

AC ELECTRICAL CHARACTERISTICS

(VCC = + 3.6 V ± 0.3 V, TA = – 30 to + 85_C)

TRANSMIT CARRIER CHARACTERISTICS

Characteristic Symbol Conditions Min Typ Max Unit

V .21 Carrier Frequency

Mark “1” f

Oscillation Frequency:

974 980 986

Originate Mode

Space “0” f

3.579545 MHz (X2) or 7.159090 MHz (ECLK)

1174 1180 1186

V .21 Carrier Frequency

Mark “1” f

or 7.159090 MHz (ECLK)

1644 1650 1656

Answer Mode

Space “0” f

1844 1850 1856

V .23 Carrier Frequency

Mark “1” f

1294 1300 1306

Space “0” f

2094 2100 2106

Transmit Carrier Level V

Transmit Attenuator = 0 dB

— 4 — dBm

Secondary Harmonic Level V

RTLA = 0, RL = 1.2 kΩ V

TxA1

– V

TxA2

— – 40 — dB

Out–of–Band Level V

TxA1

TxA2

Refer to Figure 1 dBm

TRANSMIT ATTENUATOR CHARACTERISTICS

Characteristic Symbol Conditions Min Typ Max Unit

Attenuation Range 0 — 15 dB Attenuator Accuracy 1 – 5 dB

6 – 9 dB

10 – 15 dB

– 0.5

– 1

– 1.7

— — —

0.5 1 1

RECEIVER CHARACTERISTICS (Includes Hybrid, Demodulator , and Carrier Detector)

Characteristic Symbol Conditions Min Typ Max Unit

Input Resistance R

IRX

50 500 — kΩ

Receive Carrier Amplitude V

IRX

– 48 — – 12 dBm

Carrier Detection

OFF to ON V

CDON

CDA = 1.25 V

— – 44 —

dBm

Threshold

ON to OFF V

CDOFF

fin = 1.0 kHz BR3 (b1) = 1

— – 47 —

Hysteresis (V

CDON

– V

CDOFF

) H

BR3 (b1) = 1

2 — — dB

Carrier Detection Timing OFF to ON T

CDON

CD1 = 0, CD0 = 0, CD Pin — 450 — ms CD1 = 0, CD0 = 1, CD Pin — 15 — CD1 = 1, CD0 = 0, CD Pin — 15 — CD1 = 1, CD0 = 1, CD Pin — 75 —

ON to OFF T

CDOFF

CD1 = 0, CD0 = 0, CD Pin — 30 — CD1 = 0, CD0 = 1, CD Pin — 30 — CD1 = 1, CD0 = 0, CD Pin — 15 — CD1 = 1, CD0 = 1, CD Pin — 10 —

CPTD CHARACTERISTICS

Characteristic Symbol Conditions Min Typ Max Unit

BPF Center Frequency f

— 400 — Hz

BPF Pass–Band Lower Cut–Off Frequency

– 3 dB — 330 — Hz

BPF Pass–Band Upper Cut–Off Frequency

– 3 dB — 470 — Hz

CPT Detection Level

VTD ON V

TDON

CDA = 1.25 V

— – 44 —

dBm

VTD OFF V

TDOFF

fin = 400 Hz BR3 (b1) = 1

— – 47 —

CPT Detection Timing

TTD ON T

TDON

BR3 (b1) = 1

— 10 —

TTD OFF T

TDOFF

— 25 —

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