Motorola MC145425DW, MC145425P, MC145421DW, MC145421P Datasheet
MC145421•MC145425MOTOROLA
1
(UDLT II)
The MC145421 and MC145425 UDLTs are high–speed data transceivers
capable of providing 160 kbps full–duplex data communication over 26 AWG
and larger twisted–pair cable up to 1 km in length. These devices are primarily
used in digital subscriber voice and data telephone systems. In addition, the
devices meet and exceed the CCITT recommendations for data transfer rates
of ISDNs on a single twisted pair. The devices utilize a 512 kbaud MDPSK burst
modulation technique to supply the 160 kbps full–duplex data transfer rates.
The 160 kbps rate is provided through four channels. There are two B channels,
which are 64 kbps each. In addition, there are two D channels which are
16 kbps each.
The MC145421 and MC145425 UDL Ts are designed for upward compatibility
with the existing MC145422 and MC145426 80 kbps UDLTs, as well as compa–
tibility with existing and evolving telephone switching hardware and software
architectures.
The MC145421 (Master) UDLT is designed for use at the telephone switch
line card while the MC145425 (Slave) UDLT is designed for use at the remote
digital telset or data terminal.
• Employs CMOS Technology in Order to Take Advantage of Its Proven
Capability for Complex Analog and Digital LSI Functions
• Provides Synchronous Full–Duplex 160 kbps Voice and Data
Communication in a 2B+2D Format for ISDN Compatibility
• Provides the CCITT Basic Access Data Transfer Rate (2B+D) for ISDNs
on a Single Twisted Pair Up to 1 km
• Compatible with Existing and Evolving Telephone Switch Architectures and
Call Signaling Schemes
• Protocol Independent
• Single + 5 V Power Supply
• MC145421EVK is Available
16 kbps D2
64 kbps B1
64 kbps B2
16 kbps D1
16 kbps D2
64 kbps B1
64 kbps B2
TWISTED PAIR
WIRE
≤
1 km
MASTER
ISDN UDLT
160 kbps FULL–DUPLEX
DATA TRANSMISSION
SLAVE
ISDN UDLT
16 kbps D1
Order this document
by MC145421/D
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC PACKAGE
CASE 709
DW SUFFIX
SOG PACKAGE
CASE 751F
ORDERING INFORMATION
MC145421P Plastic Package
MC145425P Plastic Package
MC145421DW SOG Package
MC145425DW SOG Package
24
1
24
1
Motorola, Inc. 1995
REV 2 (Replaces ADI1251)
9/95
MC145421•MC145425 MOTOROLA
2
PIN ASSIGNMENTS
D1I
LB
LI
V
ref
V
SS
DCLK
D2I
VD RE2
Rx
LO2
LO1
V
DD
TE1
MSI
CCI
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
13
11
12
21
22
23
24
Tx
TE2
TDC/RDC
RE1
SE
PD
D2O
D1O
MC145421 — MASTER
(PLASTIC AND SOG PACKAGES)
D1I
LB
LI
V
ref
V
SS
DCLK
D2I
VD BCLK
Rx
LO2
LO1
V
DD
EN1
TONE
CCI
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
13
11
12
21
22
23
24
Tx
EN2
XTL
CLKOUT
Mu/A
PD
D2O
D1O
MC145425 — SLAVE
(PLASTIC AND SOG PACKAGES)
MC145421•MC145425MOTOROLA
3
23
22
4
11
16
17
12
5
3
2
MODULATOR
B1
B1
B1
B1
B2
B2
B2
B2
D1
D1
D1
D1
D2
D2
D2
LO1
LO2
LB
SE
MSI
CCI
PD
VD
LI
V
ref
DEMODULATOR
SEQUENCE
AND
CONTROL
8 8 2 2
8
8
2
2
B CHANNEL BUFFERS
B CHANNEL BUFFERS
D CHANNEL BUFFERS
7
6
20
21
19
10
8
18
13
15
14
D2I
D1I
RE2
Rx
RE1
D2O
D1O
TDC/RDC
Tx
TE1
TE2
D CHANNEL BUFFERS
+
–
DCLK
9
D2
MC145421 MASTER ISDN BLOCK DIAGRAM
B1
B1
B1
B1
B2
B2
B2
B2
D1
D1
D1
D1
D2
D2
D2
D2
LO1
LO2
CCI
LB
PD
VD
LI
V
ref
XTL
Mu/A
TONE
23
22
17
18
4
11
16
19
5
3
2
MODULATOR
OSC
DEMODULATOR
SEQUENCE
AND
CONTROL
8 8 2 2
2
2
÷
2
8
8
B CHANNEL BUFFERS
B CHANNEL BUFFERS
D CHANNEL BUFFERS
D CHANNEL BUFFERS
7
6
10
8
9
20
13
15
14
21
D2I
D1I
Rx
D2O
DCLK
D1O
Tx
BCLK
EN1
EN2
+
–
12
CLKOUT
MC145425 SLAVE ISDN BLOCK DIAGRAM
MC145421•MC145425 MOTOROLA
4
ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to V
SS
)
Rating
Symbol Value Unit
DC Supply Voltage VDD – V
SS
– 0.5 to 6.5 V
Voltage Any Pin to V
SS
V – 0.5 to VDD + 0.5 V
DC Current, Any Pin (Excluding VDD,
VSS)
I ± 10 mA
Operating Temperature T
A
– 40 to + 85 °C
Storage Temperature T
stg
– 85 to + 150 °C
RECOMMENDED OPERATING CONDITIONS (T
A
= – 40 to + 85°C)
Parameter
Pins Min Typ Max Unit
DC Supply Voltage V
DD
4.5 5.0 5.5 V
Frame Rate MC145421 (See Note) MSI — 8.0 — kHz
MC145421/25 Frame Slip Rate (See Note) — — — 0.25 %
CCI Clock Frequency — — 8.192 8.29 MHz
TDC/RDC Data Clocks (for Master) — 0.128 — 4.1 MHz
DCLK — 0.016 — 4.1 MHz
Modulation Baud Rate (CCI/16) LO1, LO2 — 512 — kHz
NOTE: The slave’s crystal frequency divided by 1024 must equal the master’s MSI frequency ± 0.25% for optimum operation. Also, the
8.192 MHz input at the master divided by 1024 must be within 0.048% of the master’s 8 kHz MSI clock frequency.
DIGITAL CHARACTERISTICS (V
DD
= 5 V, TA = – 40 to + 85°C)
Parameter
Min Max Unit
Input High Level 3.5 — V
Input Low Level — 1.5 V
Input Current, V
DD
— 15 mA
Input Current (Digital Pins) — 5 µA
Input Capacitance — 10 pF
Output High Current (Except Tx on Master and Slave, and PD on the Slave) VOH = 2.5
VOH = 4.6
– 1.7
– 0.36
—
—
mA
Tx Output High Current VOH = 2.5
VOH = 4.6
– 3.4
– 0.7
—
—
mA
PD (Slave) Output High Current (See Note) VOH = 2.5 — – 90 µA
Output Low Current (Except Tx on Master and Slave, and PD on Slave) VOL = 0.4
VOL = 0.8
0.36
0.8
—
—
mA
Tx Output Low Current VOL = 0.4
VOL = 0.8
1.7
3.5
—
—
mA
PD (Slave) Output Low Current (See Note) VOL = 0.4 30 60 µA
Tx Three–State Impedance 100 — kΩ
XTL Output High Current VOH = 4.6 — – 450 µA
XTL Output Low Current VOH = 0.4 450 — µA
NOTE: To overdrive PD from a low level to 3.5 V, or a high level to 1.5 V requires a minimum of ± 800 µA drive capability.
ANALOG CHARACTERISTICS (V
DD
= 5 V, TA = 0 to 70°C)
Parameter
Min Max Unit
Modulation Differential Amplitude RL = 880 Ω (LO1 – LO2) 4.6 — Vpeak
Modulation Differential DC Offset — 40 mV
V
ref
Voltage (Typically 9/20 S (VDD – VSS))
2.0 2.5 V
PCM Tone Level – 22 – 18 dBm
Demodulator Input Amplitude 50 — mVpeak
Demodulator Input Impedance (LI to V
ref
) 75 300 kΩ
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taken to
avoid applications of any voltage higher than
maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and V
out
be constrained to
the range VSS ≤ (Vin or V
out
) ≤ VDD. Reliability
of operation is enhanced if unused inputs are
tied to an appropriate logic voltage level (e.g.,
either VSS or VDD).
MC145421•MC145425MOTOROLA
5
MC145421 MASTER PIN DESCRIPTIONS
V
DD
Positive Supply (Pin 24)
The most positive power supply pin, normally + 5 V with
respect to VSS.
V
SS
Negative Supply (Pin 1)
The most negative supply pin and logic ground, normally
0 V.
V
ref
Reference Output (Analog Ground) (Pin 2)
This pin is the output of the internal reference supply and
should be bypassed to VDD and VSS with 0.1 µF capacitors.
This pin usually serves as an analog ground reference for
transformer coupling of the device’s incoming bursts from the
line. No external dc load should be placed on this pin.
LI
Line Input (Pin 3)
This pin is an input to the demodulator for the incoming
bursts. The input has an internal 240 k
Ω resistor tied to the
V
ref
pin, so an external capacitor or line transformer may be
used to couple the input signal to the device with no dc offset.
LO1, LO2
Line Driver Outputs (Pins 23, 22)
These push–pull outputs drive the twisted pair transmission line with a 512 kHz modified DPSK (MDPSK) burst each
125 µs, in other words at an 8 kHz rate. When not modulating
the line, these pins are driven to the active high state —
being the s ame potential, they create a n ac short. When
used in conjunction with feed resistors, proper line termination is maintained.
SE
Signal Enable Input (Pin 11)
At the time of a negative transition on this pin, an internal
latch stores the states of LB
and PD for as long as SE is held
low. During this time, the VD, DO1, and DO2 outputs are
driven to the high–impedance state. When SE is high, all
pins function normally.
LB
Loopback Control (Pin 4)
A low level on this pin ties the internal modulator output to
the internal demodulator input, which loops the entire burst
for testing purposes. During the loopback operation, the LI
input is ignored and the LO1 and LO2 drivers are driven to
the active high level. The state of this pin is internally latched
if the SE pin is held low. This feature is only active when the
PD
input is high.
PD
Power–Down Input (Pin 12)
When held low the ISDN UDLT powers down, except the
circuitry that is necessary to demodulate an incoming burst
and to output VD, B, and D channel data bits. When PD is
brought high, the ISDN UDLT powers up. Then, it begins
transmitting every MSI period to the slave device, shortly
after the rising edge of MSI. The state of this pin is latched if
the SE pin is held low.
VD
Valid Data Output (Pin 5)
A high level on this pin indicates that a valid line transmission has been demodulated. A valid transmission burst is
determined by proper synchronization and the absence of
detected bit errors. VD changes state on the rising edge of
MSI when PD
is high. When PD is low, VD changes state at
the end of demodulation of a transmission burst and does not
change again until three MSI rising edges have occurred, at
which time it goes low, or until the next demodulation of a
burst. VD is a standard B–series CMOS output and is high
impedance when SE is low.
MSI
Master Sync Input (Pin 16)
This pin is the master, 8 kHz frame reference input. The
rising edge of MSI loads B and D channel data which had
been input during the previous frame into the modulator section of the device and initiates the outbound burst onto the
twisted–pair cable. The rising edge of MSI also initiates the
buffering of the B and D channel data demodulated during
the previous frame. MSI should be approximately leading
edge aligned with the TDC/RDC data clock input pin.
CCI
High–Speed Clock Input (Pin 17)
An 8.192 MHz clock should be supplied to this input. The
8.192 MHz input should be 50% duty cycle. However, it may
free–run with respect to all other clocks without performance
degradation.
D1I, D2I
D Channel Signaling Bit Inputs (Pins 6, 7)
These inputs are 16 kbps serial data inputs. Two bits
should be clocked into each of these inputs between the rising edges of the MSI frame reference clock. The first bit of
each D channel is clocked into an intermediate buffer on the
first falling edge of the DCLK following the rising edge of MSI.
The second bit of each D channel is clocked in on the next
negative transition of the DCLK. If further DCLK negative
edges occur, new information is serially clocked into the buffer replacing the previous data one bit at a t ime. Buffered
D channel data bits are burst to the slave device on the next
rising edge of the MSI frame reference clock.
D1O, D2O
D Channel Signal Outputs (Pins 9, 10)
These serial outputs provide the 16 kbps D channel signaling information from the incoming burst. T wo data bits should
be clocked out of each of these outputs between the rising
edges of the MSI frame reference clock. The rising edge of
MSI produces the first bit of each D channel on its respective
pin. Circuitry then searches for a negative D channel clock
edge. This tells the D channel data shift register to produce
the second D channel b it on the next rising e dge of the
DCLK. Further positive edges of the DCLK recirculate the
D channel output buffer information.
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