Datasheet MC14532BD, MC14532BDR2, MC14532BF, MC14532BFEL, MC14532BFR1 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14532B/D

MC14532B

8-Bit Priority Encoder

The MC14532B is constructed with complementary MOS (CMOS)
enhancement mode devices. The primary function of a priority
encoder is to provide a binary address for the active input with the
highest priority. Eight data inputs (D0 thru D7) and an enable input
(E

in)

are provided. Five outputs are available, three are address outputs

(Q0 thru Q2), one group select (GS) and one enable output (E

out

).

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–Power

Schottky TTL Load over the Rated Temperature Range

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note 3.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

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A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14532BCP PDIP–16 2000/Box
MC14532BD SOIC–16 48/Rail
MC14532BDR2 SOIC–16 2500/Tape & Reel

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

MARKING

DIAGRAMS

1

16

PDIP–16

P SUFFIX

CASE 648

MC14532BCP

AWLYYWW

SOIC–16

D SUFFIX

CASE 751B

1

16

14532B

AWLYWW

SOEIAJ–16

F SUFFIX

CASE 966

1

16

MC14532B

AWLYWW

MC14532BFEL SOEIAJ–16 See Note 1.

MC14532BF SOEIAJ–16 See Note 1.

MC14532BFR1 SOEIAJ–16 See Note 1.

MC14532B

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2

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

D2

D3

GS

E

out

V

DD

Q0

D0

D1

D7

D6

D5

D4

V

SS

Q1

Q2

E

in

TRUTH TABLE

Input Output

EinD7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0 E

out

0 X X X X X X X X 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 1

1 1 X X X X X X X 1 1 1 1 0
1 0 1 X X X X X X 1 1 1 0 0
1 0 0 1 X X X X X 1 1 0 1 0
1 0 0 0 1 X X X X 1 1 0 0 0

1 0 0 0 0 1 X X X 1 0 1 1 0
1 0 0 0 0 0 1 X X 1 0 1 0 0
1 0 0 0 0 0 0 1 X 1 0 0 1 0
1 0 0 0 0 0 0 0 1 1 0 0 0 0

X = Don’t Care

MC14532B

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C 25_C 125_C

Characteristic Symbol

V

DD

Vdc

Min Max Min Typ

(4.)

Max Min Max

Unit

Output Voltage “0” Level

V

in

= VDD or 0

V

OL

5.0
10
15

—
—
—

0.05

0.05

0.05

—
—
—

0
0
0

0.05

0.05

0.05

—
—
—

0.05

0.05

0.05

Vdc

“1” Level

V

in

= 0 or V

DD

V

OH

5.0
10
15

4.95

9.95

14.95

—
—
—

4.95

9.95

14.95

5.0
10
15

—
—
—

4.95

9.95

14.95

—
—
—

Vdc

Input Voltage “0” Level

(V

O

= 4.5 or 0.5 Vdc)

(V

O

= 9.0 or 1.0 Vdc)

(V

O

= 13.5 or 1.5 Vdc)

V

IL

5.0
10
15

—
—
—

1.5

3.0

4.0

—
—
—

2.25

4.50

6.75

1.5

3.0

4.0

—
—
—

1.5

3.0

4.0

Vdc

“1” Level

(V

O

= 0.5 or 4.5 Vdc)

(V

O

= 1.0 or 9.0 Vdc)

(V

O

= 1.5 or 13.5 Vdc)

V

IH

5.0
10
15

3.5

7.0
11

—
—
—

3.5

7.0
11

2.75

5.50

8.25

—
—
—

3.5

7.0
11

—
—
—

Vdc

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

I

OH

5.0

5.0
10
15

– 3.0

– 0.64

– 1.6
– 4.2

—
—
—
—

– 2.4

– 0.51

– 1.3
– 3.4

– 4.2
– 0.88
– 2.25

– 8.8

—
—
—
—

– 1.7

– 0.36

– 0.9
– 2.4

—
—
—
—

mAdc

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

I

OL

5.0
10
15

0.64

1.6

4.2

—
—
—

0.51

1.3

3.4

0.88

2.25

8.8

—
—
—

0.36

0.9

2.4

—
—
—

mAdc

Input Current I

in

15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance

(V

in

= 0)

C

in

— — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package)

I

DD

5.0
10
15

—
—
—

5.0
10
20

—
—
—

0.005

0.010

0.015

5.0
10
20

—
—
—

150
300
600

µAdc

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

L

= 50 pF on all outputs, all

buffers switching)

I

T

5.0
10
15

IT = (1.74 µA/kHz) f + I

DD

IT = (3.65 µA/kHz) f + I

DD

IT = (5.73 µA/kHz) f + I

DD

µAdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

T

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005.

MC14532B

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4

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, T

A

= 25_C)

Characteristic

Symbol V

DD

Min Typ

(8.)

Max Unit

Output Rise and Fall Time

t

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

t

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

t

TLH

,

t

THL

5.0
10
15

—
—
—

100

50
40

200
100

80

ns

Propagation Delay Time — Ein to E

out

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 120 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 77 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 55 ns

t

PLH

,

t

PHL

5.0
10
15

—
—
—

205
110

80

410
220
160

ns

Propagation Delay Time — Ein to GS

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 90 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL 57 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 40 ns

t

PLH

,

t

PHL

5.0
10
15

—
—
—

175

90
65

350
180
130

ns

Propagation Delay Time — Ein to Q

n

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 195 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 107 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

t

PHL

,

t

PLH

5.0
10
15

—
—
—

280
140
100

560
280
200

ns

Propagation Delay Time — Dn to Q

n

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 265 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 137 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 85 ns

t

PLH

,

t

PHL

5.0
10
15

—
—
—

300
170
110

600
340
220

ns

Propagation Delay Time — Dn to GS

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 195 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 107 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

t

PLH

,

t

PHL

5.0
10
15

—
—
—

280
140
100

560
280
200

ns

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Output

Under

VGS = V

DD

VDS = V

out

Sink Current

VGS = – V

DD

VDS = V

out

– V

DD

Source Current

Under

Test

D0 thru D7 EinD0 thru D6 D7 E

in

E

out

X 0 0 0 1

out

Q0 X 0 0 1 1
Q1

X

0

0

1

1

Q2

X

0

0

1

1

GSX001

1

Figure 1. Typical Sink and Source

Current Characteristics

Figure 2. Typical Power Dissipation Test Circuit

SWITCH
MATRIX

EXTERNAL

POWER
SUPPLY

I

D

E

in

D0
D1

D2
D3
D4
D5
D6
D7

GS

Q2

Q1

Q0

E

out

V

out

PULSE

GENERATOR

(f

o

)

E

in

D0
D1

D2
D3
D4
D5
D6
D7

V

SS

V

DD

I

D

C

L

C

L

C

L

C

L

C

L

GS

Q2

Q1

Q0

E

out

0.01 µF

500 µF

MC14532B

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5

Figure 3. AC Test Circuit and Waveforms

PROGRAMMABLE

PULSE

GENERATOR

E

in

D0
D1

D2
D3
D4
D5
D6
D7

GS

Q2

Q1

Q0

E

out

V

DD

V

SS

C

L

C

L

C

L

C

L

C

L

NOTE: Input rise and fall times are 20 ns

50%

50%

50%

50%

50%

50%

50%

50%

90%

50%

10%

90%

50%

10%

90%

50%

10%

90%

50%

10%

t

PHL

t

PHL

t

PHL

t

PHL

t

PHL

t

THL

t

THL

t

THL

t

THL

t

PLH

t

PLH

t

PLH

t

PLH

t

PLH

t

PLH

t

PLH

t

TLH

t

TLH

t

TLH

t

TLH

t

TLH

t

PHL

t

PLH

t

THL

90%

50%

10%

t

PLH

t

PHL

t

PHL

t

PHL

D0

D1

D2

D3

D4

D5

D6

D7

E

in

E

out

GS

Q0

Q1

Q2

10

11

12

13

1

2

3

4

5

15

14

9

7

6

PIN

NO.

50%

MC14532B

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6

LOGIC DIAGRAM

(Positive Logic)

LOGIC EQUATIONS

E

out

= Ein  D0  D1  D2  D3  D4  D5  D6  D7

10

11

12

13

1

2

3

4

5

D0

D1

D2

D3

D4

D5

D6

D7

E

in

9

7

6

14

15

Q0

Q1

Q2

GS

E

out

Q0 = Ein  (D1  D2  D4  D6 + D3  D4  D6 + D5  D6 + D7)
Q1 = E

in

 (D2  D4  D5 + D3  D4  D5 + D6 + D7)

Q2 = E

in

 (D4 + D5 + D6 + D7)

GS = E

in

 (D0 + D1 + D2 + D3 + D4 + 05 + D6 + D7)

MC14532B

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7

Figure 4. Two MC14532B’s Cascaded for 4–Bit Output

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Q1 Q0Q2 Q1 Q0Q2

Q1 Q0Q2Q3

GS

3/4 MC14071B

V

DD

E

in

E

out

E

in

E

out

E

out

= “1”

WITH D

in

= “0”

Figure 5. Digital to Analog and Analog to Digital Converter

DIGITAL TO ANALOG CONVERSION

The digital eight–bit word to be converted is applied to the
inputs of the MC14512 with the most significant bit at
X7 and the least significant bit at X0. A clock input of up to

2.5 MHz (at VDD = 10 V) is applied to the MC14520B.
A compromise between I

bias

for the MC1710 and ∆R

between N and P–channel outputs gives a value of R of
33 k ohms. In order to filter out the switching frequencies,
RC should be about 1.0 ms (if R = 33 k ohms, C [ 0.03 µF).
The analog 3.0 dB bandwidth would then be dc to 1.0 kHz.

ANALOG TO DIGITAL CONVERSION

An analog signal is applied to the analog input of the
MC1710. A digital eight–bit word known to represent a dig­itized level less than the analog input is applied to the
MC14512 as in the D to A conversion. The word is increm­ented at rates sufficient to allow steady state to be reached
between incrementations (i.e. 3.0 ms). The output of the
MC1710 will change when the digital input represents the
first digitized level above the analog input. This word is the
digital representation of the analog word.

ANALOG
OUTPUT

CLOCK

INPUT

ANALOG

INPUT

V

DD

X7 X6 X5 X4 X3 X2 X1 X0

MC14512

A
B
C

MC1710

R

C

Z

V

DD

V

SS

E

in

D0 D1 D2 D3 D4 D5 D6 D7

Q2 Q0Q1

STOP
WORD
INCREMENTATION

Q2 Q4Q3Q1 Q2 Q4Q3Q1

CE RCE R

1/2 MC14520B 1/2 MC14520B

DIGITAL INPUT/OUTPUT

8–BIT WORD

TO BE CONVERTED

MC14532B

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8

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74

M 0 10 0 10

S 0.020 0.040 0.51 1.01

____

MC14532B

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9

P ACKAGE DIMENSIONS

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

____

MC14532B

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10

P ACKAGE DIMENSIONS

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035
––– 0.78 ––– 0.031

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005)

0.10 (0.004)

1

16 9

8

D

Z

E

A

b
c
D
E
e

L

M

Z

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

MC14532B

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11

Notes

MC14532B

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12

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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
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Phone: [phone] (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

T oll Free from Hong Kong & Singapore:

001–800–4422–3781

Email: ONlit–[e-mail]

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, T okyo, Japan 141–8549

Phone: [phone]
Email: [e-mail]

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

MC14532B/D

NORTH AMERICA Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA

Phone: [phone] or 800–344–3860 T oll Free USA/Canada
Fax: [phone] or 800–344–3867 Toll Free USA/Canada
Email: [e-mail]

Fax Response Line: 303–675–2167 or 800–344–3810 T oll Free USA/Canada

N. American Technical Support: 800–282–9855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor – European Support

German Phone: [phone] (M–F 1:00pm to 5:00pm Munich Time)

Email: ONlit–[e-mail]

French Phone: [phone] (M–F 1:00pm to 5:00pm Toulouse T ime)

Email: ONlit–[e-mail]

English Phone: [phone] (M–F 12:00pm to 5:00pm UK Time)

Email: [e-mail]

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

*Available from Germany, France, Italy , England, Ireland