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MC141519T
Datasheet
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Motorola MC141519T Datasheet

MCM63Z736DMCM63Z818
1
MOTOROLA FAST SRAM
Advance Information
128K x 36 and 256K x 18 Bit Pipelined ZBT RAM Synchronous Fast Static RAM
Addresses (SA), data inputs (DQ), and all control signals except output enable (G
) and linear burst order (LBO) are clock (CK) controlled through positive–
edge–triggered noninverting registers.
Write cycles are internally self–timed and are initiated by the rising edge of the clock (CK) input. This feature eliminates complex off–chip write pulse generation and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily stored by an edge– triggered output register and then released to the output buffers at the next rising edge of clock (CK).
• 3.3 V LVTTL and LVCMOS Compatible
• MCM63Z736/MCM63Z818–133 = 4.2 ns Access/7.5 ns Cycle (133 MHz)
MCM63Z736/MCM63Z818–100 = 5 ns Access/10 ns Cycle (100 MHz)
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Two–Cycle Deselect
• Byte Write Control
• ADV Controlled Burst
• 100–Pin TQFP Package
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology , Inc. and Motorola, Inc.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Order this document
by MCM63Z736/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM63Z736 MCM63Z818
TQ PACKAGE
TQFP
CASE 983A–01
REV 1 2/6/98
Motorola, Inc. 1998
MCM63Z736DMCM63Z818 2
MOTOROLA FAST SRAM
PIN ASSIGNMENT
71
72
DQc
V
DDQ
DQb
69
70
66
67
68
64
65
61
62
63
3738343536 42433940 41 454644
60 59 58 57 56 55 54 53 52 51
31 3233
74
75
76
77
78
79
80
50494847
DQb
DQb
V
SS
DQb
DQb
DQb
DQb V
SS
V
DDQ
DQb
DQb
V
DDQ
V
SS
V
SS
V
DDQ
DQc
DQc DQc DQc DQc
DQc DQc
SASASE1
SBd
CK
SBc
NC
G
SA0
SASASA
SA
NC
NC
NC
LBO
SA1
V
DD
V
DD
DQa
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DDQ
DQa
DQa V
SS
V
DDQ
DQa
DQa
DQd
V
DD
V
SS
V
SS
V
DDQ
DQd
DQd DQd DQd DQd
73
DQc
94 93979695 89889291 90 8685871009998 81828384
10
9
12
11
15
14
13
17
16
20
19
18
21 22 23 24 25 26 27 28 29 30
7
6
5
4
3
2
1
8
SA
SA
CKE
SE2
SE3
VSSV
DD
V
DDQ
V
SS
DQd DQd DQd
SA
SA
SASASA
SA
SA
NC
V
SS
NC
ADV
SW
SBa
SBb
V
DD
V
DD
V
SS
V
DD
TOP VIEW
MCM63Z736
MCM63Z736DMCM63Z818
3
MOTOROLA FAST SRAM
PIN ASSIGNMENT
71
72
NC
V
DDQ
SA
69
70
66
67
68
64
65
61
62
63
3738343536 42433940 41 454644
60 59 58 57 56
55 54 53
52 51
31 32 33
74
75
76
77
78
79
80
50494847
NC
NC
V
SS
DQa
NC
DQa
DQa V
SS
V
DDQ
DQa
DQa
V
DDQ
V
SS
V
SS
V
DDQ
NC
NC
NC DQb DQb
DQb DQb
SASASE1
NC
CK
NC
NC
G
SA0
SASASA
SA
NC
NC
NC
SA1
V
DD
V
DD
DQa
V
SS
DQa
DQa
NC
DQa
V
SS
V
DDQ
NC
NC V
SS
V
DDQ
NC
NC
DQb
V
DD V
SS
V
SS
V
DDQ
DQb
DQb DQb DQb
NC
73
NC
94 93979695 89889291 90 8685871009998 81828384
10
9
12
11
15
14
13
17
16
20
19
18
21 22 23 24 25 26 27 28 29 30
7
6
5
4
3
2
1
8
SA
SA
CKE
SE2
SE3
VSSV
DD
V
DDQ
V
SS
NC NC NC
SA
SA
SASASA
SA
SA
NC
V
SS
NC
ADV
SW
SBa
SBb
V
DD
V
DD
V
SS
V
DD
TOP VIEW
MCM63Z818
LBO
MCM63Z736DMCM63Z818 4
MOTOROLA FAST SRAM
MCM63Z736 PIN DESCRIPTIONS
Pin Locations Symbol Type Description
85 ADV Input Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
89 CK Input Clock: This signal registers the address, data in, and all control signals
except G
and LBO.
87 CKE Input Clock Enable: Disables the CK input when CKE is high.
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30
DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
86 G Input Asynchronous Output Enable. 31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low. Low – linear burst counter. High – interleaved burst counter.
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 50, 81, 82, 99, 100
SA Input Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37 SA0, SA1 Input Synchronous Burst Address Inputs: The two LSB’s of the address field.
These pins must preset the burst address counter values. These inputs are registered and must meet setup and hold times.
93, 94, 95, 96
(a) (b) (c) (d)
SBx Input Synchronous Byte Write Inputs: Enables write to byte “x”
(byte a, b, c, d) in conjunction with SW
. Has no effect on read cycles. 98 SE1 Input Synchronous Chip Enable: Active low to enable chip. 97 SE2 Input Synchronous Chip Enable: Active high for depth expansion. 92 SE3 Input Synchronous Chip Enable: Active low for depth expansion. 88 SW Input Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx
pins.
14, 15, 16, 41, 65, 66, 91 V
DD
Supply Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77 V
DDQ
Supply I/O Power Supply.
5, 10, 17, 21, 26, 40,
55, 60, 64, 67, 71, 76, 90
V
SS
Supply Ground.
38, 39, 42, 43, 83, 84 NC — No Connection: There is no connection to the chip.
MCM63Z736DMCM63Z818
5
MOTOROLA FAST SRAM
MCM63Z818 PIN DESCRIPTIONS
Pin Locations Symbol Type Description
85 ADV Input Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
89 CK Input Clock: This signal registers the address, data in, and all control signals
except G
and LBO.
87 CKE Input Clock Enable: Disables the CK input when CKE is high.
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24
DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b). 86 G Input Asynchronous Output Enable. 31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low – linear burst counter.
High – interleaved burst counter.
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 50, 80, 81, 82, 99, 100
SA Input Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37 SA0, SA1 Input Synchronous Burst Address Inputs: The two LSB’s of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
93, 94
(a) (b)
SBx Input Synchronous Byte Write Inputs: Enables write to byte “x”
(byte a, b) in conjunction with SW
. Has no effect on read cycles. 98 SE1 Input Synchronous Chip Enable: Active low to enable chip. 97 SE2 Input Synchronous Chip Enable: Active high for depth expansion. 92 SE3 Input Synchronous Chip Enable: Active low for depth expansion. 88 SW Input Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx
pins.
14, 15, 16, 41, 65, 66, 91 V
DD
Supply Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77 V
DDQ
Supply I/O Power Supply.
5, 10, 17, 21, 26, 40,
55, 60, 64, 67, 71, 76, 90
V
SS
Supply Ground.
1, 2, 3, 6, 7, 25, 28, 29, 30,
38, 39, 42, 43, 51, 52, 53, 56, 57,
75, 78, 79, 83, 84, 95, 96
NC — No Connection: There is no connection to the chip.
MCM63Z736DMCM63Z818 6
MOTOROLA FAST SRAM
TRUTH TABLE
CK CKE E SW SBx ADV
SA0 –
SAx
Next Operation
Input Command
Code
Notes
L–H 1 X X X X X Hold H 1, 2 L–H 0 False X X 0 X Deselect D 1, 2 L–H 0 True 0 V 0 V Load Address, New Write W 1, 2, 3,
4, 5 L–H 0 True 1 X 0 V Load Address, New Read R 1, 2 L–H 0 X X
V (W)
1 X
Burst
B 1, 2, 4,
X (R, D) Continue
6, 7
NOTES:
1. X = don‘t care, 1 = logic high, 0 = logic low, V = valid signal, according to AC Operating Conditions and Characteristics.
2. E = true if SE1
and SE3 = 0, and SE2 = 1.
3. Byte write enables, SBx
are evaluated only as new write addresses are loaded.
4. No control inputs except CKE
, SBx, and ADV are recognized in a clock cycle where ADV is sampled high.
5. A write with SBx
not valid does load addresses.
6. A burst write with SBx
not valid does increment address.
7. ADV controls whether the RAM enters burst mode. If the previous cycle was a write, then ADV = 1 results in a burst write. If the previous cycle is a read, then ADV = 1 results in a burst read. ADV = 1 will also continue a deslect cycle.
WRITE TRUTH TABLE
Cycle Type SW SBa SBb
SBc
(See Note 1)
SBd
(See Note 1)
Read H X X X X Write Byte a L L H H H Write Byte b L H L H H Write Byte c (See Note 1) L H H L H Write Byte d (See Note 1) L H H H L Write All Bytes L L L L L
NOTE:
1. Valid only for MCM63Z736.
LINEAR BURST ADDRESS TABLE (LBO = V
SS
)
1st Address (External)
2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X10 X . . . X11 X . . . X00 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X00 X . . . X01 X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = V
DD
)
1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X00 X . . . X11 X . . . X10 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X10 X . . . X01 X . . . X00
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