MOTOROLA MC10SX1226 Technical data

MOTOROLA MC10SX1226 Technical data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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1.25Gb/s Fiber Optic Post

MC10SX1126

Amplifier

 

 

 

The MC10SX1126 is an integrated limiting amplifier for high frequency fiber optic applications. The device interfaces directly to the trans±impedance amplifier of a typical optical to electrical conversion portion of a fiber optic link. With data rate capabilities in the 1.25Gb/s range, the high gain limiting amplification of the SX1126 is ideal for high speed fiber optic applications like SONET/SDM, ATM, FDDI, Fibre Channel or Serial Hippi. The device is functionally and pin compatible to the Signetics SA5225 with a significantly higher bandwidth. The CAZP and CAZN inputs to the limiting amplifier provide an auto-zero function to effectively cancel any input offset voltage present in the amplifier.

The SX1126 incorporates a programmable level detect function to identify when the input signal has been lost. This information can be fed back to the Disable input of the device to maintain stability under loss of signal conditions. Using the Vset pin the sensitivity of the level detect can be adjusted. The CLD input is used to filter the level detect input so that random noise spikes are filtered out.

The MC10SX1126 is compatible with MECL10H logic levels.

Wideband Operation: 50MHz to 900MHz

Programmable Input Signal Level Detection

Operation with single +5V or standard ECL supply

Standard 16-lead SOIC Package

Fully Differential Design to Minimize Noise Affects

10KH Compatible

FIBER OPTIC POST AMPLIFIER

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B-05

 

CAZP CAZN

 

 

Din

 

 

 

 

Limiting

ECL

 

 

Amplifier

Buffer

 

Din

 

 

 

 

 

 

Disable

Vref

Reference

 

 

 

 

Level

ECL

Vset

 

Detect

Buffer

 

 

 

Dout

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vset

Vref VCCE Dout

 

GNDE

 

 

LOS

 

 

 

 

Dout

LOS

 

 

Dout

 

 

16

 

15

 

14

 

13

 

12

 

11

 

10

 

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Disable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

2

 

 

3

 

 

4

 

5

 

 

 

6

 

7

 

8

 

 

 

 

CAZN

CAZP

GNDA

 

Din

 

 

 

 

VCCA

CLD

Disable

LOS

 

 

Din

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2. 16±Lead Pinout

 

 

 

 

LOS

 

 

 

 

 

 

 

 

 

 

(Top View)

 

 

 

 

 

 

 

CLD

Figure 1. MC10SX1126 Block Diagram

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

4/98

Motorola, Inc. 1998

1

REV 0.1

MC10SX1126

FUNCTION TABLE

 

 

Pin

Function

 

 

 

 

 

 

CAZN

Auto-zero capacitor pin. A capacitor between this pin and CAZP cancels any offset inherent to the limiting amplifier.

CAZP

Auto-zero capacitor pin. A capacitor between this pin and CAZN cancels any offset inherent to the limiting amplifier.

GNDA

Analog ground pin. Ground for PECL operation or ±5.2V for standard ECL operation. GNDA and GNDE must be at the same

 

 

 

 

 

potential.

 

 

 

 

 

 

Din,

 

 

 

 

Differential data input.

Din

VCCA

Analog power supply pin. +5V for PECL operation or ground for standard ECL operation. VCCA and VCCE must be at the

 

 

 

 

 

same potential.

 

 

 

 

CLD

Filter capacitor for the level detect comparator. Capacitor should be connected to VCCA.

Disable

When asserted LOW, or left open and pulled LOW via the input pulldown resistor, the output buffer will be enabled and will

 

 

 

 

 

respond to the input stimulus on the Din input. Forcing Disable HIGH will force the Dout output LOW and its complimentary

 

 

 

 

 

output HIGH.

 

 

 

 

LOS

Loss of signal. This output will go HIGH when the input signal falls below (Vset/100) mVP-P.

GNDE

Digital ground pin. Ground for PECL operation or ±5.2V for standard ECL operation. GNDA and GNDE must be at the same

 

 

 

 

 

potential.

 

 

 

 

Dout,

 

 

 

Differential data outputs.

Dout

VCCE

Digital power supply pin. +5V for PECL operation or ground for standard ECL operation. VCCA and VCCE must be at the

 

 

 

 

 

same potential.

 

 

Vref

Reference voltage for threshold level set voltage division network (2.64V).

Vset

Input threshold level detect setting input. Input generated from voltage divider between Vref and GNDA.

 

1

CAZN

Vset

16

 

 

CAZ

 

 

R1

R2

 

2

CAZP

Vref

15

 

 

3

GNDA

VCCE

14

5V

 

Cin

Din

Dout

50

Cbypass

 

4

13

 

DATA IN

Cin

 

 

DATA OUT

 

Din

Dout

 

 

 

5

12

3V

 

 

 

 

50

 

5V

6

VCCA

GNDE

11

 

C

CAZ

 

 

50

 

bypass

 

CLD

LOS

 

 

7

10

 

 

 

 

 

LEVEL

 

 

 

Disable

LOS

DETECT OUT

 

8

9

 

 

 

 

 

50

 

Figure 3. Typical Operating Circuit

MOTOROLA

2

ECLinPS and ECLinPS Lite

 

 

DL140 Ð Rev 3

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