MOTOROLA MC10SX1226 Technical data
SEMICONDUCTOR TECHNICAL DATA
The MC10SX1126 is an integrated limiting amplifier for high
frequency fiber optic applications. The device interfaces directly to the
trans–impedance amplifier of a typical optical to electrical conversion
portion of a fiber optic link. With data rate capabilities in the 1.25Gb/s
range, the high gain limiting amplification of the SX1126 is ideal for high
speed fiber optic applications like SONET/SDM, ATM, FDDI, Fibre
Channel or Serial Hippi. The device is functionally and pin compatible to
the Signetics SA5225 with a significantly higher bandwidth. The C
and C
inputs to the limiting amplifier provide an auto-zero function to
AZN
effectively cancel any input offset voltage present in the amplifier.
The SX1126 incorporates a programmable level detect function to
identify when the input signal has been lost. This information can be fed
back to the Disable input of the device to maintain stability under loss of
signal conditions. Using the V
pin the sensitivity of the level detect
set
can be adjusted. The CLD input is used to filter the level detect input so
that random noise spikes are filtered out.
The MC10SX1 126 is compatible with MECL10H logic levels.
• Wideband Operation: 50MHz to 900MHz
• Programmable Input Signal Level Detection
• Operation with single +5V or standard ECL supply
• Standard 16-lead SOIC Package
• Fully Differential Design to Minimize Noise Affects
• 10KH Compatible
AZP
FIBER OPTIC
POST AMPLIFIER
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
C
AZPCAZN
D
in
Limiting
Amplifier
D
in
V
ref
V
set
Reference
ECL
Buffer
Level
Detect
C
LD
Disable
ECL
Buffer
D
out
D
out
Disable
LOS
LOS
V
set
C
AZNCAZP
Figure 1. MC10SX1126 Block Diagram
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
V
refVCCEDout
1516 14 13 12 11 10
21 34567
GNDADinD
GNDELOS LOS
D
out
inVCCACLD
9
8
Disable
Figure 2. 16–Lead Pinout
(Top View)
4/98
Motorola, Inc. 1998
1
REV 0.1
MC10SX1126
FUNCTION TABLE
Pin Function
C
AZN
C
AZP
GND
A
Din, D
in
V
CCA
C
LD
Disable When asserted LOW, or left open and pulled LOW via the input pulldown resistor , the output buffer will be enabled and will
LOS Loss of signal. This output will go HIGH when the input signal falls below (V
GND
E
D
, D
out
out
V
CCE
V
ref
V
set
Auto-zero capacitor pin. A capacitor between this pin and C
Auto-zero capacitor pin. A capacitor between this pin and C
Analog ground pin. Ground for PECL operation or –5.2V for standard ECL operation. GNDA and GNDE must be at the same
potential.
Differential data input.
Analog power supply pin. +5V for PECL operation or ground for standard ECL operation. V
same potential.
Filter capacitor for the level detect comparator. Capacitor should be connected to V
respond to the input stimulus on the Din input. Forcing Disable HIGH will force the D
output HIGH.
Digital ground pin. Ground for PECL operation or –5.2V for standard ECL operation. GNDA and GNDE must be at the same
potential.
Differential data outputs.
Digital power supply pin. +5V for PECL operation or ground for standard ECL operation. V
same potential.
Reference voltage for threshold level set voltage division network (2.64V).
Input threshold level detect setting input. Input generated from voltage divider between V
cancels any offset inherent to the limiting amplifier.
AZP
cancels any offset inherent to the limiting amplifier.
AZN
and V
/100) mV
set
CCA
.
CCA
output LOW and its complimentary
out
.
P-P
CCA
and GNDA.
ref
and V
CCE
CCE
must be at the
must be at the
DATA IN
5V
C
bypass
C
AZN
C
AZ
C
AZP
GND
A
C
in
C
in
C
AZ
D
in
D
in
V
CCA
C
LD
Disable LOS
Figure 3. T ypical Operating Circuit
V
V
V
CCE
D
D
GND
LOS
set
ref
out
out
161
R1 R2
152
143
134
125
116
E
107
98
50
DATA OUT
50
50
LEVEL
DETECT OUT
50
5V
C
bypass
3V
MOTOROLA ECLinPS and ECLinPS Lite
2
DL140 — Rev 3
Loading...