MOTOROLA MC10E1651 Technical data



SEMICONDUCTOR TECHNICAL DATA

2–1

REV 1

 Motorola, Inc. 1996

12/93

   
 

The MC10E1651 is functionally and pin-for-pin compatible with the
MC1651 in the MECL III family, but is fabricated using Motorola’s
advanced MOSAIC III process. The MC10E1651 incorporates a fixed
level of input hysteresis as well as output compatibility with 10KH logic
devices. In addition, a latch is available allowing a sample and hold
function to be performed. The device is available in both a 16-pin DIP and
a 20-pin surface mount package.

The latch enable (LEN

a

and LENb) input pins operate from standard
ECL 10KH logic levels. When the latch enable is at a logic high level the
MC10E1651 acts as a comparator, hence Q will be at a logic high level if
V1 > V2 (V1 is more positive than V2). Q

is the complement of Q. When
the latch enable input goes to a low logic level, the outputs are latched in
their present state providing the latch enable setup and hold time
constraints are met.

• Typ. 3.0 dB Bandwidth > 1.0 GHz

• Typ. V to Q Propagation Delay of 775 ps

• Typ. Output Rise/Fall of 350 ps

• Common Mode Range –2.0 V to +3.0 V

• Individual Latch Enables

• Differential Outputs

• 28mV Input Hysteresis

Qa

Qa

LEN

a

V2a

V1a

Qb

Qb

LEN

b

V2b

V1b

LOGIC DIAGRAM

VEE = –5.2 V
VCC = +5.0 V

FN SUFFIX

PLASTIC PACKAGE

CASE 775-02



DUAL ECL OUTPUT

COMPARATOR

WITH LATCH

L SUFFIX

CERAMIC PACKAGE

CASE 620-10

FUNCTION TABLE

LEN V1, V2 Function

H
H

L

V1 > V2
V1 < V2

X

H

L

Latched

MC10E1651

MOTOROLA ECLinPS and ECLinPS Lite

DL140 — Rev 4

2–2

Pinout: 20-Lead PLCC (Top View)

Qb

GND

NC

GND

Qa

Qb LEN

b

NC V1b V2b

V

CC

NC

NC

V

EE

V

CC

Qa

LENaNC V2a V1a

Pinout: 16-Pin Ceramic DIP (Top View)

87654321

910111213141516

NCV

CC

V2bV1bLEN

b

QbQbGND

V

EE

V

CC

V1aV2aLEN

a

QaQaGND

19

181317 16 15 14

12

11

10

9

4 5 6 7 8

20

1

2
3

ABSOLUTE MAXIMUM RATINGS (Beyond which device life may be impaired)

Symbol Characteristic Min Typ Max Unit

VSUP Total Supply Voltage

|VEE| + |VCC|

12.0

V

VPP Differential Input Voltage

|V1 – V2|

3.7

V

DC CHARACTERISTICS (VEE = –5.2 V ±5%; VCC = +5.0 V ±5%)

0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit Condition

V

OH

Output HIGH Voltage –1020 –840 –980 –810 –920 –735 mV

V

OL

Output Low Voltage –1950 –1630 –1950 –1630 –1950 –1600 mV

II
I

IH

Input Current (V1, V2)
Input HIGH Current (LEN

)

65

150

65

150

65

150

µA

I

CC

I

EE

Positive Supply Current
Negative Supply Current

50

–55

50

–55

50

–55

mA

VCMR Common Mode Range –2.0 3.0 –2.0 3.0 –2.0 3.0 V
Hys Hysteresis 27 27 30 mV
V

skew

Hysteresis Skew –1.0 –1.0 0 mV 1

C

in

Input Capacitance
DIP
PLCC

3
2

3
2

3
2

pF

1. Hysteresis skew (V

skew

) is provided to indicate the offset of the hysteresis window. For example, at 25°C the nominal hysteresis value is 27mV

and the V

skew

value indicates that the hysteresis was skewed from the reference level by 1mV in the negative direction. Hence the hysteresis
window ranged from 14mV below the reference level to 13mV above the reference level. All hysteresis measurements were determined using
a reference voltage of 0mV.

MC10E1651

2–3 MOTOROLAECLinPS and ECLinPS Lite

DL140 — Rev 4

AC CHARACTERISTICS (V

EE

= –5.2 V ±5%; VCC = +5.0 V ±5%)

0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit Condition

t

PLH

t

PHL

Propagation Delay to Output
V to Q
LEN

to Q

600
400

750
575

900
750

625
400

775
575

925
750

700
500

850
650

1050

850

ps 1

t

s

Setup Time
V

450 300 450 300 550 350

ps

t

h

Enable Hold Time
V

–50 –250 –50 –250 –100 –250

ps

t

pw

Minimum Pulse Width
LEN

400 400 400

ps

t

skew

Within Device Skew 15 15 15 ps 2

T

DE

Delay Dispersion
(ECL Levels)

100

60

ps

3, 4
3, 5

T

DL

Delay Dispersion
(TTL Levels)

350
100

ps

6, 7
5, 6

t

r

t

f

Rise/Fall Times
20-80%

225 325 475 225 325 475 250 375 500

ps

1. The propagation delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals.
For propagation delay measurements the threshold level (V

THR

) is centered about an 850mV input logic swing with a slew rate of 0.75 V/NS.

There is an insignificant change in the propagation delay over the input common mode range.

2. t

skew

is the propagation delay skew between comparator A and comparator B for a particular part under identical input conditions.

3. Refer to figure 4 and note that the input is at 850mV ECL levels with the input threshold range between the 20% and 80% points. The delay
is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q

output signals.

4. The slew rate is 0.25 V/NS for input rising edges.

5. The slew rate is 0.75 V/NS for input rising edges.

6. Refer to Figure 5 and note that the input is at 2.5 V TTL levels with the input threshold range between the 20% and 80% points. The delay is
measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q

output signals.

7. The slew rate is 0.3 V/NS for input rising edges.

APPLICATIONS INFORMATION

The timing diagram (Figure 3) is presented to illustrate the
MC10E1651’s compare and latch features. When the signal
on the LEN

pin is at a logic high level, the device is operating
in the “compare mode,” and the signal on the input arrives at
the output after a nominal propagation delay (t

PHL

, t

PLH

). The
input signal must be asserted for a time, ts, prior to the
negative going transition on LEN and held for a time, th, after
the LEN transition. After time th, the latch is operating in the
“latch mode,” thus transitions on the input do not appear at
the output. The device continues to operate in the “latch
mode” until the latch is asserted once again. Moreover, the
LEN

pulse must meet the minimum pulse width (tpw)
requirement to effect the correct input-output relationship.
Note that the LEN waveform in Figure 3 shows the LEN
signal swinging around a reference labeled VBB

INT

; this

waveform emphasizes the requirement that LEN

follow

typical ECL 10KH logic levels because VBB

INT

is the

internally generated reference level, hence is nominally at
the ECL VBB level.

Finally, VOD is the input voltage overdrive and represents

the voltage level beyond the threshold level (V

THR

) to which
the input is driven. As an example, if the threshold level is set
on one of the comparator inputs as 80mV and the input signal
swing on the complementary input is from zero to 100mV , the
positive going overdrive would be 20mV and the negative
going overdrive would be 80mV. The result of differing
overdrive levels is that the devices have shorter propagation
delays with greater overdrive because the threshold level is
crossed sooner than the case of lower overdrive levels.
Typically, semiconductor manufactures refer to the threshold
voltage as the input offset voltage (VOS) since the threshold
voltage is the sum of the externally supplied reference
voltage and inherent device offset voltage.

MC10E1651

MOTOROLA ECLinPS and ECLinPS Lite

DL140 — Rev 4

2–4

Figure 3. Input/Output Timing Diagram

Q

Q

V

THR

V

LEN

VBB

INT

V

OD

t

pw

t

h

t

s

t

PHL

t

PLH(LEN

)

V

IN

DELAY DISPERSION

Under a constant set of input conditions comparators have
a specified nominal propagation delay. However, since
propagation delay is a function of input slew rate and input
voltage overdrive the delay dispersion parameters, TDE and
TDT, are provided to allow the user to adjust for these
variables (where TDE and TDT apply to inputs with standard
ECL and TTL levels, respectively).

Figure 4 and Figure 5 define a range of input conditions
which incorporate varying input slew rates and input voltage
overdrive. For input parameters that adhere to these
constraints the propagation delay can be described as:

T

NOM

± TDE (or TDT)

where T

NOM

is the nominal propagation delay. T

NOM

accounts for nonuniformity introduced by temperature and
voltage variability, whereas the delay dispersion parameter
takes into consideration input slew rate and input voltage
overdrive variability. Thus a modified propagation delay can
be approximated to account for the effects of input conditions
that differ from those under which the parts where tested. For
example, an application may specify an ECL input with a slew
rate of 0.25 V/NS, an overdrive of 17mV and a temperature of
25°C, the delay dispersion parameter would be 100 ps. The
modified propagation delay would be

775ps ± 100ps

Figure 4. ECL Dispersion Test Input Conditions

Figure 5. TTL Dispersion Test Input Conditions

0 V

0.5 V

2.0 V

2.5 V

– 1.75 V

– 1.58 V

– 1.07 V

–0.9 V

SLEW RATE = 0.75 V/NS

SLEW RATE = 0.75 V/NS

SLEW RATE =

0.25 V/NS

SLEW RATE =

0.30 V/NS

INPUT

THRESHOLD

RANGE

INPUT

THRESHOLD

RANGE

MC10E1651

2–5 MOTOROLAECLinPS and ECLinPS Lite

DL140 — Rev 4

OUTLINE DIMENSIONS

FN SUFFIX

PLASTIC PLCC PACKAGE

CASE 775–02

ISSUE C

A
B
C
E
F
G
H
J
K
R
U
V

W

X
Y

Z
G1
K1

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

9.78

9.78

4.20

2.29

0.33

0.66

0.51

0.64

8.89

8.89

1.07

1.07

1.07
—
2

°

7.88

1.02

10.03

10.03

4.57

2.79

0.48

0.81
—
—

9.04

9.04

1.21

1.21

1.42

0.50

10

°

8.38
—

0.385

0.385

0.165

0.090

0.013

0.026

0.020

0.025

0.350

0.350

0.042

0.042

0.042
—

2

°

0.310

0.040

0.395

0.395

0.180

0.110

0.019

0.032
—
—

0.356

0.356

0.048

0.048

0.056

0.020

10

°

0.330
—

1.27 BSC0.050 BSC

NOTES:

1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE
TOP OF LEAD SHOULDER EXITS PLASTIC BODY
AT MOLD PARTING LINE.

2. DIM G1, TRUE POSITION TO BE MEASURED AT
DATUM -T-, SEATING PLANE.

3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER
SIDE.

4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.

7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).

-N-

Y BRK

-M-

-L-

W

V

D

D

20

1

A

R

Z

C

G

G1

E

J

VIEW S

B

U

Z

G1

X

H

F

VIEW S

K

K1

VIEW D-D

0.007 (0.180) T L

–M

SNSM

0.007 (0.180) T L

–M

SNSM

SEATING
PLANE

-T-

0.010 (0.250) T L

–M

SNSS

0.007 (0.180) T L

–M

SNSM

0.007 (0.180) T L

–M

SNSM

0.010 (0.250) T L

–M

SNSS

0.007 (0.180) T L

–M

SNSM

0.007 (0.180) T L

–M

SNSM

0.004 (0.100)

MC10E1651

MOTOROLA ECLinPS and ECLinPS Lite

DL140 — Rev 4

2–6

OUTLINE DIMENSIONS

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

19.05

6.10
—

0.39

1.40

0.21

3.18

19.93

7.49

5.08

0.50

1.65

0.38

4.31

0

°

0.51

15

°

1.01

1.27 BSC

2.54 BSC

7.62 BSC

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

0.750

0.240
—

0.015

0.055

0.008

0.125

0.785

0.295

0.200

0.020

0.065

0.015

0.170

0.050 BSC

0.100 BSC

0.300 BSC

A
B
C
D
E

F
G
J
K
L
M
N

0

°

0.020

15

°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

1 8

916

-A-

-B-

C

KN

G

E

F

D 16 PL

-T-

SEATING

PLANE

M

L

J 16 PL

0.25 (0.010) T A

M

S

0.25 (0.010) T B

M

S

MC10E1651

2–7 MOTOROLAECLinPS and ECLinPS Lite

DL140 — Rev 4

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability , including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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Opportunity/Affirmative Action Employer.

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MC10E1651/D

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