Datasheet MC10165L, MC10165P Datasheet (Motorola)



SEMICONDUCTOR TECHNICAL DATA

3–87

REV 6

 Motorola, Inc. 1996

9/96

  

The MC10165 is a device designed to encode eight inputs to a binary
coded output. The output code is that of the highest order input. Any input
of lower priority is ignored. Each output incorporates a latch allowing
synchronous operation. When the clock is low the outputs follow the
inputs and latch when the clock goes high. This device is very useful for
a variety of applications in checking system status in control processors,
peripheral controllers, and testing systems.

The input is active when high, (e.g., the three binary outputs are low
when input D0 is high). The Q3 output is high when any input is high. This
allows direct extension into another priority encoder when more than
eight inputs are necessary. The MC10165 can also be used to develop
binary codes from random logic inputs, for addressing ROMs, RAMs, or
for multiplexing data.

PD= 545 mW typ/pkg (No Load)
tpd= 4.5 ns typ (Data to Output)

tr, tf= 2.0 ns typ (20%–80%)

TRUTH TABLE

DATA INPUTS OUTPUTS

D0 D1 D2 D3 D4 D5 D6 D7 Q3 Q2 Q1 Q0

H X X X X X X X H L L L
L H X X X X X X H L L H
L L H X X X X X H L H L
L L L H X X X X H L H H
L L L L H X X X H H L L
L L L L L H X X H H L H
L L L L L L H X H H H L
L L L L L L L H H H H H
L L L L L L L L L L L L



PIN ASSIGNMENT

V

CC1

Q1
Q0

CLOCK

D0
D7
D1

V

EE

V

CC2

Q2
Q3
D2
D5
D4
D3
D6

16
15
14
13
12
11
10

9

1
2
3
4
5
6
7
8

L SUFFIX

CERAMIC PACKAGE

CASE 620–10

P SUFFIX

PLASTIC PACKAGE

CASE 648–08

MC10165

MOTOROLA MECL Data

DL122 — Rev 6

3–88

C 4

D0 5

D1 7

D2 13

D3 10

D4 11

D5 12

D6 9

D7 6

3 Q0

2 Q1

15 Q2

14 Q3

LOGIC DIAGRAM

V

CC1

= PIN 1

V

CC2

= PIN 16

VEE= PIN 8

MC10165

3–89 MOTOROLAMECL Data

DL122 — Rev 6

ELECTRICAL CHARACTERISTICS

Test Limits

Pin

Under

–30°C +25°C +85°C

Characteristic Symbol

Under

Test

Min Max Min Typ Max Min Max

Unit

Power Supply Drain Current I

E

8 144 105 131 144 mAdc

Input Current I

inH

4
5

390
350

245
220

245
220

µAdc

I

inL

4
5

0.5

0.5

0.5

0.5

0.3

0.3

µAdc

Output Voltage Logic 1 V

OH

2

3
14
15

–1.060
–1.060
–1.060
–1.060

–0.890
–0.890
–0.890
–0.890

–0.960
–0.960
–0.960
–0.960

–0.810
–0.810
–0.810
–0.810

–0.890
–0.890
–0.890
–0.890

–0.700
–0.700
–0.700
–0.700

Vdc

Output Voltage Logic 0 V

OL

2

3
14
15

–1.890
–1.890
–1.890
–1.890

–1.675
–1.675
–1.675
–1.675

–1.850
–1.850
–1.850
–1.850

–1.650
–1.650
–1.650
–1.650

–1.825
–1.825
–1.825
–1.825

–1.615
–1.615
–1.615
–1.615

Vdc

Threshold Voltage Logic 1 V

OHA

2

3
14
15

–1.080
–1.080
–1.080
–1.080

–0.980
–0.980
–0.980
–0.980

–0.910
–0.910
–0.910
–0.910

Vdc

Threshold Voltage Logic 0 V

OLA

2

3
14
15

–1.655
–1.655
–1.655
–1.655

–1.630
–1.630
–1.630
–1.630

–1.595
–1.595
–1.595
–1.595

Vdc

Switching Times (50Ω Load) ns
Propagation Delay Data Input t

5+14+

t

5–14–
t

7+3+

t

11+15+
t

13+2+

14
14

3
15

2

2.0

2.0

2.0

2.0

2.0

7.0

7.0

7.0

7.0

7.0

3.0

3.0

3.0

3.0

3.0

7.0

7.0

7.0

7.0

7.0

2.0

2.0

2.0

2.0

2.0

8.0

8.0

8.0

8.0

8.0

Clock Input t

4–3+

t

4–3–

t

4–14+

t

4–14–

3 (2.)

3 (3.)
14 (2.)
14 (3.)

1.5

1.5

1.5

1.5

4.5

4.5

4.5

4.5

2.0

2.0

2.0

2.0

4.0

4.0

4.0

4.0

1.5

1.5

1.5

1.5

4.5

4.5

4.5

4.5

Setup Time t

setupH

t

setupL

3
3

6.0

6.0

6.0

6.0

3.4

3.0

6.0

6.0

Hold Time t

holdH

t

holdL

3
3

1.0

1.0

1.0

1.0

–2.3
–2.7

1.0

1.0

Rise Time (20 to 80%) t

3+

3 1.1 3.5 1.1 2.0 3.3 1.1 3.5

Fall Time (20 to 80%) t

3–

3 1.1 3.5 1.1 2.0 3.3 1.1 3.5

1. The same limit applies for all D type input pins. To test input currents for other D inputs, individually apply proper voltage to pin under test.

2. Output latched to low state prior to test.

3. Output latched to high state prior to test.
* T o preserve reliable performance, the MC10165P (plastic packaged device only) is to be operated in ambient temperatures above 70°C only when

500 lfpm blown air or equivalent heat sinking is provided.

MC10165

MOTOROLA MECL Data

DL122 — Rev 6

3–90

ELECTRICAL CHARACTERISTICS (continued)

TEST VOLTAGE VALUES (Volts)

@ Test Temperature V

IHmaxVILminVIHAmin

V

ILAmax

V

EE

–30°C –0.890 –1.890 –1.205 –1.500 –5.2
+25°C –0.810 –1.850 –1.105 –1.475 –5.2
+85°C –0.700 –1.825 –1.035 –1.440 –5.2

Pin

TEST VOLTAGE APPLIED TO PINS LISTED BELOW

Characteristic Symbol

Und

er

Test

V

IHmaxVILminVIHAmin

V

ILAmax

V

EE

(VCC)

Gnd

Power Supply Drain Current I

E

8 8 1, 16

Input Current I

inH

4
5

4

5

(1.)

8
8

1, 16
1, 16

I

inL

4
5

4

5

(1.)

8
8

1, 16
1, 16

Output Voltage Logic 1 V

OH

2

3
14
15

6
6
6
6

4
4
4
4

8
8
8
8

1, 16
1, 16
1, 16
1, 16

Output Voltage Logic 0 V

OL

2

3
14
15

4
4
4
4

8
8
8
8

1, 16
1, 16
1, 16
1, 16

Threshold Voltage Logic 1 V

OHA

2

3
14
15

4
4
4
4

6
6
6
6

8
8
8
8

1, 16
1, 16
1, 16
1, 16

Threshold Voltage Logic 0 V

OLA

2

3
14
15

4
4
4
4

6
6
6
6

8
8
8
8

1, 16
1, 16
1, 16

1, 16
Switching Times (50Ω Load) +1.11V +0.31V Pulse In Pulse Out –3.2 V +2.0
Propagation Delay Data Input t

5+14+

t

5–14–
t

7+3+

t

11+15+
t

13+2+

14
14

3

15

2

4
4
4
4
4

5
5

7
11
13

14
14

3

15

2

8
8
8
8
8

1, 16
1, 16
1, 16
1, 16
1, 16

Clock Input t

4–3+

t

4–3–

t

4–14+

t

4–14–

3 (2.)

3 (3.)
14 (2.)
14 (3.)

7

7

4
4
4
4

3

3
14
14

8
8
8
8

1, 16
1, 16
1, 16
1, 16

Setup Time t

setupH

t

setupL

3
3

4,7
4,7

3

3

8
8

1, 16
1, 16

Hold Time t

holdH

t

holdL

3
3

4,7
4,7

3

3

8
8

1, 16
1, 16

Rise Time (20 to 80%) t

3+

3 4 7 3 8 1, 16

Fall Time (20 to 80%) t

3–

3 4 7 3 8 1, 16

1. The same limit applies for all D type input pins. To test input currents for other D inputs, individually apply proper voltage to pin under test.

2. Output latched to low state prior to test.

3. Output latched to high state prior to test.
* T o preserve reliable performance, the MC10165P (plastic packaged device only) is to be operated in ambient temperatures above 70°C only when

500 lfpm blown air or equivalent heat sinking is provided.

Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.

MC10165

3–91 MOTOROLAMECL Data

DL122 — Rev 6

APPLICATION INFORMATION

A typical application of the MC10165 is the decoding of
system status on a priority basis. A 64 line priority encoder
is shown in the figure below. System status lines are

connected to this encoder such that, when a given condition
exists, the respective input will be at a logic high level. This
scheme will select the one of 64 different system
conditions, as represented at the encoder inputs, which
has priority in determining the next system operation to be
performed. The binary code showing the address of the
highest priority input present will appear at the encoder
outputs to control other system logic functions.

Q2

Six bit output
word yielding
number of
highest priority
channel present
at input

ZZZ

MC10164

MC10164 MC10164

X0 X7. . . . . . . A B C

C
D0

D7

Q0

Q1
Q2

LSB

MSB

MC10165MC10165MC10165MC10165MC10165MC10165MC10165MC10165

C
D0

D7

Q0
Q1
Q2
Q3

C
D0

D7

C
D0

D7

C
D0

D7

C
D0

D7

C
D0

D7

C
D0

D7

C
D0

D7

Q0
Q1
Q2
Q3

Q0
Q1
Q2
Q3

Q0
Q1
Q2
Q3

Q0
Q1
Q2
Q3

Q0
Q1
Q2
Q3

Q0
Q1
Q2
Q3

Q0

Q3

1/2 MC10101

System
Clock

Highest
Priority
Input

Lowest
Priority
Input

64–LINE PRIORITY ENCODER

X0 X7. . . . . . . A B C X0 X7. . . . . . . A B C

Q1

MC10165

MOTOROLA MECL Data

DL122 — Rev 6

3–92

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

–A–

–B–

–T–

F

E

G

N

K

C

SEATING
PLANE

16 PLD

S

A

M

0.25 (0.010) T

16 PLJ

S

B

M

0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50

E 0.050 BSC 1.27 BSC

F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31

L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01

____

16 9

18

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MC10165/D

*MC10165/D*

◊