Datasheet MC100LVE210, MC100E210 Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA
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The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part–to–part skew down to an output–to–output skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111’s to accomplish the same task. The MC100LVE210 works from a –3.3V supply while the MC100E210 provides identical function and performance from a standard –4.5V 100E voltage supply.
DUAL 1:4, 1:5 DIFFERENTIAL
Dual Differential Fanout Buffers
200ps Part–to–Part Skew
50ps Typical Output–to–Output Skew
Low Voltage ECL/PECL Compatible
28–lead PLCC Packaging
For applications which require a single–ended input, the VBB reference voltage is supplied. For single–ended input applications the V reference should be connected to the CLK input and bypassed to ground via a 0.01µf capacitor. The input signal is then driven into the CLK input.
To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50, even if only one side is being used. In most applications all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used it is necessary to terminate at least the output pairs adjacent to the output pair being used in order to maintain minimum skew. Failure to follow this guideline will result in small degradations of propagation delay (on the order of 10–20ps) of the outputs being used, while not catastrophic to most designs this will result in an increase in skew. Note that the package corners isolate outputs from one another such that the guideline expressed above holds only for outputs on the same side of the package.
The MC100L VE210, as with most ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVE210 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE210’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage of VCC–2.0V will need to be provided. For more information on using PECL, designers should refer to Motorola Application Note AN1406/D.
BB
LOW VOLTAGE
FANOUT BUFFER
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
7/95
Motorola, Inc. 1996
4–1
REV 1
MC100LVE210 MC100E210
V
EE
V
BB
CLKa
V
CC
CLKa
CLKb CLKb
Qa0 Qa0 Qa1 V
25 24 23 22 21 20 19
26
27
28
1
2
3
4
Pinout: 28–Lead PLCC
(Top View)
567891011
Qb4
Qb3 Qb2Qb4 V
Qa1 Qa2 Qa2
CCO
Qb3 Qb2
CCO
Qa3
18
Qa3
17
Qb0
16
15
V
CCO
14
Qb0
13
Qb1
12
Qb1
LOGIC SYMBOL
PIN NAMES
Pins
CLKa, CLKb Qa0:4, Qb0:3 V
BB
Function
Differential Input Pairs Differential Outputs VBB Output
CLKa CLKa
CLKb CLKb
V
BB
Qa0 Qa0
Qa1 Qa1
Qa2 Qa2
Qa3 Qa3
Qb0 Qb0
Qb1 Qb1
Qb2 Qb2
Qb3 Qb3
Qb4 Qb4
MOTOROLA ECLinPS and ECLinPS Lite
4–2
DL140 — Rev 3
MC100LVE210 MC100E210
MC100L VE210 ECL DC CHARACTERISTICS
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
V
OH
V
OL
V
IH
V
IL
V
BB
V
EE
I
IH
I
EE
MC100L VE210 PECL DC CHARACTERISTICS
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
V
OH
V
OL
V
IH
V
IL
V
BB
V
CC
I
IH
I
EE
1. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
Output HIGH Voltage –1.085 –1.005 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 V Output LOW Voltage –1.830 –1.695 –1.555 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 V Input HIGH Voltage –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 V Input LOW Voltage –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 V Output Reference
Voltage Power Supply Voltage –3.0 –3.8 –3.0 –3.8 –3.0 –3.8 –3.0 –3.8 V Input HIGH Current 150 150 150 150 µA Power Supply Current 55 55 55 65 mA
Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output Reference
1
Voltage Power Supply Voltage 3.0 3.8 3.0 3.8 3.0 3.8 3.0 3.8 V Input HIGH Current 150 150 150 150 µA Power Supply Current 55 55 55 65 mA
–1.38 –1.26 –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 V
–40°C 0°C 25°C 85°C
1
2.215 2.295 2.42 2.275 2.345 2.420 2.275 2.345 2.420 2.275 2.345 2.420 V
1
1.47 1.605 1.745 1.490 1.595 1.680 1.490 1.595 1.680 1.490 1.595 1.680 V
1
2.135 2.420 2.135 2.420 2.135 2.420 2.135 2.420 V
1
1.490 1.825 1.490 1.825 1.490 1.825 1.490 1.825 V
1.92 2.04 1.92 2.04 1.92 2.04 1.92 2.04 V
MC100L VE210 AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = V
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Condition
t
PLH
t
PHL
t
skew
V
PP
V
CMR
tr/t
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
3. The within–device skew is defined as the worst case difference between any two similar delay paths within a single device.
4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay . The VPP(min) is AC limited
5. V
Propagation Delay to Output
IN (differential) IN (single–ended)
Within–Device Skew QaQb
Part–to–Part Skew (Diff) Minimum Input Swing 500 500 500 500 mV Note 4 Common Mode Range –1.5 –0.4 –1.5 –0.4 –1.5 –0.4 –1.5 –0.4 V Note 5 Output Rise/Fall Time 200 600 200 600 200 600 200 600 ps 20%–80%
f
QaQa,QbQb
differential output signals. See
475 400
675 700
505075
200
475 400
503075
75
Definitions and T esting of ECLinPS AC Parameters
ECL Data Book (DL140/D).
Definitions and T esting of ECLinPS AC Parameters
in Chapter 1 (page 1–12) of the Motorola High Performance ECL Data Book (DL140/D).
for the LVE210 as a differential input as low as 50 mV will still produce full ECL levels at the output.
is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
CMR
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
= GND)
CCO
675 700
50
200
500 450
700 750
503075
200
500 450
503075
50
ps 700 750
ps Note 3
50
200
in Chapter 1 (page 1–12) of the Motorola High Performance
Note 1 Note 2
DL140 — Rev 3
4–3 MOTOROLAECLinPS and ECLinPS Lite
MC100LVE210 MC100E210
MC100E210 ECL DC CHARACTERISTICS
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
V
OH
V
OL
V
IH
V
IL
V
BB
V
EE
I
IH
I
EE
MC100E210 PECL DC CHARACTERISTICS
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
V
OH
V
OL
V
IH
V
IL
V
BB
V
CC
I
IH
I
EE
1. These values are for VCC = 5.0V. Level Specifications will vary 1:1 with VCC.
Output HIGH Voltage –1.085 –1.005 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 V Output LOW Voltage –1.830 –1.695 –1.555 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 V Input HIGH Voltage –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 V Input LOW Voltage –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 V Output Reference
Voltage Power Supply Voltage –5.25 –4.2 –5.25 –4.2 –5.25 –4.2 –5.25 –4.2 V Input HIGH Current 150 150 150 150 µA Power Supply Current 55 55 55 65 mA
Output HIGH Voltage13.915 3.995 4.12 3.975 4.045 4.12 3.975 4.045 4.12 3.975 4.045 4.12 V Output LOW Voltage13.170 3.305 3.445 3.19 3.295 3.38 3.19 3.295 3.38 3.19 3.295 3.38 V Input HIGH Voltage Input LOW Voltage Output Reference
1
Voltage Power Supply Voltage 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 V Input HIGH Current 150 150 150 150 µA Power Supply Current 55 55 55 65 mA
–1.38 –1.26 –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 V
–40°C 0°C 25°C 85°C
1
3.835 4.12 3.835 4.12 3.835 4.12 3.835 4.12 V
1
3.190 3.525 3.190 3.525 3.190 3.525 3.190 3.525 V
3.62 3.74 3.62 3.74 3.62 3.74 3.62 3.74 V
MC100E210 AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = V
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Condition
t
PLH
t
PHL
t
skew
V
PP
V
CMR
tr/t
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
3. The within–device skew is defined as the worst case difference between any two similar delay paths within a single device.
4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay . The VPP(min) is AC limited
5. V
Propagation Delay to Output
IN (differential) IN (single–ended)
Within–Device Skew QaQb
Part–to–Part Skew (Diff) Minimum Input Swing 500 500 500 500 mV Note 4 Common Mode Range –1.5 –0.4 –1.5 –0.4 –1.5 –0.4 –1.5 –0.4 V Note 5 Output Rise/Fall Time 200 600 200 600 200 600 200 600 ps 20%–80%
f
QaQa,QbQb
differential output signals. See
475 400
675 700
505075
200
475 400
503075
75
Definitions and T esting of ECLinPS AC Parameters
ECL Data Book (DL140/D).
Definitions and T esting of ECLinPS AC Parameters
in Chapter 1 (page 1–12) of the Motorola High Performance ECL Data Book (DL140/D).
for the E210 as a differential input as low as 50 mV will still produce full ECL levels at the output.
is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
CMR
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
= GND)
CCO
675 700
50
200
500 450
700 750
503075
200
500 450
503075
50
ps 700 750
ps Note 3
50
200
in Chapter 1 (page 1–12) of the Motorola High Performance
Note 1 Note 2
MOTOROLA ECLinPS and ECLinPS Lite
4–4
DL140 — Rev 3
-L-
28 1
-N-
MC100LVE210 MC100E210
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE D
SNSM
0.007 (0.180) T L
Y BRK
B
0.007 (0.180) T L
U
D
Z
-M-
D
W
V
X
VIEW D-D
–M
G1
0.010 (0.250) T L
–M
SNSM
SNSS
–M
Z
C
G
G1
0.010 (0.250) T L
0.007 (0.180) T L
A
0.007 (0.180) T L
R
E
0.004 (0.100)
SEATING
-T-
J
PLANE
VIEW S
SNSS
–M
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
–M
–M
SNSM
SNSM
H
0.007 (0.180) T L
–M
SNSM
K1
K
SNSM
0.007 (0.180) T L
F
–M
VIEW S
INCHES MILLIMETERS
MIN MINMAX MAX
DIM
G1 K1
A B C E F G H J K R U V W X Y Z
0.485
0.485
0.165
0.090
0.013
0.050 BSC
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042 —
°
2
0.410
0.040
0.495
0.495
0.180
0.110
0.019
0.032 — —
0.456
0.456
0.048
0.048
0.056
0.020
10
0.430 —
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
0.64
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
0.50
°
°
2
1.02
10
10.92 —
°
10.42
DL140 — Rev 3
4–5 MOTOROLAECLinPS and ECLinPS Lite
MC100LVE210 MC100E210
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MOTOROLA ECLinPS and ECLinPS Lite
4–6
*MC100LVE210/D*
MC100LVE210/D
DL140 — Rev 3
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