Motorola MC100LVEL39DW, MC100LVEL39DWR2, MC100EL39, MC100EL39DW, MC100EL39DWR2 Datasheet
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SEMICONDUCTOR TECHNICAL DATA
4–1
REV 2
Motorola, Inc. 1996
3/96
÷
÷
The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
MC100EL39 is pin and functionally equivalent to the MC100LVEL39 but
is specified for operation at the standard 100K ECL voltage supply. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended LVECL or, if positive power supplies are
used, LVPECL input signal. In addition, by using the VBB output, a
sinusoidal source can be AC coupled into the device (see Interfacing
section of the ECLinPS Data Book DL140/D). If a single-ended input is
to be used, the VBB output should be connected to the CLK
input and
bypassed to ground via a 0.01µF capacitor. The VBB output is designed to
act as the switching reference for the input of the LVEL39 under
single-ended input conditions, as a result, this pin can only source/sink up
to 0.5mA of current.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
Upon startup, the internal flip-flops will attain a random state; therefore,
for systems which utilize multiple LVEL39s, the master reset (MR) input
must be asserted to ensure synchronization. For systems which only use
one LVEL39, the MR pin need not be exercised as the internal divider
design ensures synchronization between the ÷2/4 and the ÷4/6 outputs of
a single device.
• 50ps Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• 75kΩ Internal Input Pulldown Resistors
• >2000V ESD Protection
• Low Voltage V
EE
Range of –3.0 to –3.8V
CLK
Pinout: 20-Lead SOIC (Top View)
CLK MR V
CC
1718 16 15 14 13 12
43
5 6 7 8 9
Q0
11
10
Q1 Q1 Q2 Q2 Q3 Q3 V
EE
EN
1920
21
VCCQ0
DIVSELb V
BB
V
CC
NC DIVSELa
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
1
20
PIN FUNCTION
CLK Diff Clock Inputs
EN
Sync Enable
MR Master Reset
V
BB
Reference Output
Q0, Q
1
Diff ÷2/4 Outputs
Q2, Q
3
Diff ÷4/6 Outputs
DIVSEL Frequency Select Input
PIN DESCRIPTION
CLK
Z
ZZ
X
EN
L
H
X
MR
L
L
H
FUNCTION
Divide
Hold Q
0–3
Reset Q
0–3
FUNCTION TABLE
Z = Low-to-High Transition
ZZ = High-to-Low Transition
DIVSELa Q0, Q1 OUTPUTS
0 Divide by 2
1 Divide by 4
DIVSELb Q2, Q3 OUTPUTS
0 Divide by 4
1 Divide by 6
MC100LVEL39 MC100EL39
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 3
4–2
CLK
CLK
EN
MR
DIVSELb
÷
2/4
Q0
Q0
Q1
Q1
÷
4/6
Q2
Q2
Q3
Q3
LOGIC DIAGRAM
R
R
DIVSELa
CLK
Q (
÷
2)
Q (
÷
4)
Q (
÷
6)
Figure 1. Timing Diagrams
MC100LVEL39
DC CHARACTERISTICS (VEE = –3.8V to –3.0; VCC = GND)
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 50 59 50 59 50 59 54 61 mA
V
BB
Output Reference Voltage –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 V
I
IH
Input High Current 150 150 150 150 µΑ
MC100LVEL39
AC CHARACTERISTICS (VEE = –3.8V to –3.0; VCC = GND)
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
f
MAX
Maximum Toggle Frequency 1000 1000 1000 1000 MHz
t
PLH
t
PHL
Propagation Delay CLK → Q (Diff)
to Output CLK → Q (S.E.)
MR → Q
760
710
600
960
1010
900
780
730
600
980
1030
900
800
750
610
1000
1050
910
850
800
630
1050
1100
930
ps
t
SKEW
Within-Device Skew
1
Q0 – Q
3
50 50 50 50 ps
Part-to-Part Q0 – Q3 (Diff) 200 200 200 200
t
S
Setup Time EN → CLK
DIVSEL → CLK
250
400
250
400
250
400
250
400
ps
t
H
Hold Time CLK → EN
CLK → Div_Sel
100
150
100
150
100
150
100
150
ps
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