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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 2
Motorola, Inc. 1996
12/93
JK FlipĆFlop
The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters
the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition of
the clock. The reset pin is asynchronous and is activated with a logic
HIGH.
• 525ps Propagation Delay
• 2.2GHz Toggle Frequency
• High Bandwidth Output Transitions
• 75kΩ Internal Input Pulldown Resistors
• >1000V ESD Protection
1
2
3
4 5
6
78Q
V
EE
V
CC
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
K
Q
CLK
R
K
R
J
J
MC10EL35
MC100EL35
J
L
L
H
H
X
TRUTH TABLE
K
L
H
L
H
X
R
L
L
L
L
H
CLK
Z
Z
Z
Z
X
Qn+1
Qn
L
H
Qn
L
Z = LOW to HIGH Transition
1
8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
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MC10EL35 MC100EL35
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 3
3–2
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply 10EL
Current 100EL
272732
32
272732
32
272732
32
27323237mA
V
EE
Power Supply 10EL
Voltage 100EL
–5.2
–4.5
–4.75
–4.20
–5.2
–4.5
–5.5
–5.5
–4.75
–4.20
–5.2
–4.5
–5.5
–5.5
–4.75
–4.20
–5.2
–4.5
–5.5
–5.5
V
I
IH
Input HIGH Current 150 150 150 150 µA
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
f
MAX
Maximum Toggle
Frequency
1.4 2.0 1.8 2.2 1.8 2.2 1.8 2.2 GHz
t
PLH
t
PHL
Propagation Delay CLK
to Output MR
290
225
515
450
740
675
340
275
515
450
690
625
350
275
525
450
700
625
395
350
570
525
745
700
ps
t
S
Setup Time J, K 150 0 150 0 150 0 150 0 ps
t
H
Hold Time J, K 250 100 250 100 250 100 250 100 ps
t
RR
Reset Recovery 400 200 400 200 400 200 400 200 ps
t
PW
Minimum Pulse Width
CLK, Reset
400 400 400 400 ps
t
r
t
f
Output Rise/Fall Times Q
(20% – 80%)
100 225 350 100 225 350 100 225 350 100 225 350 ps