MOTOROLA MC10EL34, MC100EL34 Technical data
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 2
Motorola, Inc. 1996
12/93
÷
÷ ÷
The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended ECL or, if positive power supplies are used,
PECL input signal. In addition, by using the VBB output, a sinusoidal
source can be AC coupled into the device (see Interfacing section of the
ECLinPS Data Book DL140/D). If a single-ended input is to be used, the
VBB output should be connected to the CLK
input and bypassed to ground
via a 0.01µF capacitor. The VBB output is designed to act as the switching
reference for the input of the EL34 under single-ended input conditions,
as a result, this pin can only source/sink up to 0.5mA of current.
The common enable (EN
) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple EL34s in a system.
• 50ps Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• 75kΩ Internal Input Pulldown Resistors
• >1000V ESD Protection
V
CC
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Q0 Q1 V
CC
Q2
1516 14 13 12 11 10
21
3 4 5 6 7
V
CC
9
8
Q2
Q0
EN
NC CLK CLK VBBMR V
EE
D
Q R
Q R
÷
2
Q R
÷
4
Q R
÷
8
Q1
PIN FUNCTION
CLK Diff Clock Inputs
EN
Sync Enable
MR Master Reset
V
BB
Reference Output
Q
0
Diff ÷2 Outputs
Q
1
Diff ÷4 Outputs
Q
2
Diff ÷8 Outputs
PIN DESCRIPTION
CLK
Z
ZZ
X
EN
L
H
X
MR
L
L
H
FUNCTION
Divide
Hold Q
0–3
Reset Q
0–3
FUNCTION TABLE
Z = Low-to-High Transition
ZZ = High-to-Low Transition
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
1
16
MC10EL34 MC100EL34
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 3
3–2
AC/DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
f
MAX
Max Toggle Frequency 1100 1100 1100 1100 MHz
I
EE
Power Supply 10EL
Current 100EL
39
39
39
39
39
39
3942mA
V
BB
Output Reference 10EL
Voltage 100EL
–1.43
–1.38
–1.30
–1.26
–1.38
–1.38
–1.27
–1.26
–1.35
–1.38
–1.25
–1.26
–1.31
–1.38
–1.19
–1.26
V
I
IH
Input High Current 150 150 150 150 µΑ
t
PLH
t
PHL
Propagation CLK→Q0
Delay to CLK→Q1,2
Output MR→Q
960
900
750
1200
1140
1060
960
900
750
1200
1140
1060
960
900
750
1200
1140
1060
970
910
790
1210
1150
1090
ps
t
SKEW
Within-Device Skew 100 100 100 100 ps
t
S
Setup Time EN 400 400 400 400 ps
t
H
Hold Time EN 250 250 250 250 ps
V
PP
Minimum Input Swing
CLK
250 250 250 250
mV
V
CMR
Common Mode Range
CLK
–2.0 –0.4 –2.0 –0.4 –2.0 –0.4 –2.0 –0.4
V
t
r
t
f
Output Rise/Fall Times Q
(20% – 80%)
275 525 275 525 275 525 275 525 ps
Figure 1. Timing Diagram
CLK
Q0
Q1
Q2
EN
The EN signal will freeze the internal clocks to the flip–flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state
during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same
manner, time and relationship as they would have had the EN
signal not been asserted.
Internal Clock
Disabled
Internal Clock
Enabled
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