Motorola MC10EL32D, MC10EL32DR2, MC100EL32D, MC100EL32DR2 Datasheet
MC10EL32
MC100EL32
PIN FUNCTION
CLK Clock Inputs
Reset Asynch Reset
V
BB
Ref Voltage Output
Q Data Ouputs
PIN DESCRIPTION
1
8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 3
Motorola, Inc. 1996
5/95
÷
2 Divider
The MC10EL/100EL32 is an integrated ÷2 divider. The differential
clock inputs and the VBB allow a differential, single-ended or AC coupled
interface to the device. If used, the VBB output should be bypassed to
ground with a 0.01µF capacitor. Also note that the VBB is designed to be
used as an input bias on the EL32 only , the VBB output has limited current
sink and source capability.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flop will attain a random state; the reset
allows for the synchronization of multiple EL32’s in a system.
• 510ps Propagation Delay
• 3.0GHz Toggle Frequency
• High Bandwidth Output Transitions
• 75kΩ Internal Input Pulldown Resistors
• >1000V ESD Protection
1
2
5
6
78Q
V
EE
V
CC
QCLK
V
BB
R
÷2
Reset
CLK
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
3
4
MC10EL32 MC100EL32
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 3
3–2
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply 10EL
Current 100EL
252530
30
252530
30
252530
30
25293035mA
V
EE
Power Supply 10EL
Voltage 100EL
–5.2
–4.5
–4.75
–4.20
–5.2
–4.5
–5.5
–5.5
–4.75
–4.20
–5.2
–4.5
–5.5
–5.5
–4.75
–4.20
–5.2
–4.5
–5.5
–5.5
V
V
BB
Output Reference 10EL
Voltage 100EL
–1.43
–1.38
–1.30
–1.26
–1.38
–1.38
–1.27
–1.26
–1.35
–1.38
–1.25
–1.26
–1.31
–1.38
–1.19
–1.26
V
I
IH
Input HIGH Current 150 150 150 150 µA
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
f
MAX
Maximum Toggle
Frequency
2.2 3.0 2.6 3.0 2.6 3.0 2.6 3.0 GHz
t
PLH
t
PHL
Propagation Delay
CLK to Q
Reset to Q
360
390
500
540
640
690
410
440
500
540
590
640
420
440
510
540
600
640
450
450
540
550
630
650
ps
V
PP
Minimum Input Swing
1
150 150 150 150 mV
t
r
t
f
Output Rise/Fall Times Q
(20% – 80%)
100 225 350 100 225 350 100 225 350 100 225 350 ps
1. Minimum input swing for which AC parameters are guaranteed.
Figure 1. Timing Diagram
CLK
RESET
Q
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