MOTOROLA MC100LVEL14DW, MC100LVEL14DWR2, MC100EL14DW, MC100EL14DWR2 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

1:5 Clock Distribution Chip

The MC100LVEL/100EL14 is a low skew 1:5 clock distribution chip
designed explicitly for low skew clock distribution applications. The
device can be driven by either a differential or single-ended ECL or, if
positive power supplies are used, PECL input signal. The LVEL14 is
functionally and pin compatible with the EL14 but is designed to operate
in ECL or PECL mode for a voltage supply range of –3.0V to –3.8V ( or

3.0V to 3.8V). If a single-ended input is to be used the VBB output should
be connected to the CLK
capacitor. The VBB output is designed to act as the switching reference
for the input of the LVEL14 under single-ended input conditions, as a
result this pin can only source/sink up to 0.5mA of current.

The LVEL14 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high speed
system clock. When LOW (or left open and pulled LOW by the input
pulldown resistor) the SEL pin will select the differential clock input.

The common enable (EN
be enabled/disabled when they are already in the LOW state. This avoids
any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock, therefore
all associated specification limits are referenced to the negative edge of
the clock input.

input and bypassed to ground via a 0.01µF

) is synchronous so that the outputs will only

MC100LVEL14

MC100EL14

20

1

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D-04

• 50ps Output-to-Output Skew

• Synchronous Enable/Disable

• Multiplexed Clock Input

• 75kΩ Internal Input Pulldown Resistors

• >2000V ESD Protection

• V

Range of –3.0V to –5.5V

EE

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

EN
1920

Q0

V

NC SCLK

CC

1718 16 15 14 13 12

D
Q

21

43

Q1 Q2 Q3 Q4

V

CC

Q0

CLK CLK VBBSEL V

1 0

56789

Q2Q1

PIN DESCRIPTION

PIN FUNCTION

CLK Diff Clock Inputs
SCLK Scan Clock Input
EN
SEL Clock Select Input
V

BB

Q

0–4

EE

11

10

Q4Q3

FUNCTION TABLE

CLK

L
H
X
X
X

* On next negative transition of
CLK or SCLK

Sync Enable
Reference Output

Diff Clock Outputs

SCLK

X
X
L
H
X

SEL

L

L
H
H
X

EN

L
L
L
L

H

Q

L

H

L

H

L*

7/95

 Motorola, Inc. 1996

4–1

REV 1

MC100LVEL14 MC100EL14

ABSOLUTE MAXIMUM RATINGS

Symbol

V

EE

V

I

I

out

T

A

V

EE

1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet.

2. Parametric values specified at: 100EL Series: –4.20V to –5.50V

Power Supply (VCC = 0V) –8.0 to 0 VDC
Input Voltage (VCC = 0V) 0 to –6.0 VDC
Output Current Continuous

Operating Temperature Range –40 to +85 °C
Operating Range

1

Characteristic Rating Unit

Surge

1,2

10EL Series: –4.94V to –5.50V

50

100

–5.7 to –4.2 V

mA

DC CHARACTERISTICS (VEE = VEE(min) – VEE(max); VCC = GND1)

–40°C 0°C to 85°C

Symbol Characteristic Min Typ Max Min Typ Max Unit Condition

V

OH

V

OL

V

OHA

V

OLA

V

IH

V

IL

I

IL

1. This table replaces the three tables traditionally seen in ECL 100K data books. The same DC parameter values at VEE = –4.5V now apply across
the full VEE range of –3.0V to –5.5V . Outputs are terminated through a 50Ω resistor to –2.0V except where otherwise specified on the individual
data sheets.

Output HIGH Voltage –1085 –1005 –880 –1025 –955 –880 mV VIN = VIH(max)
Output LOW Voltage –1830 –1695 –1555 –1810 –1705 –1620 mV or VIL(min)
Output HIGH Voltage –1095 — — –1035 — — mV VIN = VIH(max)
Output LOW Voltage — — –1555 — — –1610 mV or VIL(min)
Input HIGH Voltage –1165 — –880 –1165 — –880 mV
Input LOW Voltage –1810 — –1475 –1810 — –1475 mV
Input LOW Current CLK

Others

–300

0.5

— — –300

0.5

— — µA VIN = VIL(max)

MOTOROLA ECLinPS and ECLinPS Lite

4–2

DL140 — Rev 3