Motorola MC100LVEL14, MC100EL14 Datasheet


SEMICONDUCTOR TECHNICAL DATA
   
3.0V to 3.8V). If a single-ended input is to be used the VBB output should be connected to the CLK capacitor. The VBB output is designed to act as the switching reference for the input of the LVEL14 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current.
The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input.
The common enable (EN be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.
input and bypassed to ground via a 0.01µF
) is synchronous so that the outputs will only


20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
50ps Output-to-Output Skew
Synchronous Enable/Disable
Multiplexed Clock Input
75kInternal Input Pulldown Resistors
>2000V ESD Protection
V
Range of –3.0V to –5.5V
EE
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
V
EN
V
CC
Q0
1920
21
Q0
NC SCLK
CC
1718 16 15 14 13 12
D Q
43
Q1 Q2 Q3 Q4
CLK CLK VBBSEL V
1 0
56789
Q2Q1
PIN DESCRIPTION
PIN FUNCTION
CLK Diff Clock Inputs SCLK Scan Clock Input EN SEL Clock Select Input V
BB
Q
0–4
EE
11
10
Q4Q3
FUNCTION TABLE
CLK
L H X X X
* On next negative transition of CLK or SCLK
Sync Enable Reference Output
Diff Clock Outputs
SCLK
X X L H X
SEL
L
L H H X
EN
L L L L
H
Q
L
H
L
H
L*
7/95
Motorola, Inc. 1996
4–1
REV 1
MC100LVEL14 MC100EL14
ABSOLUTE MAXIMUM RATINGS
Symbol
V
EE
V
I
I
out
T
A
V
EE
1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet.
2. Parametric values specified at: 100EL Series: –4.20V to –5.50V
Power Supply (VCC = 0V) –8.0 to 0 VDC Input Voltage (VCC = 0V) 0 to –6.0 VDC Output Current Continuous
Operating Temperature Range –40 to +85 °C Operating Range
1
Characteristic Rating Unit
Surge
1,2
10EL Series: –4.94V to –5.50V
50
100
–5.7 to –4.2 V
mA
DC CHARACTERISTICS (VEE = VEE(min) – VEE(max); VCC = GND1)
–40°C 0°C to 85°C
Symbol Characteristic Min Typ Max Min Typ Max Unit Condition
V
OH
V
OL
V
OHA
V
OLA
V
IH
V
IL
I
IL
1. This table replaces the three tables traditionally seen in ECL 100K data books. The same DC parameter values at VEE = –4.5V now apply across the full VEE range of –3.0V to –5.5V . Outputs are terminated through a 50 resistor to –2.0V except where otherwise specified on the individual data sheets.
Output HIGH Voltage –1085 –1005 –880 –1025 –955 –880 mV VIN = VIH(max) Output LOW Voltage –1830 –1695 –1555 –1810 –1705 –1620 mV or VIL(min) Output HIGH Voltage –1095 –1035 mV VIN = VIH(max) Output LOW Voltage –1555 –1610 mV or VIL(min) Input HIGH Voltage –1165 –880 –1165 –880 mV Input LOW Voltage –1810 –1475 –1810 –1475 mV Input LOW Current CLK
Others
–300
0.5
–300
0.5
µA VIN = VIL(max)
MOTOROLA ECLinPS and ECLinPS Lite
4–2
DL140 — Rev 3
MC100LVEL14 MC100EL14
MC100LVEL14 AC/DC CHARACTERISTICS (VEE = –3.8V to –3.0V; VCC = GND)
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
V
BB
I
IH
t
PLH
t
PHL
t
SKEW
t
S
t
H
V
PP
V
CMR
t
r
t
f
1. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = –3.3V . Note for PECL operation, the V
MC100EL14 AC/DC CHARACTERISTICS (VEE = –4.2V to –5.5V; VCC = GND)
Power Supply Current
Output Ref 100LVEL Voltage 100EL
Input High Current 150 150 150 150 µΑ Prop CLK to Q (Diff)
Delay CLK to Q (SE)
Part-to-Part Skew Within-Device Skew
Setup Time EN 0 0 0 0 ps Hold Time EN 0 0 0 0 ps
Minimum Input Swing CLK
Common Mode Range
Output Rise/Fall Times Q (20% – 80%)
100L VEL
100EL
SCLK to Q
1
2
VPP < 500mV VPP 500mV
–1.43 –1.38
520 470 470
150 150 150 150 mV
–2.0 –1.8
230 500 230 500 230 500 230 500 ps
323240
40
–1.30 –1.26
720 770 770
200
50
–0.4 –0.4
–1.38 –1.38
550 500 500
–2.1 –1.9
323240
40
–1.27 –1.26
750 800 800
200
50
–0.4 –0.4
–1.35 –1.38
580 530 530
–2.1 –1.9
323240
40
–1.25
–1.31
–1.26
–1.38
680
780 830 830
200
50
–0.4 –0.4
630 580 580
–2.1 –1.9
680 680
(min) will be fixed at 3.3V – |V
CMR
343442
–1.19 –1.26
42
830 880 880
20050ps
–0.4 –0.4
(min)|.
CMR
mA
ps
V
V
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
V
BB
I
IH
t
PLH
t
PHL
t
SKEW
t
S
t
H
V
PP
V
CMR
t
r
t
f
1. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = –4.5V . Note for PECL operation, the V
Power Supply Current
Output Ref 100LVEL Voltage 100EL
Input High Current 150 150 150 150 µΑ Prop CLK to Q (Diff)
Delay CLK to Q (SE)
Part-to-Part Skew Within-Device Skew
Setup Time EN 0 0 0 0 ps Hold Time EN 0 0 0 0 ps
Minimum Input Swing CLK
Common Mode Range
Output Rise/Fall Times Q (20% – 80%)
100L VEL
100EL
SCLK to Q
1
2
VPP < 500mV VPP 500mV
–1.43 –1.38
520 470 470
150 150 150 150 mV
–3.2 –3.0
230 500 230 500 230 500 230 500 ps
323240
40
–1.30 –1.26
720 770 770
200
50
–0.4 –0.4
–1.38 –1.38
550 500 500
–3.3 –3.1
323240
40
–1.27 –1.26
750 800 800
200
50
–0.4 –0.4
–1.35 –1.38
580 530 530
–3.3 –3.1
323240
40
–1.25
–1.31
–1.26
–1.38
680
780 830 830
200
50
–0.4 –0.4
630 580 580
–3.3 –3.1
680 680
(min) will be fixed at 5.0V – |V
CMR
343442
–1.19 –1.26
42
830 880 880
20050ps
–0.4 –0.4
(min)|.
CMR
mA
ps
V
V
DL140 — Rev 3
4–3 MOTOROLAECLinPS and ECLinPS Lite
MC100LVEL14 MC100EL14
-A-
1120
-B-
P 10 PL
110
D
20 PL
0.010 (0.25) T A B
M
G 18 PL
S S
C
K
-T-
SEATING PLANE
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
ISSUE E
J
F
M M
B
M
0.010 (0.25)
R X 45°
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
MIN MINMAX MAX
DIM
12.65
A
7.40
B
2.35
C
0.35
D
0.50
F
1.27 BSC 0.050 BSC
G J
0.25
K
0.10
M
0
°
P
10.05
R
0.25
12.95
7.60
2.65
0.49
0.90
0.32
0.25 7
10.55
0.75
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.010
0.012
0.004
0.009
0
7
°
°
°
0.395
0.010
0.415
0.029
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4–4
*MC100LVEL14/D*
MC100LVEL14/D
DL140 — Rev 3
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