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SEMICONDUCTOR TECHNICAL DATA
The MC10/100E445 is an integrated 4-bit serial to parallel data
converter. The device is designed to operate for NRZ data rates of up to
2.0Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both
4-bit conversion and a two chip 8-bit conversion function. The conversion
sequence was chosen to convert the first serial bit to Q0, the second to
Q1 etc.
• On-Chip Clock ÷4 and ÷8
• 2.0Gb/s Data Rate Capability
• Differential Clock and Serial Inputs
• V
Output for Single-Ended Input Applications
BB
PARALLEL CONVERTER
4-BIT SERIAL/
• Asynchronous Data Synchronization
• Mode Select to Expand to 8-Bits
• Internal 75kΩ Input Pulldown Resistors
• Extended 100E V
Two selectable serial inputs provide a loopback capability for testing
purposes when the device is used in conjunction with the E446 parallel to
serial converter.
The start bit for conversion can be moved using the SYNC input. A
single pulse applied asynchronously for at least two input clock cycles
shifts the start bit for conversion from Qn to Qn–1. For each additional
shift required an additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock dividers to “swallow”
a clock pulse, effectively shifting a bit from the Qn to the Qn–1 output (see
Timing Diagram B).
The MODE input is used to select the conversion mode of the device. With the MODE input LOW, or open, the device will
function as a 4-bit converter. When the mode input is driven HIGH the data on the output will change on every eighth clock cycle
thus allowing for an 8-bit conversion scheme using two E445’s. When cascaded in an 8-bit conversion scheme the devices will
not operate at the 2.0Gb/s data rate of a single device. Refer to the applications section of this data sheet for more information on
cascading the E445.
For lower data rate applications a VBB reference voltage is supplied for single-ended inputs. When operating at clock rates
above 500MHz differential input signals are recommended. For single-ended inputs the VBB pin is tied to the inverting differential
input and bypassed via a 0.01µF capacitor. The VBB provides the switching reference for the input differential amplifier . The V
can also be used to AC couple an input signal, for more information on AC coupling refer to the interfacing section of the design
guide in the ECLinPS data book.
Upon power-up the internal flip-flops will attain a random state. To synchronize multiple E445’s in a system the master reset
must be asserted.
Range of –4.2V to –5.46V
EE
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
BB
PIN NAMES
Pin Function
SINA, SINA
SINB, SINB
SEL
Q0–Q3
CLK, CLK
CL/4, CL/4
CL/8, CL/8
MODE
SYNCH
Differential Serial Data Input A
Differential Serial Data Input B
Serial Input Selector Pin
Parallel Data Outputs
Differential Clock Inputs
Differential ÷4 Clock Output
Differential ÷8 Clock Output
Conversion Mode 4-Bit/8-Bit
Conversion Synchronizing Input
FUNCTION TABLES
Mode Conversion SEL Serial Input
L
H
8/97
Motorola, Inc. 1997
4-Bit
8-Bit
H
L
1
V
CL/4
NCMODESINASINA
CCO
CCO
19202122232425
18
17
16
15
14
13
12
111098765
Q3V
SOUT
SOUT
V
CC
Q0
Q1
V
CCO
Q2
SYNC
RESET
SINB
26
SINB
27
SEL
28
V
EE
CLK
CLK
V
BB
A
B
Figure 1. 28–Lead Pinout
1
2
3
4
REV 3
CL/8CL/8
(Top View)
CL/4V
CCO
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MC10E445 MC100E445
SINB
SINB
SINA
SINA
SEL
QD
QD Q2QD
QD Q1QD
QD Q0QD
QD
Q3
MODE
CLK
CLK
SYNC
RESET
OutIn
Latch
EN
QD
D
Q
Figure 2. Logic Diagram
SOUT
SOUT
0
1
Out
÷
4
R
Out
÷
2
R
CL/4
CL/4
CL/8
CL/8
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DL140 — Rev 4
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MC10E445 MC100E445
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit Condition
I
IH
V
OH
V
BB
I
EE
1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard
10E and 100E VOH levels.
Input HIGH Current 150 150 150 µA
Ouput HIGH Current
10E (SOUT Only)
100E (SOUT Only)
Output Reference Voltage
10E
100E
Power Supply Current
10E
100E
–1020
–1025
–1.38
–1.38
154
154
–790
–830
–1.27
–1.26
185
185
–980
–1025
–1.35
–1.38
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit Condition
f
MAX
t
PLH
t
PHL
t
s
t
h
t
RR
t
PW
t
r
t
f
Maximum Conversion Frequency 2.0 2.0 2.0 Gb/s
Propagation Delay to Output
CLK to Q
CLK to SOUT
CLK to CL/4
CLK to CL/8
Setup Time
SINA, SINB
SEL
Hold Time
SINA, SINB, SEL
Reset Recovery Time 500 300 500 300 500 300 ps
Minimum Pulse Width
CLK, MR
Rise/Fall Times
SOUT
Other
1500
1800
975
1325
1325
–200
225
425
2100
1150
1550
1550
350
650
800
1100
1100
–1000–250
450 300 450 300 450 300
400 400 400
100
200
= GND)
CCO
154
154
= GND)
CCO
1500
1800
800
100
200
975
1325
1325
–200
225
425
1100
1100
–1000–250
–760
–830
–1.25
–1.26
185
185
2100
1150
1550
1550
350
650
–910
–1025
–1.31
–1.38
1500
800
1100
1100
–1000–250
100
200
154
177
1800
975
1325
1325
–200
225
425
–670
–830
–1.19
–1.26
185
212
2100
1150
1550
1550
350
650
V
1
1
V
mA
NRZ
ps
ps
ps
ps
ps 20%–80%
DL140 — Rev 4
3 MOTOROLAECLinPS and ECLinPS Lite