SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/MC100E336 contains three bus transceivers with both
transmit and receive registers. The bus outputs (BUS0
–BUS2) are
specified for driving a 25Ω bus; the receive outputs (Q0 – Q2) are
specified for 50Ω. The bus outputs feature a normal HIGH level (VOH) and
a cutoff LOW level — when LOW, the outputs go to –2.0V and the output
emitter-follower is “off”, presenting a high impedance to the bus. The bus
outputs also feature edge slow-down capacitors.
• 25Ω Cutoff Bus Outputs
• 50Ω Receiver Outputs
• Transmit and Receive Registers
• 1500ps Max. Clock to Bus
• 1000ps Max. Clock to Q
• Bus Outputs Feature Internal Edge Slow-Down Capacitors
• Additional Package Ground Pins
• Extended 100E V
EE
Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
The Transmit Enable pins (TEN) control whether current data is held in
the transmit register, or new data is loaded from the A/B inputs. A LOW on
both of the Bus Enable inputs (BUSEN), when clocked through the
register, disables the bus outputs to –2.0V.
The receiver section clocks bus data into the receive registers, after
gating with the Receive Enable (RXEN
) input.
All registers are clocked by a positive transition of CLK1 or CLK2 (or
both).
Additional leadframe grounding is provided through the Ground pins (GND) which should be connected to 0V. The GND pins
are not electrically connected to the chip.
LOGIC DIAGRAM
BUSEN1
BUSEN2
RXEN
V
EE
CLK1
CLK2
A
0
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
115 6 7 8 9 10
TEN2 TEN1 B2A2NC V
CCOQ2
GND
BUS2
V
CC
Q
1
V
CCO
BUS1
GND
B0A1B1V
CCO
BUS0
GND Q
0
A
0
B
0
A
1
B
1
A
2
B
2
TEN1
TEN2
RXEN
BUSEN1
BUSEN2
CLK1
CLK2
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
0
0
0
1
1
1
BUS0
BUS1
BUS2
50
Ω
50
Ω
50
Ω
25 Ω CUTOFF
25
Ω
CUTOFF
25
Ω
CUTOFF
Q
0
Q
1
Q
2
1
Pinout: 28-Lead PLCC (Top View)
* All VCC and V
CCO
pins are tied together on the die.
3-BIT REGISTERED
BUS TRANSCEIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02