Motorola MC10E256FN, MC100E256FN Datasheet
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/100E256 contains three 4:1 multiplexers followed by
transparent latches with differential outputs. Separate Select controls are
provided for the leading 2:1 mux pairs (see logic symbol).
When the Latch Enable (LEN) is LOW, the latch is transparent, and
output data is controlled by the multiplexer select controls. A logic HIGH
on LEN latches the outputs. The Master Reset (MR) overrides all other
controls to set the Q outputs LOW.
• 950ps Max. D to Output
• 850ps Max. LEN to Output
• Split Select
• Differential Outputs
• Extended 100E V
EE
Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
SEL1A
SEL1B
SEL2
V
EE
LEN
MR
D
1c
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
115 6 7 8 9 10
D1bD1aD2dD2cD2bD2aV
CCO
Q
2
Q
2
V
CC
Q
1
Q
1
V
CCO
Q
0
D1dD0aD0bD0cD0dV
CCOQ0
1
Pinout: 28-Lead PLCC (Top View)
* All VCC and V
CCO
pins are tied together on the die.
FUNCTION TABLE
Pin State Operation
SEL2 H Output c/d Data
SEL1A H Input d Data
SEL1B H Input b Data
PIN NAMES
Pin Function
D0x– D
2x
Data Inputs
SEL1A, SEL1B First-stage Select Inputs
SEL2 Second-stage Select input
LEN Latch Enable
MR Master Reset
Q0, Q0– Q2, Q
2
Data Outputs
3-BIT 4:1
MUX-LATCH
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
MC10E256 MC100E256
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–2
LOGIC DIAGRAM
D
0a
D
0b
D
0c
D
0d
D
1a
D
1b
D
1c
D
1d
D
2a
D
2b
D
2c
D
2d
SEL1A
SEL1B
SEL2
LEN
MR
Q0
Q0
Q1
Q1
Q2
Q2
D
EN
R
D
EN
R
D
EN
R
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
I
IH
Input HIGH Current 150 150 150 µA
I
EE
Power Supply Current mA
10E 69 83 69 83 69 83
100E 69 83 69 83 79 96
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