MOTOROLA MC10E241FNR2, MC100E241FNR2, MC100E241FN Datasheet
LOGIC DIAGRAM
SEL1
CLK
MR
V
EE
S-IN
D
0
D
1
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
115 6 7 8 9 10
SEL0 NC D7D6D5V
CCOQ7
Q
6
Q
5
V
CC
NC
V
CCO
Q
4
Q
3
D2D3D4V
CCOQ0Q1Q2
Q
0
Q1 – Q
6
Q
7
S-IN
D
0
D1 – D
6
D
7
HOLD/LOAD
SHIFT
CLK
MR
BITS 1–6
D
D
D
Q
Q
Q
R
R
R
1
Pinout: 28-Lead PLCC (Top View)
* All VCC and V
CCO
pins are tied together on the die.
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 3
Motorola, Inc. 1996
7/96
The MC10E/100E241 is an 8-bit shiftable register. Unlike a standard
universal shift register such as the E141, the E241 features internal data
feedback organized so that the SHIFT control overrides the HOLD/LOAD
control. This enables the normal operations of HOLD and LOAD to be
toggled with a single control line without the need for external gating. It
also enables switching to scan mode with the single SHIFT control line.
The eight inputs D0– D7 accept parallel input data, while S-IN accepts
serial input data when in shift mode. Data is accepted a set-up time
before the positive-going edge of CLK; shifting is also accomplished on
the positive clock edge. A HIGH on the Master Reset pin (MR)
asynchronously resets all the registers to zero.
• SHIFT overrides HOLD/LOAD Control
• 1000ps Max. CLK to Q
• Asynchronous Master Reset
• Pin-Compatible with E141
• Extended 100E V
EE
Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
PIN NAMES
Pin Function
D0– D
7
Parallel Date Inputs
S-IN Serial Data Inputs
SEL0 SHIFT Control
SEL1 HOLD/LOAD Control
CLK Clock
MR Master Reset
Q0– Q
7
Data Outputs
8-BIT SCANNABLE
REGISTER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
MC10E241 MC100E241
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–2
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
I
IH
Input HIGH Current 150 150 150 µA
I
EE
Power Supply Current MA
10E 125 150 125 150 125 150
100E 125 150 125 150 144 173
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
f
SHIFT
Max. Shift Frequency 700 900 700 900 700 900 MHz
t
PLH
Propagation Delay to Output ps
t
PHL
Clk 625 750 975 625 750 975 625 750 975
MR 600 725 975 600 725 975 600 725 975
t
s
Setup Time ps
D 175 25 175 25 175 25
SEL0 (SHIFT) 350 200 350 200 350 200
SEL1 (HOLD/LOAD) 400 250 400 250 400 250
S-IN 125 –100 125 –100 125 –100
t
h
Hold Time ps
D 200 – 25 200 – 25 200 – 25
SEL0 (SHIFT) 100 – 200 100 – 200 100 – 200
SEL1 (HOLD/LOAD) 50 – 250 50 – 250 50 – 250
S-IN 300 100 300 100 300 100
t
RR
Reset Recovery Time 900 600 900 600 900 600 ps
t
PW
Minimum Pulse Width ps
Clk, MR 400 400 400
t
SKEW
Within-Device Skew 60 60 60 ps 1
t
r
Rise/Fall Times ps
t
f
20 - 80% 300 525 800 300 525 800 300 525 800
1. Within-device skew is defined as identical transitions on similar paths through a device.
FUNCTION TABLE
MR SEL0 SEL1 Function
1 X X Outputs LOW
0 1 X Shift Data
0 0 1 Hold Data
0 0 0 Load Data
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