MOTOROLA MC10E167, MC100E167 Technical data
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/100E167 contains six 2:1 multiplexers followed by D
flip-flops with single-ended outputs. Input data are selected by the Select
control, SEL. The selected data are transferred to the flip-flop outputs by
a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset
(MR) pin asynchronously forces all Q outputs LOW.
• 1000MHz Min. Operating Frequency
• 800ps Max. Clock to Output
• Single-Ended Outputs
• Asynchronous Master Resets
• Dual Clocks
• Extended 100E V
EE
Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
Q
0
V
CCO
NCD3aD3bD4aD4bD5a
D5b
CLK1
CLK2
V
EE
MR
SEL
D0a
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
115 6 7 8 9 10
Q
5
Q
4
V
CC
Q
3
Q
2
V
CCO
Q
1
D0b D1a D1b D2a D2b V
CCO
1
Pinout: 28-Lead PLCC (Top View)
* All VCC and V
CCO
pins are tied together on the die.
PIN NAMES
Pin Function
D0a – D5a Input Data a
D0b – D5b Input Data b
SEL Select Input
CLK1, CLK2 Clock Inputs
MR Master Reset
Q0– Q
5
Data Outputs
FUNCTIONS
SEL Data
H
L
a
b
6-BIT 2:1
MUX-REGISTER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
D0a
D0b
D1a
D1b
D2a
D2b
D3a
D3b
D4a
D4b
SEL
CLK1
CLK2
MR
Q
0
Q
1
Q
2
Q
3
Q
4
D
Q
R
D
Q
R
D
Q
R
D
Q
R
D
Q
R
D5a
D5b
Q
5
D
Q
R
SEL
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
MUX
MC10E167 MC100E167
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–2
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
I
IH
Input HIGH Current 150 150 150 µA
I
EE
Power Supply Current mA
10E 94 113 94 113 94 113
100E 94 113 94 113 108 130
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
f
MAX
Max. Toggle Frequency 1000 1400 1000 1400 1000 1400 MHz
t
PLH
Propagation Delay to Output ps
t
PHL
Clk 450 650 800 450 650 800 450 650 800
MR 450 650 850 450 650 850 450 650 850
t
s
Setup Time ps
D 100 – 50 100 – 50 100 – 50
SEL 275 125 275 125 275 125
t
h
Hold Time ps
D 300 50 300 50 300 50
SEL 75 –125 75 –125 75 –125
t
RR
Reset Recovery Time 750 550 750 550 750 550 ps
t
PW
Minimum Pulse Width ps
Clk, MR 400 400 400
t
SKEW
Within-Device Skew 75 75 75 ps 1
t
r
Rise/Fall Times ps
t
f
20 - 80% 300 450 800 300 450 800 300 450 800
1. Within-device skew is defined as identical transitions on similar paths through a device.
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