MOTOROLA MC10E160FNR2, MC100E160FNR2, MC10E160FN, MC100E160FN Datasheet
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/100E160 is a 12-bit parity generator/checker. The Q
output is HIGH when an odd number of inputs are HIGH. A HIGH on the
Enable input (EN) forces the Q output LOW.
The E160 also features an output register. Multiplexers direct the
register input, giving the option of holding present data by asserting
HOLD
LOW, or of shifting data in through the S-IN pin by asserting SHIFT
HIGH. The output register itself is clocked by a positive edge on CLK1 or
CLK2 (or both). A HIGH on the reset pin (R) overrides to force the Y
output LOW.
• Provides Odd-HIGH Parity of 12 Inputs
• Shiftable Output Register with Hold
• 900ps Max. D to Q/Q Output
• Enable
• Asynchronous Register Reset
• Dual Clocks
• Extended 100E V
EE
Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
PIN NAMES
Pin Function
D0– D
11
Data Inputs
S-IN Serial Data Input
EN Enable, active LOW
HOLD Hold, active LOW
SHIFT Shift, active HIGH
CLK1, CLK2 Clock Inputs
R Reset Inputs
Q, Q Direct Output
Y, Y Register Output
12-BIT PARITY
GENERATOR/CHECKER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
D
1
D11HOLD
S-IN SHIFT CLK1 CLK2
EN
V
CCO
D
0
D
2
D
3
D
4
LOGIC DIAGRAM
D
5
D
6
D
7
V
EE
D
8
D
9
D
10
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
115 6 7 8 9 10
Q
Q
V
CC
Y
Y
V
CCO
NC
R
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
EN
HOLD
S-IN
SHIFT
CLK1
CLK2
R
D
11
D
R
Y
Y
Q
0
1
1
MUX
Pinout: 28-Lead PLCC (Top View)
* All VCC and V
CCO
pins are tied together on the die.
SEL
0
1
MUX
SEL
MC10E160 MC100E160
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–2
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
I
IH
Input HIGH Current µA
CLK1, CLK2 200 200 200
R 300 300 300
All Other Inputs 150 150 150
I
EE
Power Supply Current mA
10E 82 98 82 98 82 98
100E 82 98 82 98 94 113
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
t
PLH
Propagation Delay to Output ps
t
PHL
D to Q 400 650 950 400 650 950 400 650 950
En to Q 300 550 750 300 550 750 300 550 750
CLK to Y 275 500 700 275 500 700 275 500 700
R to Y 275 500 725 275 500 725 275 500 725
t
s
Setup Time ps
D 1200 900 1200 900 1200 900
HOLD 600 300 600 300 600 300
S-IN 350 150 350 150 350 150
SHIFT 500 250 500 250 500 250
t
h
Hold Time ps
D – 400 – 900 – 400 – 900 – 400 – 900
HOLD 100 –300 100 – 300 100 – 300
S-IN 300 –150 300 –150 300 –150
SHIFT 200 –250 200 – 250 200 – 250
t
r
Rise/Fall Time ps
t
f
20 - 80% 300 450 650 300 450 650 300 450 650
1. Within a device skew is guaranteed for identical transitions on similar paths through a device.
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