MOTOROLA MC10E156, MC100E156 Technical data
D1d D0b D0c D0d V
CCOQ0
V
CCO
D2aD2bD2cD2dD1aD1b
LOGIC DIAGRAM
SEL0
SEL1
MR
V
EE
LEN1
LEN2
D
1c
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
115 6 7 8 9 10
Q
2
Q
2
V
CC
Q
1
Q
1
V
CCO
Q
0
D0a
D0a
D0b
D0c
D0d
D1a
D1b
D1c
D1d
D2a
D2b
D2c
D2d
SEL0
SEL1
LEN1
LEN2
MR
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
4:1
MUX
4:1
MUX
4:1
MUX
D
EN
R
D
EN
R
D
EN
R
1
Pinout: 28-Lead PLCC (Top View)
* All VCC and V
CCO
pins are tied together on the die.
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 3
Motorola, Inc. 1996
7/96
The MC10E/100E156 contains three 4:1 multiplexers followed by
transparent latches with differential outputs. When both Latch Enables
(LEN1, LEN2) are LOW, the latch is transparent, and output date is
controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH
on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset
(MR) overrides all other controls to set the Q outputs LOW.
• 950ps Max. D to Output
• 850ps Max. LEN to Output
• Differential Outputs
• Asynchronous Master Reset
• Dual Latch-Enables
• Extended 100E V
EE
Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
PIN NAMES
Pin Function
D0x – D3x Input Data
SEL0, SEL1 Select Inputs
LEN1, LEN2 Latch Enables
MR Master Reset
Q0– Q
2
True Outputs
Q
0
– Q
2
Inverted Outputs
FUNCTION TABLE
SEL1 SEL0 Data
L
L
H
H
L
H
L
H
a
b
c
d
3-BIT 4:1
MUX-LATCH
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
MC10E156 MC100E156
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–2
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
I
IH
Input HIGH Current 150 150 150 µA
I
EE
Power Supply Current mA
10E 75 90 75 90 75 90
100E 75 90 75 90 86 103
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
t
PLH
Propagation Delay to Output ps
t
PHL
D 400 600 900 400 600 900 400 600 900
SEL0 550 775 1050 550 775 1050 550 775 1050
SEL1 450 650 900 450 650 900 450 650 900
LEN 350 500 800 350 500 800 350 500 800
MR 350 600 825 350 600 825 350 600 825
t
s
Setup Time ps
D 400 275 400 275 400 275
SEL0 700 300 700 300 700 300
SEL1 600 400 600 400 600 400
t
h
Hold Time ps
D 300 – 275 300 – 275 300 – 275
SEL0 100 – 300 100 – 300 100 – 300
SEL1 200 – 400 200 – 400 200 – 400
t
RR
Reset Recovery Time 800 600 800 600 800 600 ps
t
PW
Minimum Pulse Width ps
MR 400 400 400
t
SKEW
Within-Device Skew 50 50 50 ps 1
t
r
Rise/Fall Times ps
t
f
20 - 80% 275 475 700 275 475 700 275 475 700
1. Within-device skew is defined as identical transitions on similar paths through a device.
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