RX MID CHANNELS
850: CH190 -- 881,6
GSM: CH 62 -- 947,4 MHz
EGSM: CH 37 -- 942,4Mhz
DCS: CH 700 -- 1842,8MHz
PCS: CH 661 -- 1960MHz
TX_OUT_HB
TX_OUT_LB
1900 MHZ
1800 MHz
900 MHz
850 MHz
B+
DCS/PCS OUT
9
1
2
5
2
1
2
U50
PA + Antenna Switch
GSM850/
GSM900 OUT
from Neptune
( Frontend Control
and Digital Modulation)
MCLK
J1050
Coax Cable to Keyboard PCB
3
3
16
15
14
(NC)
TXIMSMDI
Power and
Antenna
Control
8
13
(PA Power Control)
RAMP
21
1
RF_SENSE
6
4
7
3
NEPTUNE LTS
(to U200)
( to Atlas )
TX_START
(Transmitt Enable)
(Band select)
TX_EN
CNTRL_2
CNTRL_3
CNTRL_1
(Transmitt Enable)
(Receive Enable)
TX_START
RX_ANT_EN
( Frontend Control
and Digital Modulation)
(Clock )
(Reset )
(Data In /OUT)
MCLK
MS
MDI
RF_SENSE
T9
W10
U9
U6
V8
B10
SPI
L1 Timer
PA Control
U800
DSP Peripherals
accelerator, encryption
Timer, Interupts
DSP
UltraLite
104 MHz
Shared Memory
1Mbit RAM
DSP
Memory
Power
SIM
Interface
H1
A11
E2
V5
VSIM
K2
SIM DIO
K3
SIM RST
J4
SIM CLK
L1
SIM_PD
R1
M1
DATA BUS
ADDRESS BUS
IO_REG
PERIPH_REG
REF_REG
VBUCK
(from Atlas)
(Data In /OUT)
(Reset )
(Clock )
(from Atlas)
VSIM_EN
(VCC + 2.775V)
(VCC + 1,575V)
(VCC + 1,875V)
(to Atlas)
D0-15
(VCC + 2.775V)
(from / to J508)
A1-24
D2
C3
D6 G5
G8
D7E8E7
A2
SAW/ LNA
LNA
Matching
A3
SAW/ LNA
LNA
Matching
A5
SAW/ LNA
LNA
Matching
A6
SAW/ LNA
LNA
Matching
U1051
G1
2
F1
1
Quadrature
Mixer
Quadrature
Generator
Polyphase
Filter
DC
Correct
( VCO Feedback )
( VCO Tuning)
VCO1 (TX_LB)
VCO2 (TX_HB)
TX_EN
IIN
RX/TX
IBIN
Switch
(100KHz)
QBIN
RX/TX
QIN
Switch
U250
GSM/ EDGE
TRANCEIVER
FIN
ADC
13 bit
ADC
13 bit
Loop Filter
Sync
Filter
Sync
Filter
Digital TX
Interface
GMSK
Modulator
Phase Det.
(100KHz)
Devider
CP
Anti
Drop
Anti
Drop
EDGE
Modulator
Anti
Alias
Anti
Alias
EDGE
FIR
Filter
GMSK/ EDGE Select
Pre-Distortion
Filter
DAC1
Chanel
Filter
Chanel
Filter
Anti
Alias
PA Control
B7
GPIO
DAC
12 bit
DAC
12 bit
Reference
Devider
Serial
Interface
C2
E6
LPF
LPF
Oscilator and
ADC
Voltage
Reg.
F8
ENR
F7
CLKR
F6
Clock Generator
Interface
H7
D8
G7
E5
C5
C6
F4
F5
G4
G3
H3
G7..
C1..
FSR
DRI
OSCO
PERIPH_IO_REG
OSCM
1
Y1201
3
26MHz
RF_DATA
RF_CLK
RF_CS
LDTO
( Lock Detect Out)
VCO_REG
PERIPH_IO_REG
RF_REG
(VCC’s from Atlas)
(Clock enable)
2
(NC)
(Clock )
(U250 Control Bus)
Output Mixer
Serial
(Data In /OUT)
(Chip select)
W7
G12
Voi c e B a n d
A13
N10
26 MHz
A4
Oscillator
U8
V7
SPI
W9
UART / USB
Interface
A17
C15
C16
B16
D15
A16
Keypad
Interface
A15
G3....
F3....
W13
MCU
ARM7
52 MHz
MCU
Memory
External
Memory
Interface
Clock Generator
MQSPI
Display
GPIO
On
Off
T11
V12
MQSPI
V11
W12
B14
D18
T10
T12
B
aseBand
Timer
Interface
V13
U13
G8
One
Serial Audio
Wire
Port Interface
Bus
W11
D13
(rx)
A12
U11
E3
W5
B12
UART2
Universal
Asynchron.
(tx)
B13
N13
N17
Rx /Tx
V16
D16
B17
BT
B15
D19
W18
V17
G17
K16
J19
T16
T19
L16
N18
P2
N3
M4
P1
L3...
U10
V6
U12
C18
E1
T15
CE0B
CE_2
(NC)
CS2B
EB1B
EB0B
R WB
OEB
BURSTCLK
LBAB
ECBB
LCD_RS
LCD_CS
LCD_CLK_DATA6
LCD_SDATA_DATA7
LCD DATA (0 - 5)
TOUT12
STANDBY_GATEB
ANT_DETB
RTCK
LT_SNS_CTL
ADC DATA
Light Sensor
K1
G8
D6
F3
FLASH
C2
F5,D5
J2,H1,H8
C6
E5
G7
32 MB Flash
(Bias output for THERM signal)
(from J508)
(to J508 Tri data write)
6
1
Q801
2
U700
F4
E4...
8MB SRam
(to U1301 ATI
(to Clock enable Circuit)
RESET OUT
(from
VBUCK
Atlas
)
OSCM
(clock)
U804
4
2
1
USB_VPIN
USB_XRXD_RTS
USB_VPOUT_TXD
Neptune Atlas
USB/ RS232
Communication
(from/ to J508
and Sidekey’s)
USB_VMIN_RXD
USB_TXENB
USB_VMOUT
CLK 13 MHz
BB_SPI_MISO
BB_SPI_MOSI
AUL_INT
GA_SPI_CS
AUL_CS
GA_INT
TRI_SPI_CS
U806
Level
Shift
4
STANDBY_1_5V
2
BB_SPI_CLK
KBC0-1
KBR0-7
SJC_MOD
Neptune Atlas
(13 MHz)
Neptune ATI
Communication
(framesync)
OWB
One Wire data from Battery
BB_SAP_FS
BB_SAP_CLK
(from/ to Neptune
Serial Audio for Ringtone
and V oice Audio)
BLUE_RX
BB_SAP_RX
BB_SAP_TX
Communication and Wakeup)
BLUE_TX
BLUE_CTSB
BLUE_RTSB
BLUE_CLK_ENB
(from/ to U301 BT, J1300
Neptune - BT - Neptune
BLUE_WAKEB
BLUE_HOST_WAKEB
Revision Overview
Rev. 1.0: Initial Block Diagram
L7
Main PCB
(from Neptune GPIO)
STANDBY_GATEB
SIDE KEYS
Up, Down
VA, PT T
(Watchdog)
GPIO_RESET
RESETB
RESET OUT
CLK 32KHZ
WDOG
STANDBY
Servive, Engineering & Optimization 2005.08.26
LEVEL 3 AL Block Diagram Rev. 1.0
and BT))
(to ATI)
(to U700)
(from Atlas)
(to Atlas)
(from /to Atlas
(to Atlas)
L7
Alexander Buehler, Michael Mauderer Page 1of 3
Main PCB
L7
V30x, V400, V50x, V600
30
25
10
21
16
15
32
(on PCB)
Strip Line
Antenna
BT_ANTENNA
1
Y300
3
PERIPH_REG
BT_REG
Bluetooth
(from/ to U301 BT,
Neptune - BT - Neptune
Communication and Wakeup)
Serial Audio for Ringtone
BLUE_WAKEB
BLUE_HOST_WAKEB
BLUE_CLK_ENB
(from Neptune/ Atlas)
(from Atlas)
(from/ to Neptune
and Voic e Audio)
BLUE_TX
BLUE_RX
BLUE_CTSB
BLUE_RTSB
RESET_B
CLK_32KHZ
BB_SAP_RX
BB_SAP_FS
BB_SAP_CLK
BB_SAP_TX
Bluetooth
5
33
29
31
11
9
13
22
12
(framesync)
(clock)
27
U301
28
(from Atlas)
Neptune Atlas
USB/ RS232
Communication
(from Atlas)
(from Atlas)
(to Atlas)
(from Neptune)
(from Neptune)
(from Atlas)
Neptune Atlas
Communication
GND
MIC_BIAS
GND
ALERT+
ALERTGND
GND
INT_MIC+
GND
GND
RTCK
GND
TRI_SPI_CS
BB_SPI_CLK
BB_SPI_MOSI
BB_SPI_MISO
GND
PERIPH_REG
LEDKP
VBOOST
Board to Board Connector
J508
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
g1- g4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
SIM_REG
GND
SJC_MOD
ANT_DET
GND
SIM_DIO
SIM_RST
SIM_CLK
LED_CONTROL
KBC0
KBC1
KBR0
KBR1
KBR2
KBR3
KBR4
KBR5
KBR6
KBR7
ON1B
GND
(from Atlas)
(from Neptune)
(to Neptune)
(from/to Neptune)
(to Neptune)
(from Neptune)
(from Atlas)
(from Atlas)
(from Atlas)
VBOOST
DISP_LED1
DISP_LED2
DISP_LED3
DISP_LED4
GND
PERIPH_REG
GND
VBUCK
LCDC_OE
LCDC_GS
LCDC_LS
GND
LCDC_DCLK
GND
LCDC_SD
VBUCK
GND
LCDC_CM
ATI_GPIO_C1
GND
GND
(VSync)
(H Sync)
DISPLAY
CONNECTOR
J503
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
g2
g4g1g3
(ATI- Neptune
Tri-Flash -Neptune
Communication)
Output Enable
Gate Start
Latch Start
Data Clock
Serial Data
Color Mode
RESET
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GPIO_RESET
BB_SPI_CLK
BB_SPI_MOSI
BB_SPI_MISO
GA_SPI_CS
LCDC_OE
LCDC_GS
LCDC_LS
LCDC_DCLK
LCDC_SD
LCDC_CM
ATI_GPIO_C1
LCDC_RED5
LCDC_RED4
LCDC_RED3
LCDC_RED2
LCDC_RED1
LCDC_RED0
LCDC_GREEN5
LCDC_GREEN4
LCDC_GREEN3
LCDC_GREEN2
LCDC_GREEN1
LCDC_GREEN0
LCDC_BLUE0
LCDC_BLUE1
LCDC_BLUE2
LCDC_BLUE3
LCDC_BLUE4
LCDC_BLUE5
GND
ATI_GPIO_C0
GND
GND
Graphics Accelerator
Camera /Display
U1301
ATI
H16
R14
R16
SPI
R15
P16
R2
T1
R1
P1
Control
F1
E1
F16
J5
N2
H4
K4
M2
J5
M5
M1
L5
RGB Data
K5
L1
L4
M4
N1
N5
P2
N4
P4
F15
ID
(Neptume / ATI
Communication Bus
Tri Flash Write Data)
GA_INT
LCD_CLK
LCD_CS
LCD_RS
E14
P15
P19
K16
SPI
Timer
Power
Image Data
Sync.
Control
SDIO
Interface
LCD_DATA (0 - 5)
LCD_SDATA
K15
B
U19
R6
T6
T7
V6
R7
T8
R8
R9
W8
V8
W9
W6
W7
V7
L2
J2
L16
L14
L17
K17
K16
J17
CLK_32KHZ_2_7V
GA_CORE
2_7V_REG
GPIO_REG
CAM_D0
CAM_D1
CAM_D2
CAM_D3
CAM_D4
CAM_D5
CAM_D6
CAM_D7
CAM_HSYNC
CAM_VSYNC
CA_CLK_OUT
CAM_CLK_IN
CAM_SCL
CAM_SDA
CAM_RESET
U2243
U2242
CAM_PWRDWN
(GRAPH_REG)
(IO_REG)
(VBUCK)
P504
20
5
7
9
10
11
12
13
14
15
16
6
2
1
3
23
22
CAM_REG
CAMERA
CONNECTOR
CAM_REG
J500
5
2
4
3
1
G1-G4
(Shield)
Mini USB
UID
(Shield contacts)
VBUS
ESD
VR500
D526
VR524
VR523
SH10
SH11
(to Charging Circuit)
(to J508)
ESD
FL505
(to J508)
(from Atlas)
(PPD device support)
(Accessory Detection signal)
FL500
ALERT-
ALERT+
SPKRM
SPKRP
MIC_BIAS1
MIC_INM
VBOOST
VBUS
UID
DD+
V10
U8
T6
R7
P9
T9
B4
D2
H8
F3
E3
BB SAP CLK
BB SAP FS
BB SAP RX
R5
R3
P4
13 Bit
SAP
Alert
Amplifier
Handset
Amplifier
Microphone
Supply
Amplifier
Headset
Amplifier
Stereo
Det.
Headset
Det.
VBUS 5V
Pass FET
B
S
U
U
M
E
Interface
BB SAP TX
K11
VSIM_EN
R4
VSIM
N5
( 1,8/ 3V ) SIM_REG
(tx) (rx)
CODEC
16 BIT
STEREO
RF REG
H3
(to Neptune amd J508)
( 2,775V ) RF_REG
NC
NC
BT REG
K2
(to U250)
(to U301)
( 1,875V ) BT_REG
NC
NC
DET.
STEREO
U900
ATLAS UL
REG
IO REG
REF REG
CAMERA
K17
H4
L16
(to Atlas, Neptune, ATI)
(to Neptune)
(to P504)
( 2,775 ) IO_REG
( 2,775 ) CAM_REG
( 1,575V ) REF_REG
USB_VPIN
USB_XRXD RTS
USB_VPOUT TXD
USB_VMIN RXD
C4
F4
B2
B1
USB/RS232
Neptune PCap
(communication)
REG
REG
AUDIO
GRAPH
U6
M18
(only used in Atlas)
(to ATI)
( 2,775V ) AUD_ REG
( 1,275 ) GRAPH_REG
USB_TXENB
B3
PERIPH
USB_VMOUT
E4
IO REG
H2
J508)
(Atlas internal and
( 2,775V ) PERIPH_REG
BB-SPI_CLK
T17
PRI SPI
CNTL.
LOGIC
Neptune PCap
Communication
Logic
Switcher
Buck 350mA
F16
U700,ATI, )
( Atlas, Neptune,
( 1,875V ) VBUCK
BB_SPI_MOSI
T18
(to J508 Power Key)
AUL_INT
BB_SPI_MISO
AUL CS
U18
U16
Switcher
C913
N14
Boost 300mA
G16
ON
LOGIC
Motor
to Vibrator
P2
ON1B
F14
VIB REG
T14
C15
P13
AD
D14
U14
CONV.
F13
D/A
E15
B16
CHARGE
CONTR.
B12
B14
C6
LED
B6
CNTL.
D6
F6
B8
C5
D12
V17
V16
F12
B+ Sense
VCO
REG
V2
F3,E13........
TIMER
R16
P16
V12
K10
U15
E12
RTC_BATT
Y900
WDOG
TX_START
RESETB
(toNeptune)
SIM_PD
CHRGRAW
(VBUS)
THERM
(Battery Sense)
BATT+
(Batt Current)
BATTISNS
(Charge Current - )
BATTISNS
CHRGISNSP
CHRGCTRL
BATTFET
BPFET
DISP_LED1
DISP_LED2
DISP_LED3
DISP_LED4
LED_CONTROL
LEDKP
STANDBY
CLK_32KHZ
CLK_32KHZ_2_7V
CLK 13 MHZ
(Charger Current + )
(Current Control)
(to J503)
(from U806)
(to Neptune and U301 BT)
(from Neptune)
(from Neptune)
(from Neptune, Tx Mode indication for Atlas)
(from/ to Neptune and U700)
(to J1300)
BATTERY
CHARGER
(from Acesory Connector)
(EXT Power)
VBUS
(VBUS Sense)
S
M1
G
D
S
G
M2
Charger and Powersource Control
(to J5ß8)
J506
RTC
(One Wire Bus
THERM
to Neptune)
OWB
R910
BATT CONN.
3
(Bias)
IO REG
R911
D
G
S
Battery to BPLUS
Switch
M1400
2
4
VR1201 / ESD
M3
D
S
D902
1
GND
TOUT12
Color definition only for this section !
Main Charge Path
B+ support without Ext Charger
B+ support with Ext Charger
(Main Source
B+
for Atlas)
M4
G
VBUS to BP
Switch
(from Acesory Connector)
VBUS
(Bias Voltage from
Neptune)
(EXT Power)
Q901
C936
VIB_REG
( 1,3V )
VCO_REG_CNTL
(to Atlas and J508)
( 5,5V ) VBOOST
B+
VCO_REG
( 2,775V )
(to U250)
(Main Source- from M3)
VIB
Servive, Engineering & Optimization 2005.08.26
LEVEL 3 AL Block Diagram Rev. 1.0
L7
Alexander Buehler, Michael Mauderer Page 2of 3