RX MID CHANNELS
850: CH190 -- 881,6
GSM: CH 62 -- 947,4 MHz
EGSM: CH 37 -- 942,4Mhz
DCS: CH 700 -- 1842,8MHz
PCS: CH 661 -- 1960MHz
FL100
Quard Saw Filter
and Matching
1
High Band
1900MHz
3
High Band
1800MHz
4
Low Band
900MHz
6
Low Band
850MHz
4
4
FL82
FL54
14
15
12
13
10
11
8
9
2
2
Synthesizer
U250
K12
LNA
L12
G12
LNA
H12
D12
LNA
E12
A12
LNA
B12
L8
L10
TX_HB
TX_LB
Amplitude Modulation
BP
850 MHz
900 MHz
1800 MHz
1900 MHZ
VCO_REG
18,31
DCS/PCS OUT
25
1
2
11,14....
26
1
2
U50
PA + Antenna Switch
2
÷
2
÷
GSM850/
GSM900 OUT
4
÷
90°
2
÷
90°
LPF
3
3
Transmit
Modulator
DC
Correct
LPF
RX VCO
234
TX VCO
1
Power and
Antenna
Control
16
10
(PA Power Control)
VDETECT
VRAMP
B3
A4
PA Control
Digital Radio
Receiver
RX CP
TX CP
Phase Modulation
LPF
Internal
Antenna
M1
ANT_DET_B
J7506
6
17
8
13
15
9
PA Power Control selection via VRAMP, TX_HB and TX_LB
1. IPC: Input Power Control mode - for EDGE mode
(PA gain is fixed and PA input power varies)
2.BCM: Bias Control mode - for GMSK mode
(PA gain varies according to power step and fixed input PA power)
(Transmitt Enable)
TX_EN
US_EURO
TX_ANT_SW_EN
LB_HB
IPC_BCM
TX_START
RESETB
(Transmitt Enable)
A1
C2 A2
C3
B2
GPIO
Synthesizer
ADC
Vol t age
Reg.
RX / TX
RX / TX
Serial
B9
E2
G1
STANDBYB
(Data TX)
DRI
(TX/RX Ena ble)
MS
(Data RX)
MDI
(readback)
MISOB
(only used in Engineering debug mode
- not for Service)
MCLK
BT_CLK
BT_CLK_EN
1
2
Y201
3
26MHz
RF_DATA
RF_CLK
RF_CS
VCO_REG
VM_REG
VBUCK
RF_REG
IO_REG
REF_1p2
(Data In /OUT)
(Clock )
(Chip select)
(VCC’s from Atlas)
In / Out - Put contr oler
Clock
Interface
J5, J8
G2
D1
E3
G3
F3
J1
J3
K4
K5
D2
F1
E1
C10
H2
B4
C1
C5
(indicates mechanical Antenna connection to U800)
Mechanical
Antenna Switch
(U250 Control Bus)
NEPTUNE LTE2
U800
L1 Timer
U6
N10
W10
GPIO
U9
T8
26 MHz
A4
Oscillator
U8
V7
SPI
W9
UART / USB
A17
B16
C15
Interface
D15
C16
A16
Keypad
Interface
F3....
F2....
W13
BP
5,6
2
U700
F4
E4...
(LCD Control to J2 )
2
U807
Switch
3
RESET OUT
VBUCK
Hall Effect
1
U1600
6
(from Neptune)
(from
Atlas
(Flip Open/ Close
Detect)
)
IO_REG
M18
H1
Power
A11, U16, .....
V5, R16, ....
SIM
Interface
External
Memory
Interface
MQSPI
Display
GPIO
E2
K2
K3
J4
L1
R1
M1
W18
V17
T18
G17
K16
J19
T16
T19
L16
N18
D14
P2
N3
M4
P1
L3...
D18
U12
U10
N9
W8
Clock Generator
DSP Peripherals
accelerator, encryption
Timer, Interupts
DSP
UltraLite
104 MHz
Shared Memory
1Mbit RAM
MCU
ARM7
52 MHz
DSP
Memory
MCU
Memory
V8
On
Off
T11
V12
MQSPI
W12
V11
B14
T10
B
aseBand
U13
One
Serial Audio
Wire
Port Interface
Bus
W11
D13
(rx)
A12
U11
E3
W5
Timer
Interface
V13
G8
B12
UART2
Universal
Asynchron.
(tx)
Rx /Tx
B13
N13
D16
N17
V16
D19
A12
BT
C14
B15
T7
REG_BYP_CORE
(VCC + 2.775V)
IO_REG
PERIPH_IO_REG
(VCC + 1,575V)
REF_REG
(VCC + 1,875V)
VBUCK
(from Atlas )
VSIM
(Data In /OUT)
SIM DIO
(Reset )
SIM RST
(Clock )
SIM CLK
SIM_PD
(from Atlas )
(to Atlas)
VSIM_EN
DATA BUS
ADDRESS BUS
CS0B
CS1B
CS2B
EB1B
EB0B
R_WB
OEB
BURSTCLK
LBAB
ECBB
LCD_OE
LCD_RS
LCD_CS
LCD_CLK_DATA6
LCD_SDATA_DATA7
LCD DATA (0 - 5)
LCD_WEB
ANT_DET_B
(Bias output for THERM signal)
TOUT12
(EL Backlight Enable to U1501)
EL_EN
TF_ENABLE
TX_EN_SW
EMU_HDST_DET
HS INT
(VCC + 2.775V)
(from / to J24_DB)
D0-15
A0-23
K1
G8
D6
F3
FLASH
C2
F5,D5
J2,H1,H8
C6
E5
G7
16 MB SRam
64 MB Flash
(indicates mechanical Antenna connection to U800)
(Trans Flash Enable to J27 )
(to Atlas U900)
(to Atlas U950 )
Inverter
4
U1401
5
PERIPH_IO_REG
(clock)
(framesync)
OWB
K1
USB_VPIN
USB_XRXD_RTS
USB_VPOUT_TXD
USB_VMIN_RXD
Neptune Atlas
USB/ RS232
Communication
USB_SE0
Key-Matrix
0-9,*,#
Navigation,
Smart,
Vol um e
Neptune Atlas
(13 MHz)
Communication
CLK 13 MHz
BB_SPI_CLK
KBC0-2
KBR0-7
USB_TXENB
(from J5000 via J2 )
BB_SPI_MISO
BB_SPI_MOSI
AUL_INT
AUL_CS
GRAPH_INT
STANDBY_1_5V
2
U801
Level
Shift
4
BB_SAP_FS
BB_SAP_CLK
(from/ to Neptune
Serial Audio for Ringtone
and Voic e Audio)
One Wire data from Battery
(Watchdog)
ATI_RESETB_2_7V
RESETB
RESET OUT
CLK 32KHZ
WDOG
STANDBY
(to Atlas )
(to J2)
(from Atlas)
(to U700)
(to Atlas)
(from Atlas)
BLUE_RX
BB_SAP_RX
BB_SAP_TX
Communication and Wakeup)
BLUE_RTSB
BLUE_TX
BLUE_CTSB
BLUE_HOST_WAKEB
(from/ to U301 BT, J1300
Neptune - BT - Neptune
BLUE_WAKEB
BT_RESET_B
Revision Overview
Rev. 1.0: Initial Block Diagram
Rev. 1.1: updated U700 Memory size
Rev. 1.2 updated MISOB information,updat ed information at
U950 Headset detect circuit, updated information at U50 /
IPC_BCM
Rev. 1.3: RX signal name#s change + Pins on U50
Servive, Engineering & Optimization 2006.12.1
LEVEL 3 AL Block Diagram Rev. 1.3
K1
Page 1of 2
J1
G1-G4
EL_EN
VBOOST
Mini USB
1
4
2
3
5
(Shield)
Bluetooth
(from/ to U301 BT,
Neptune - BT - Neptune
Communication and Wakeup)
VR960
VR1203
VR1212
VR1212
U1501
EL Driver
3
10
PERIPH_IO_REG
(from Atlas)
BLUE_WAKEB
BLUE_HOST_WAKEB
(to U250)
(from U250)
(from Atlas)
ALERT
Internal
VBUS
ESD
8
Bluetooth
B3......
BP
BLUE_RX
BLUE_TX
BLUE_CTSB
BLUE_RTSB
STANDBY
BT_RESET_B
BT_CLK_EN
BT_CLK
CLK_32KHZ
H6
E5
E4
E8
E7
C8
C6
C4
E3
D7
E2
F6
M1401
2
PCB
1
Pads
(to J2)
4
MIC
3
(to Charging Circuit)
(PPD device support)
(Accessory Detection signal)
Headset detect circuit
U950
R950
(100K Headset
detect Resistor)
EMU_HDST_DET
(Headset detect Enable from Neptune)
EL_LAMP_VP
EL_LAMP_VM
U301
ESD
FL1400
(from Atlas)
(Bias from Atlas)
PERIPH_IO_ REG
(on PCB)
Strip Line
Antenna
BT_ANT
25
H1
H2
BB_SAP_RX
C7
BB_SAP_FS
A7
BB_SAP_CLK
B6
BB_SAP_TX
C7
ALERTM
ALERTP
HAND_SPKRM
HAND_SPKRP
MICBIAS1
MICINM
VBOOST
VBUS
USB_ID
DM_TXD
DP_RXD
FL301
(framesync)
(clock)
NC
NC
NC
V10
U8
T6
R7
P9
T9
B4
D2
H8
F3
E3
(from/ to Neptune
Serial Audio for Ringtone
and Voice Audio)
(tx)
(rx)
BB_SAP_TX
BB_SAP_FS
BB_SAP_RX
BB_SAP_CLK
R5
R3
P4
13 Bit
SAP
Alert
Amplifier
Handset
Amplifier
Microphone
Supply
Amplifier
Headset
Amplifier
Stereo
Det.
Headset
Det.
VBUS 5V
Pass FET
B
S
U
U
M
E
Interface
VSIM
REF REG
N5
R17
K11
R4
RF REG
H3
GND
(tx) (rx)
CODEC
16 BIT
STEREO
RF REG
H3
Daughter Board
J6
7
8
1
2
G1-G3
3
Transflash
5
4
DIG REG
P18
CAMERA
H4
J4
SIM
REG
1
2
3
4
5
6
Neptune Atlas
Communication
USB_VPIN
B2
USB/RS232
NeptuneAtlas
(communication)
IO REG
REF REG
K17
L16
TF_VDD
USB/ RS232
USB_XRXD_RTS
USB_VPOUT_TXD
C4
F4
GRAPH
M18
USB_VMIN_RXD
B1
REG
USB_TXENB
B3
B+ Sense
AUDIO
U6
Q2000
+
BATT
USB_SE0
E4
Logic
U900
ATLAS UL
REG
Switcher
PERIPH
IO REG
H2
RTC
BB_SPI_MOSI
BB-SPI_CLK
T17
T18
PRI SPI
CNTL.
LOGIC
Neptune Atlas
Communication
Switcher
Buck 350mA
F16
FL1200
BB_SPI_MISO
U18
U16
Boost 300mA
G16
AUL CS
J27
14..
AUL_INT
N14
VCO
V2
3
VCO_DRV
Daughter Board Connector
REG
Flip Connector
FL3002
(One Wire Bus
THERM
to Neptune)
OWB
R910
FLIP CONNECTOR
J2
50
49
48
47
46
45
44
43
41
42
40
39
37
38
35
36
34
33
32
31
29
30
27
28
26
25
24
23
21
22
19
20
18
17
15
16
13
14
11
12
10
9
7
8
5
6
3
4
2
1
g1- g4
BATT CONN.
3
2
(Bias)
VR1201
PERIPH REG
R911
D
G
Q904 (M3)
S
Battery to BPLUS
Switch
G
CLK_32KHZ_2_7V
GND
GND
SDC0CLK
GND
LCD_DATA3
LCD_DATA0
LCD_DATA5
LCD_DATA6
SDC0CMD
GND
BB_SAP_RX
BB_SAP_TX
BB_SAP_CLK
BB_SAP_FS
PERIPH_IO_REG
VBOOST
GND
BLED_SINK3
BLED_SINK1
BLED_SINK3
BLED_SINK4
GND
HAND_SPKRM
HAND_SPKRP
GND
J3
4
1
BATTP
Color definition only for this section !
D
Q903 (M4)
S
VBUS to BP
D903
(SD Card Clock from U5000)
(LCD Data from Neptune)
(SD Card Command from U5000)
(Control Bus for ATI
from/ to Neptune)
(from Atlas)
GND
TOUT12
Main Charge Path
B+ support without Ext Charger
B+ support with Ext Charger
(Main Source
BP
for Atlas)
Switch
(from Mini USB Connector)
VBUS
(from Atlas)
(from Atlas)
(Bias Voltage from
Neptune)
(EXT Power)
(to Atlas)
FL3001
11
13
1
3
5
9
7
12
8
2
6
4
10
SDC0DQ0
SDC0DQ1
SDC0DQ2
SDC0DQ3
SDC0CMD
SDC0CLK
PERIPH_IO_REG
TF_ENABLE
SIM_DIO
SIM_CLK
VSIM
SIM_RST
GND
RTC_BATT
(SD Card Data
from/ to Daughter
Board Conn. J27)
(LCD Data from Neptune)
(fitered VCC from Atlas)
(interupt from U5000
to Neptune)
(LCD Control
from Neptune)
(fitered VCC from Atlas)
(from Atlas)
(from Neptune)
(from Atlas)
(from J1)
(from Atlas)
SDC0DQ0
SDC0DQ2
SDC0DQ3
SDC0DQ1
GND
LCD_DATA7
LCD_DATA4
LCD_DATA1
LCD_DATA2
GRAFX_REG_FL
CAM_AVDD_FL
GND
GRAPH_INT
LCD_WEB
LCD_OEB
LCD_CS
LCD_RS
CAM_DIG_REG_FL
VBUCK_FL
GND
IO_REG
ATI_RESETB_2_7V
LEDB1
VBUS
CHRGLED
Charger and Power-
source Control
Charger
(from Acesory Connector)
(EXT Power)
Q905 (M1)
G
G
VBUS
R905
S
D
S
PWR_SW
SIM_PD
CHRGLED
CHRGRAW
THERM
(Battery Sense)
BATTP
(Batt Current)
ISNS
(toNeptune)
(toFL3002)
(VBUS Sense)
(Charger Current + )
(Current Control)
ON
LOGIC
F14
AD
CONV.
D/A
CHARGE
CONTR.
T14
L10
C15
P13
D14
F13
U14
E15
B16
CHRGISNSP_PM
CHRGCTRL
Q906 (M2)
B12
B14
C6
LED
B6 BLED_SINK2
CNTL.
D6 BLED_SINK3
F8
D12
V17
V16
R16
P16
TIMER
V12
K10
Motor
to Vibrator
VIB REG
F3,E13........
4
P2
U15
P14
F12
E12
BATTFET
BPFET_PM
BLED_SINK1
BLED_SINK4
RTC_BATT
Y900
CLK_32KHZ
CLK_32KHZ_2_7V
CLK 13 MHZ
(from Neptune)
WDOG
TX_EN_SW
STANDBYB
STANDBY
RESETB
(from FL3001)
(from J1300)
(to Neptune and U301 BT)
(to J1300)
(from Neptune)
(from Neptune, Tx Mode indication for Atlas)
(to U250)
(from U800)
(to Neptune, U250)
Q910
1
VVIB
K1
( 1,2V ) REF_1P2
(to U250)
VSIM_EN
(from U800)
( 1,3V )
( 2,775V ) RF_REG
(2,775V ) VM_REG
( 1,8/ 3V ) VSIM
(to U250)
(to Neptune amd J27)
( 1,8V ) CAM_DIG_REG
(to U250)
(to J2, J1000, J2000)
( 2,775 ) CAM_AVDD
( 1,575V ) REF_REG
(to Neptune)
(to J2, J1000, Q2020)
( 2,775 ) IO_REG
(to AL + RF))
( 2,775V ) PERIPH_IO_ REG
( 2,775V ) AUD_ REG
( 1,275 ) GRAFX_REG
(to J2)
(only used in Atlas)
( 5,5V ) VBOOST
( 1,875V ) VBUCK
(to AL + RF))
(to AL + RF))
J3500, U1501)
(to J2, J1000, D1000
BP
( 2,775V ) VCO_REG
(Main Source- from Q904)
(to U50,U250)
1
JVIB
2
Revision Overview
Rev. 1.0: Initial Block Diagram
Rev. 1.1: updated U700 Memory size
Rev. 1.2 updated MISOB information,updat ed information at
U950 Headset detect circuit, updated information at U50 /
IPC_BCM
Rev. 1.2: RX signal name#s change + Pins on U50
Servive, Engineering & Optimization 2006.12.1
LEVEL 3 AL Block Diagram Rev. 1.3
K1
Page 2of 2