Motorola E6-0001, E6 Schematic

RX MID CHANNELS

850: CH190 -- 881,6

GSM: CH 62 -- 947,4 MHz

EGSM: CH 37 -- 942,4Mhz

DCS: CH 700 -- 1842,8MHz

PCS: CH 661 -- 1960MHz

HB_TX_OUT

LB_TX_OUT

(PA Detect to Neptune)

PCS_RX_50

DCS_RX_50

GSM_RX_50

CELL_RX_50

1900 MHZ

1800 MHz

900 MHz

850 MHz

BPLUS

ISENSE

DCS/PCS OUT

9

1

2

5

1
2

1

2

U150
PA + Antenna Switch

GSM850/

GSM900 OUT

from Neptune

( Frontend Control

and Digital Modulation)

MCLK

Internal
Antenna

P101

Mechanical

Antenna Switch

3

3

16

15

14

(NC)

TXIMSMDI

Power and
Antenna
Control

8

13

(PA Power Control)

RAMP

21

6

4

7

3

(Transmitt Enable)

(Band select)

TX_EN

CNTRL_2

CNTRL_3

CNTRL_1

J100

ANT_DETB

( to Neptune)

REG_BYP_CORE

(from PCAP /Bias)

BPLUS

D2 G1

D1, G2

Q801

S1,S2

Neptune

„Bypass-Caps“

Reset Circuit

RESETB

(from PCap)

C805-C808

M18....

V5

NEPTUNE LTS

( to PCap )

TX_START

(Receive Enable)

TX_START

RX_ANT_EN

(Transmitt Enable)

(to U200)

( Frontend Control

and Digital Modulation)

(Data In /OUT)

(from PA)

(Clock )

(Reset )

ISENSE

MCLK

MS

MDI

T9
W10
U9

U6
V8

B10

SPI

L1 Timer

PA Control

U800

DSP Peripherals

accelerator, encryption
Timer, Interupts

DSP

UltraLite
104 MHz

Shared Memory

1Mbit RAM

DSP

Memory

POWER

SIM

Interface

M17

E2

C5

A11
H1

K2
K3

J4
L1
R1
M1

NEP_AVDD
VBUCK
BB_IO_REG
REF_REG
BB_IO_REG_NEP

AP_IO_REG
V_SIM
SIM DIO

SIM RST
SIM CLK

SIM_PD

VSIM_EN

DATA BUS
ADDRESS BUS

(VCC + 1,875V)
(VCC + 1,875V)

(VCC + 1,875V)

(VCC + 1,575V)

(VCC + 2.775V)

(VCC + 2,775V)

(from /to Daughter Board)

(to Pcap)

D0-15

A1-24

VBUCK

(VCC from PCap)

(VCC from PCAP)

D2

C3

D6 G5

G8

D7E8E7

A2

SAW/ LNA

LNA

Matching

A3

SAW/ LNA

LNA

Matching

A5

SAW/ LNA

LNA

Matching

A6

SAW/ LNA

LNA

Matching

G1

F1

Quadrature
Mixer

Quadrature
Generator

Polyphase
Filter

DC
Correct

( VCO Feedback )

( VCO Tuning)

VCO1 (TX_LB)

VCO2 (TX_HB)
TX_EN

IIN

RX/TX

IBIN

Switch

(100KHz)

QBIN

RX/TX

QIN

Switch

U100

GSM/ EDGE

TRANCEIVER

FIN

ADC
13 bit

ADC
13 bit

Loop Filter

Sync
Filter

Sync
Filter

Digital TX
Interface

GMSK
Modulator

Phase Det.

(100KHz)

Devider

CP

Anti
Drop

Anti
Drop

EDGE
Modulator

Anti
Alias

Anti
Alias

EDGE
FIR
Filter

GMSK/ EDGE Select

Pre-Distortion
Filter

DAC1

Chanel
Filter

Chanel
Filter

Anti
Alias

PA Control

B7

GPIO

DAC
12 bit

DAC
12 bit

Reference
Devider

Serial
Interface

C2

E6

LPF

LPF

Oscilator and

ADC
Voltage
Reg.

Output Mixer

Serial

F8

F7

F6

H7

D8
G7

E5
C5
C6

Clock Generator

F4
F5

G4

Interface

G3

H3

B8..
C1..

ENR
CLKR
FSR
DRI

OSCO
AP_IO_REG_RF

OSCM

1

Y100

3

26MHz

RF_DATA
RF_CLK
RF_CS

LDTO

( Lock Detect Out)

(VCC’s from PCAP)

VCO_REG
AP_IO_REG_RF

RF_REG

(Clock enable)

2

(NC)

OSCO_F

(VCC)

(U250 Control Bus)

OSCM

(from U900)

BB_IO_REG

4
Inverter

U804

2

BP_SLEEP_RQST

W7
G12

VoiceBand

A13
N10

26 MHz

A4

Oscillator

(Data In /OUT)

U8

(Clock )

V7

(Chip select)

(from PCAP)

(Sleep Mode Indication to Clock Circuit) (Clock disable/ enable)

SPI

W9

UART / USB

Interface

A17

A16

C16

C15

NEP_ICL_SE0

NEP_VPIN

NEP_ICL_VPOUT

Neptune Bulverde

USB

Communication

On
Off

Keypad
Interface

D15

B16

NEP_ICL_XRXD

NEP_VMIN

NEP_ICL_TXENB

P16

CLK 13MHZ_1_8V

(13 MHz to PCap)

V12

T11

BB_SPI_CLK

Neptune PCap

Communication

MQSPI

V11

BB_SPI_MOSI

W12

BB_SPI_MISO

B14

PCAP_CS

PCAP_INT

G8

2
Level

Shift

U803

T10

BP_SLEEP_RQST_1_5V

AP_SLEEP_RQST

(from PCAP)

4

Clock Generator

Timer

Interface

V13

U13

W5

BB_WDOG

RESET OUT

NEP_RESET_INB

(to U805)

(from U801)

(BP-AP Watchdog)

MCU

ARM7

52 MHz

E3

CLK_32KHz_1_5V

(from Level Shifter U2009)

One

Wire

Bus

W11

BaseBand
Serial Audio

Port Interface

D13

(clock)

OWB

One Wire data from Battery

(rx)
A12

BB_SAP_CLK

(framesync)

(from/ to Neptune

BB_SAP_FS

B12

Serial Audio for Ringtone

(tx)

( TX Audio Data )

Memory

B13

( RX Audio Data )

BB_SAP_RX

( Mono )

and Voice Audio)

MCU

BB_SAP_TX

Universal

Asynchron.

UART2

Rx /Tx

External

Memory

Interface

MQSPI

Display

GPIO

G17
K16

W18

V17
J19
T16
T19
L16
N18

M2
N1

V14

U12

EB1_B
EB0_B

CS0B
CS1B
R_WB
OEB
BURSTCLK
LBAB
ECBB

( from U2000)

AP_READY

( to U2000)

BP_READY

1

BP_OPT1

W8

BP_OPT2

ANT_DETB

4

( from Mech Antenna Switch)

F3
C2
K1

FLASH

D6,J1
F5,D5
J2,H1
C6
E5

G7

2MB Ram

4 MB Flash

( Bulverde / Neptune Handshake)

U809

5

Switch

6

U805

(from Neptune)

F4

RESET_OUT

VCC_NEP_MEM

B5...

E4

BB_IO_REG
BP_FLASH_MODE_EN

(from Bulverde -forces Neptune in Flash Mode)

Revision Overview

Rev. 1.0: Initial Block Diagram

( VCC)

VBUCK

( VCC
from PCap)

E6

BP_SLEEP_RQST

to PCap )

(Sleep Mode Indication

GSM SERVICE SUPPORT GROUP 2006.11.10

LEVEL 3 AL Block Diagram Rev. 1.0

E6

Page 1of 3

VBUCK

(VCC from PCap)

PCUTS_VCC

AP_SLEEP_RQST

(Bulverde to PCap Sleep Indicator)

B6...

B2,B4,.....

SDRAM
(48MB)

Flash
(64MB)

( to FM Chip U500))

E6

(13MHz Clock to U900)

(from Level Shifter U2006)
(to U2005)

ADDR:BUS10

H4

N11

U2001

C6
AB7
AD6

AA6
AC7
AD6
AB9

AB10

B3

AC5
AB5

E4

NRESET_OUT

U911

( Bulverde / Neptune Handshake)

( from / to Daughter Board)

(from/ to Neptune

Serial Audio for Ringtone

MMEDIA_13MHz

CLK_32KHZ_1_5V

1-25

0-15

and Voice Audio)

(from U901 EMU IC)

13 MHz

ADDR. BUS
DATA BUS

SDCLK0
SDCLK2
SDCLK3

NSDCS0

NSDCS3
NSDCAS
NSDRAS

SDCKE

DQM0
DQM1

NRESET_OUT

AP_CLK_RQST

AP_READY
BP_READY

BT_TXD
BT_RXD
BT_CTS
BT_RTS
BT_NRESET
BLUE_WAKEB

BLUE_HOSTWAKEB

(clock)

(framesync)

( TX Audio Data )

( RX Audio Data )

(from/ to
Audio Circuit)

(from EMU IC)

(from/ to
Audio Circuit)

(to EMU IC)

(from/ to

Audio Circuit)

(from/ to J400)

Y2000

NCS0

NOE

NWE

BB_SAP_CLK
BB_SAP_FS
BB_SAP_RX

BB_SAP_TX

( the PCap is Master for

AUDIO_IN
HJACK_DET
INT_MICP

MIC_BIAS1
HJACK_MIC

MIC_BIAS2
ALERTM_PAD

ALERTP_PAD
AL_OUT

AR_OUT
PGA_INR
PGA_INL
HAND_SPKRP
HAND_SPKRM
HJACK_SPK_L
HJACK_SPK_R

U22

AA22
AD21
AC21

AC4
AD7
AD3

D1
C1

L1
M1
N1
E1
F1

G8

J8
E3

Y21

Y23

AC19
Y22

C22

C21

C19

B20

A15
AC11

C10

Audio Clock and
Framesync.)

TSY2
TSY1

TSX2
TSX1

VBUCK

XTAL

INT.

MEM.

Int.

GPIO

(framesync)
(clock)

(Voice, BT Audio)

D13

BB_SAP_CLK

K7
H5

R1
N3

R2

M2

F1
H1
K3
L2

J7
L6
J4

K2
K3

L2

T4
R4
T2
T3

U13

VHOLD_EXT_EN

Q907

( 1,8V )

VCC_STACKED_MEM

SSP2/

Codec1

T24

C23

BB_SAP_FS

BB_SAP_RX

F6

H7

(tx) (rx)

CODEC

13 BIT

PHONE
AUDIO

AMPL.

TOUCH

SCREEN

INTERF.

MEMORY

HOLD

(rx)

(tx)

B14

BB_SAP_TX

F5

H8

AUX2

K14

B

PNP

Q908

E

C

BPLUS

VCC_TRANSFLASH

( 2,80V )

SSP3/

Codec2

(Application Aud.)

(rx)

(tx)
AB12

AD10

AC14

AD9

BB_SAP_RX

AP_SAP_FS

AP_SAP_CLK

AP_SAP_TX

D2D3B2

(tx) (rx)

CODEC

16 BIT

STEREO

VSIM

E10

B7

H14

VSIM_EN

( Not used)

( 1,8/ 3V ) VSIM

U2000

Bulverde

(Aplication Processor)

CPU

Flash
32MB

(Bias)

HJACK_SPKL

ST_REF

NC

G3

H6

G7C6C5F7E5

G8

USB/RS232

(communication)

Stereo

Detect

U900

PCAP3

V8

V9V10

N12

G17

A7

A6

B

PNP
E

RF_REG

BPLUS

( 1,275V )VCC_PLL

( 2,775V )

( 1,575V ) REF_REG

SSP1/

1st Serial

Interface

B15

D16

AP_SPI_MOSI

AP_SPI_MISO

P8

R7

PRI SPI

CNTL.

LOGIC

V5V6V7

Q901

C

BT_RF_REG

( 2,775V )

B13

M15

( 2,775V ) VCO_REG

Y24

AP_SPI_CLK

M8

V4

A17

AP_PCAP_INT

L10

H15

( 2,775V ) BB_IO_REG

Neptune PCap
Communication

AP_PCAP_CS

K9

Logic

F17

( 1,275 ) VCC_SRAM

BB_SPI_MISO

BB_SPI_MOSI

BB-SPI_CLK

E11

F11

C12

SEC SPI

CNTL.

LOGIC

V2V3

U1

( 2,775V ) AUD_REG

Key Lock Switch

AUDIO_REG

Current

L401

U404

1
5

6

(from PCAP )

VBUCK

GND

(VCC from PCap)

(I2C Data Bus to FM Receiver

and Funlight Driver)

(VCC from PCap)

2

BPLUS

BLK_PWM

4

(from/to USB 2.0)

S402

(forces Neptune in Flash Mode)

BP_FLASH_MODE_EN

AP_IO_REG
VBUCK
AP_CORE

VCC_SRAM

( VCC fromU901)

(FM IC interupt)

(Interupt from U901)

(Enable to EMU IC)

USB20_SWITCH

2

KEY_LOCK

I2C_RESET
I2C_SCL
I2C_SDA

VCC_PLL
BUL_VCC_IO
BUL_VCC_BB
BUL_VCC_BATT
BUL_VCC_LCD
BUL_VCC_MEM

(Backlight Enable)

FM_INT

EMU_INT

USB_READY

nPWE

USB20_INT

USB20_Ready

USB20_DREQ0

USB20_nCS1

A3

Generic

C18

GPIO

A14
D20
A22

AC20
A12
AD12
AB20

Power

J24
A4
A7
A5

A18

Generic

GPIO

C16

V23
AB18

A10
R22

B9
AB5

C8

AD19

USB/ Client

Port 2

EMU -Bulverde

(communication)

D19

D14

AB14

C14

A21

B19

U2000

Bulverde

USB/ Host

Port3

Bulverde Neptun
(communication)

F22

AB11

C13

C12

A13

F23

Data

C7

MMC_D0
MMC_D1
MMC_D2
MMC_D3
MMC_CMD
MMC_CLK

SD_nCD

SD_nWP

CAM_CLKIN
CAM_DATA(0-7
CAM_EN
CAM_VSYNC_F
CAM_HSYNC_F

LCD_ID0
LCD_ID1
LCD_OE
LCD_VSYNC
LCD_HSYNC
LCD_MCLK
LCD_SD

LDD0-LDD17

KP_BL_EN

KBR0
KBR1
KBR4
KBR3
KBC1
KBC5
KBR2
KBC2

Camera

PWR_SW

S401

Data
Data
Data

Command
Clock

Card detect
Write protect

(2 pole filter)

Q401
Q402
Q403
Q406

Timing

Trimmer

J401

24
8
4
14
12
16
10

18
6

20

(from /to Daughter Board)

(from PCap)

AP_IO_REG

VBUCK

CAM_EN_F

1

9

6

4

CAM_VSYNC
CAM_HSYNC

2

8

U2010

1

J400

2
4
8
12
16
20

27....

11

9
7
5

Connector

Keypad

GND

Display

Connector

1,10...

22,26

2
6
7,8..
24

11...
4
10
9

5

J403

1
23
21

Camera

Connector

CAM_CLKOUT_RAW

20

Constant

Backlight Supply

D101

32

LED+

1,4V

LED-

38

GND

VBUCK
AP_IO_REG

TSY2
TSY1
TSX2
TSX1

(from U2000)

(VCC from PCap)

( to PCap )

28

L413

L410-

A19
D17

GPIO

B17

GPIO

Kamera

LCD

Keypad

GPIO

C17
B18
A20
C11

B16

C15...

AB13
AA11
AA12
AA14

R21
R23
R21
R23
P23
P22
B7

G24..

D22
AC18
AC17
AD18
AA17
AD15
AD14

AB17
AB16

SD Card

Display

Interface

GPIO/

Timer

W23

AA10

BB_WDOG W21

C24

Y22

BP_RESETB

U801

(to Neptune)

POWER/

FAIL DET.

AB24

U910

POWER_FAIL_N

NEP_RESET_INB

PCAP_MCU_RESETB

PCAP_INT

PCAP CS

AP_WDOG

D15

H12

H9

V1

Switcher 2

Switcher 3

Buck Mode

Boost Mode

F10

D10

H17

(to U901 / U403)

SYS_RESTART

K11

TIMER

Switcher 1

Buck Mode

F15

G12........

PCAP_BP

K12

B Sense

RESETB

L12

RESETB

to Vibra

(to Q801)

VIB

DRIVE

POWER

FAIL DET.

L17

( 1,3V )

2

POWER_FAIL

N9

ON

LOGIC

LCELL_BYP

J12

AD

CONV.

D/A

IO

CHARGE
CONTR.

OVER
VOLT.
CNTL.

LED

CNTL.

BACKl.
CONTR.

TIMER

T10

C962/963

N13

A5
T16
R17
M11

U5

N8

K13

R15

K16
K15

K17

C2
C1

P10

M9
P15
U8

U10

T7

T11

ACC_ID
EMU_PWR_ON
BATTP
BATTI
THERM

THERMBIAS

SIM_PD

NC

BL2_SINK
BL_FDBK

BL_SINK

CLK_13MHZ_1_8V
MMEDIA_13MHZ
BP_SLEEP_RQST
AP_SLEEP_RQST

TX_START

Y900

CLK_32KHz

RTC_BATT

( from /to J401)

(Accesory ID from U901)

(External B+ Sense from U901)

(Battery Current Sense from R921)

(Battery Sense )

(Thermistor from Battery)

(to

Neptune

)

( from /to J401)

( from Neptune (Clock Source))
( from Bulverde) (Clock Source))

(Sleep Mode Indication)

(Sleep Mode Indication)

(from

Neptune

)

(Level Shifter)

24

U501

(RTC Batterie)

+

J900

-

M901

4

THERM

Battery

Connector

(disables: RF_REG, BB_IO_REG, VCO_REG)

(disables: AP_CORE,VCC_SRAM, VCC_PLL)

CLK_32KHz_1_5V

CLK_32KHz

(to U2000+U300+U800)

(to U500 / FM IC)

2
3
1

BATTP

(OWB Battery Data to Neptune Interface)

OWB

GND

R921

BATTI

(from R901 - Charger)

Revision Overview

Rev. 1.0: Initial Block Diagram

EMU_USB_VPIN

EMU_USB_VPOUT_TXD

EMU_USB_SE0

EMU_USB_TXENB

EMU_USB_VMIN_RXD

Bulverde -EMU- IC

USB

Communication

EMU_USB_XRXD

NEP_ICL_SE0

NEP_ICL_VPOUT

Bulverde - Neptune

Communication

USB

NEP_ICL_XRXD

NEP_ICL_VPIN

NEP_ICL_VMIN

NEP_ICL_TXENB

Q990

(to J402) VVIB

GSM SERVICE SUPPORT GROUP 2006.11.10

LEVEL 3 AL Block Diagram Rev. 1.0

BPLUS

AP_IO_REG

( 2,775V ) AP_IO_REG

( 1,875V ) VBUCK

( 5,5V ) VBOOST

(Enable)

( 1,2V ) AP_CORE

E6

Page 2of 3