MOTOROLA DSP56366 Technical data

Advance Information

DSP56366/D Rev. 1.6, 01/2004

24-Bit Audio Digital Signal Processor

Freescale Semiconductor, Inc.

Topic Page

Overview ............................ .........i

Signal/Connection

Descriptions ....................... 1-1

nc...

Specifications .......................... 2-1

Packaging .................... ...........3-1

Design Considerations ...........4-1

Ordering Information ...............5-1

Power Consumption

Benchmark ....................... A-1

IBIS Model .............................B-1

cale Semiconductor,

Overview

The DSP56366 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56366 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Motorola Symphony™ DSP family, as shown in Figure 1. This design provides a two-fold performance increase over Motorola’s popular Symphony family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct memory access (DMA). The DSP56366 offers 120 million instructions per second (MIPS) using an internal 120 MHz clock at 3.3 V.

Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

“asserted” Means that a high true (active high) signal is high or that a low

“deasserted” Means that a high true (active high) signal is low or that a low

Used to indicate a signal that is active when pulled low (For example, the RESET

true (active low) signal is low

true (active low) signal is high

pin is active when low.)

Frees

This document contains information on a new product. Specifications and information herein are subject to change without notice.

IMOTOROLA DSP56366 Advance Information i

Examples: Signal/

Symbol

PIN PIN False Deasserted VIH / V PIN True Asserted VIH / V PIN False Deasserted VIL / V

Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product

specifications.

Logic State Signal State Voltage*

True Asserted VIL / V

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Overview Features

TRIPLE

TIMER

nc...

CLOCK

cale Semiconductor,

DAX (SPDIF Tx.)

ADDRESS GENERATI

SIX CHANNEL

INTER NAL

PLL

EXTAL

RESET

PINIT/NMI

HOST INTER

PROGR AM

ESAI

INTER-

FACE

ESAI_1

PERIPHERAL

EXPANSION AREA

PIO_EB

24-BIT DSP563

PROGR AM

MODA/IRQA MODB/IRQB MODC/IRQC

MODD/IRQD

SHI INTER

PROGRA M RAM /INSTR. CACHE 3K x 24

PROGR AM

MEMORY EXPANSION AREA

X MEMOR Y RAM 13K X

PM_EB

YAB XAB PAB DAB

DDB YDB XDB PDB GDB

DATA ALU 24X24+56->56-BIT

Figure 1 DSP56366 Block Diagram

Y MEMOR Y RAM 7K X 24

XM_EB

24 BITS BUS

YM_EB

EXTERNAL ADDRESS

BUS

SWITCH

DRAM & SRAM BUS

EXTERN AL DATA

POWE

JTAG

OnCE

ADDRESS

CONTROL

DATA

Frees

1 Features

1.1 DSP56300 Modular Chassis

• 120 Million Instructions Per Second (MIPS) with an 120 MHz clock at 3.3V.

• Object Code Compatible with the 56K core.

• Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support.

• Program Control with position independent code support and instruction cache support.

• Six-channel DMA controller.

ii DSP56366 Advance Information MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

• PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors (1 to 16) and power saving clock divider (2

• Internal address tracing support and OnCE for Hardware/Software debugging.

• JTAG port.

• Very low-power CMOS design, fully static design with operating frequencies down to DC.

• STOP and WAIT low-power standby modes.

: i=0 to 7). Reduces clock noise.

Overview

Features

1.2 On-chip Memory Configuration

• 7Kx24 Bit Y-Data RAM and 8Kx24 Bit Y-Data ROM.

• 13Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM.

• 40Kx24 Bit Program ROM.

• 3Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 1K of Program RAM may be used as

nc...

Instruction Cache or for Program ROM patching.

• 2Kx24 Bit from Y Data RAM and 5Kx24 Bit from X Data RAM can be switched to Program RAM resulting in up to 10Kx24 Bit of Program RAM.

cale Semiconductor,

Frees

1.3 Off-chip Memory Expansion

• External Memory Expansion Port.

• Off-chip expansion up to two 16M x 24-bit word of Data memory.

• Off-chip expansion up to 16M x 24-bit word of Program memory.

• Simultaneous glueless interface to SRAM and DRAM.

1.4 Peripheral Modules

• Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony, AC97, network and other programmable protocols.

• Serial Audio Interface I(ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I Sony, AC97, network and other programmable protocols The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT support HCKR and HCKT (high frequency clocks)

• Serial Host Interface (SHI): SPI and I support for 8, 16 and 24-bit words.

• Byte-wide parallel Host Interface (HDI08) with DMA support.

• Triple Timer module (TEC).

• Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF, IEC958, CP-340 and AES/EBU digital audio formats.

• Pins of unused peripherals (except SHI) may be programmed as GPIO lines.

C protocols, multi master capability, 10-word receive FIFO,

1.5 Packaging

• 144-pin plastic LQFP package.

MOTOROLA DSP56366 Advance Information iii

For More Information On This Product,

Go to: www.freescale.com

Overview Documentation

Freescale Semiconductor, Inc.

2 Documentation

Table 1 lists the documents that provide a complete description of the DSP56366 and are required to

design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information).

Table 1 DSP56366 Documentation

Document Name Description Order Number

DSP56300 Family Manual Detailed description of the 56000-family

architecture and the 24-bit core processor and instruction set

DSP56366 User’s Manual Detailed description of memory, peripher-

nc...

DSP56366 Technical Data Sheet Electrical and timing specifications; pin

DSP56366 Product Brief Brief description of the chip DSP56366P/D

als, and interfaces

and package descriptions

cale Semiconductor,

DSP56300FM/AD

DSP56366UM/D

DSP56366/D

Frees

iv DSP56366 Advance Information MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION 1

SIGNAL/CONNECTION DESCRIPTIONS

1.1 SIGNAL GROUPI NG S

The input and output signals of the DSP56366 are organized into functional groups, which are listed in

Table 1-1 and illustrated in Figure 1-1.

The DSP56366 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs.

Table 1-1 DSP56366 Functional Signal Groupings

nc...

cale Semiconductor,

Frees

Functional Group

Power (VCC) Ground (GND) Clock and PLL Address bus

Data bus 24 Figure 1-6 Bus control 10 Figure 1-7 Interrupt and mode control 5 Figure 1-8 HDI08

SHI 5 Figure 1-10 ESAI

ESAI_1

Digital audio transmitter (DAX)

Port A

Port B

Port C

Port E

Port D

Number of

Signals

20 18

18 Figure 1-5

16 Table 1-9

12 Table 1-11

6 Table 1-12

2 Table 1-13

Detailed

Description

Figure 1-2 Figure 1-3 Figure 1-4

Timer 1 Table 1-14 JTAG/OnCE Port 4 Figure 1-15

Notes: 1. Port A is the external memory interface po rt, inc luding the ex ternal addres s bus, d ata bu s, a nd co ntrol

signals.

2. Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals.

3. Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.

4. Port D signals are the GPIO port signals which are multiplexed with the DAX signals.

5. Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.

MOTOROLA DSP56366 Advance Information 1-1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions Signal Groupings

nc...

cale Semiconductor,

Frees

PORT A ADDRESS BUS

A0-A17

VCCA (3)

GNDA (4)

PORT A DATA BUS

D0-D23

VCCD (4)

GNDD (4)

PORT A BUS CONTROL

AA0-AA2/RAS0-RAS2

CAS

RD WR TA BR BG

BB VCCC (2) GNDC (2)

INTERRUPT AND MODE CONTROL

MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD

RESET

PLL AND CLOCK

EXTAL

PINIT/NMI

PCAP VCCP GNDP

QUIET POWER

VCCQH (3)

VCCQL (4)

GNDQ (4)

SPDIF TRANSMITTER (DAX)

ADO [PD1] ACI [PD0]

TIMER 0

TIO0 [TIO0]

DSP56366

Port D

Port B

Port C

Port E

OnCE ON-CHIP EMULATION/

TDI

TCK TDO

TMS

JTAG PORT

PARALLEL HOST PORT (HDI08)

HAD(7:0) [PB0-PB7] HAS/HA0 [PB8] HA8/HA1 [PB9] HA9/HA2 [PB10] HRW/HRD [PB11] HDS/HWR [PB12] HCS/HA10 [PB13] HOREQ/HTRQ [PB14] HACK/HRRQ [PB15]

VCCH GNDH

SERIAL AUDIO INTERFACE (ESAI)

SCKT[PC3] FST [PC4] HCKT [PC5] SCKR [PC0] FSR [PC1] HCKR [PC2] SDO0[PC11] / SDO0_1[PE11] SDO1[PC10] / SDO1_1[PE10] SDO2/SDI3[PC9] / SDO2_1/SDI3_1[PE9] SDO3/SDI2[PC8] / SDO3_1/SDI2_1[PE8] SDO4/SD I1 [PC7] SDO5/SD I0 [PC6]

SERIAL AUDIO INTERFACE(ESAI_1)

SCKT_1[PE3]

T_1[PE4]

FS SCKR_1[PE0] FSR_1[PE1] SDO4_1/SDI1_1[PE7] SDO5_1/SDI0_1[PE6] VCCS (2) GNDS (2)

SERIAL HOST INTERFACE (SHI)

MOSI/HA0

/HA2

SS MISO/SDA

SCK/SCL

HREQ

Figure 1-1 Signals Identified by Functional Group

1-2 DSP56366 Advance Information MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

1.2 POWER

Freescale Semiconductor, Inc.

Signal/Connection Descriptions

Table 1-2 Power Inputs

Power

nc...

cale Semiconductor,

Frees

Power

Name

CCP

(4) Quiet Core (Low) Power—V

CCQL

(3) Quiet External (High) Power—V

CCQH

(3) Address Bus Power—V

CCA

(4) Data Bus Power—V

CCD

(2) Bus Control Power—V

CCC

CCH

(2) SHI, ESAI, ESAI_1, DAX and Timer Power —V

CCS

PLL Power—V and the input should be provided with an extremely low impedance path to the V power rail. There is one V

This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four V

must be tied externally to all other chip power inputs. The user must provide adequate decoupling capacitors. There are three V

drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are three V

This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four V

input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two V

Host Power—V tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There is one V

ESAI, ESAI_1, DAX and Timer. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two V

CCS

is VCC dedicated for PLL use. The voltage should be well-regulated

CCP

input.

CCP

CCQL

is an isolated power for sections of the address bus I/O

CCA

is an isolated power for sections of the data bus I/O drivers.

CCD

is an isolated power for the bus control I/O drivers. This

CCC

is an isolated power for the HDI08 I/O drivers. This input must be

CCH

inputs.

Description

is an isolated power for the internal processing logic.

inputs.

CCQL

is a quiet power source for I/O lines. This input

CCQH

inputs.

CCQH

inputs.

CCA

inputs.

CCD

inputs.

CCC

input.

CCH

is an isolated power for the SHI,

CCS

MOTOROLA DSP56366 Advance Information 1-3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions Ground

1.3 GROUND

Table 1-3 Grounds

nc...

cale Semiconductor,

Frees

Ground

Name

GND

(4) Quiet Ground—GNDQ is an isolated ground for the internal processing logic. This con-

GND

(4) Addr ess Bus Ground—GNDA is an isolated ground for sections of the address bus

GND

(4) Data Bus Ground—GNDD is an isolated ground for sections of the data bus I/O driv-

(2) Bus Control Ground—GNDC is an isolated ground for the bus control I/O drivers. This

GND

(2) SHI, ESAI, ESAI_1, DAX and Timer Ground—GNDS is an isolated ground for the SHI,

PLL Ground—GNDP is a ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. V to GND There is one GND

nection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GND

I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GND

ers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GND nections.

connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GND

Host Ground—GNDh is an isolated ground for the HD08 I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GND

ESAI, ESAI_1, DAX and Timer. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GND

by a 0.47 µF capacitor located as close as possible to the chip package.

connections.

connection.

connections.

Description

should be bypassed

CCP

connections.

connection.

con-

1-4 DSP56366 Advance Information MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

1.4 CLOCK AND PLL

Table 1-4 Clock and PLL Signals

Signal/Connection Descriptions

Clock and PLL

Signal

Name

EXTAL Input Input External Clock Input—An external clock source must be connected

PCAP Input Input PLL Capacitor—PCAP is an input connecting an off-chip capacitor

nc...

PINIT/N

Type

Input Input PLL Initial/Nonmaskable Interrupt—During assertion of RESET,

cale Semiconductor,

State

during

Reset

Signal Description

to EXTAL in order to supply the clock to the internal clock generator and PLL.

This input cannot tolerate 5 V.

to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to V

If the PLL is not used, PCAP may be tied to V ing.

the value of PINIT/NMI PLL control register, determining whether the PLL is enabled or disabled. After RESET cessing, the PINIT/NMI negative-edge-trigge red nonma sk ab le int erru pt (NM I) reque st inte r nally synchronized to internal system clock.

This input cannot tolerate 5 V.

CCP

, GND, or left float-

is written into the PLL Enable (PEN) bit of the

de assertion and during normal instruction pro-

Schmitt-trigger input is a

Frees

MOTOROLA DSP56366 Advance Information 1-5

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions External Memory Expansion Port (Port A)

1.5 EXTERNAL MEMORY EXPANSION PORT (PORT A)

When the DSP56366 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0

1.5.1 External Add ress Bu s

Table 1-5 External Address Bus Signals

–AA2/RAS2, RD, WR, BB, CAS.

Signal

Name

nc...

A0–A17 Output Tri-stated Address Bus—When the DSP is the bus master, A0–A17 are

Type

State

during

Reset

Signal Description

active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A0–A17 do not change state when external memory spaces are not being accessed.

1.5.2 External Dat a Bus

Table 1-6 External Data Bus Signals

Signal

Name

D0–D23 Input/Output Tri-stated Data Bus—When the DSP is the bus master, D0–D23 are

Type

cale Semiconductor,

State

during

Reset

Signal Description

active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0–D23 are tri-stated.

Frees

1-6 DSP56366 Advance Information MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

1.5.3 External Bus C ontrol

Table 1-7 External Bus Control Signals

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

Signal

Name

AA0–AA2/

RAS0

–RAS2

nc...

CAS

Type

Output Tri-stated Address Attribute or Row Address Strobe—When

Output Tri-stated Column Address Strobe— When the DSP is the bus

Output Tri-stated Read Enable—When the DSP is the bus master, RD

Output Tri-stated Write Enable—When the DSP is the bus master, WR

cale Semiconductor,

State

during

Reset

Signal Description

defined as AA, these signals can be used as chip selects or additional address lines. When defined as RAS

, these signals can be used as RAS for DRAM interface. These signals are tri-statable outputs with programmable polarity.

master, CAS strobe the column address. Otherwise, if the bus mastership enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated.

is an active-low output that is asserted to read external memory on the data bus (D0-D23). Otherwise, RD tri-stated.

is an active-low output that is asserted to write external memory on the data bus (D0-D23). Otherwise, WR is tri-stated.

is an active-l ow ou tp ut us ed by DRAM t o

Frees

MOTOROLA DSP56366 Advance Information 1-7

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions External Memory Expansion Port (Port A)

Table 1-7 External Bus Control Signals (continued)

Signal

Name

TA Input Ignored

nc...

Type

cale Semiconductor,

State

during

Reset

Input

Signal Description

Transfer Acknowledge—If the DSP is the bus master

and there is no external bus activity, or the DSP is not the bus master, the TA is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be added to the wait states inserted by the BCR by keeping TA deasserted. In typical operation, TA the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA system clock. The number of wait states is determined by the TA whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles.

In order to use the TA programmed to at least one wait state. A zero wait state access cannot be extended by TA otherwise improper operation may result. TA ate synchronously or asynchronously, depending on the setting of the TAS bit in the operating mode register (OMR).

functionality may not be used while performing DRAM type accesses, otherwise improper operation may result.

is asserted synchronous to the internal

input or by the bus control register (BCR),

input is ignored. The TA input

is deasserted at

functionality, the BCR must be

deassertion,

can oper-

Frees

1-8 DSP56366 Advance Information MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table 1-7 External Bus Control Signals (continued)

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

Signal

Name

BR Output Output

nc...

Type

Input Ignored

cale Semiconductor,

State

during

Reset

(deasserted)

Input

Signal Description

Bus Request—BR is an active-low output, never

tri-stated. BR mastership. BR needs the bus. BR independent of whether the DSP56366 is a bus master or a bus sl av e. B us “p ar ki ng ” al l ow s BR serted even though the DSP56366 is the bus master. (See the description of bus “parking” in the BB description.) The bus request hol d (BR H) bit in the BCR allows BR even though the DSP does not need the bus. BR typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. BR requests for the external bus, never for the internal bus. During hardware reset, BR arbitration is reset to the bus slave state.

Bus Grant—BG is an active-low inpu t. BG is as serte d by an external bus arbitration circuit when the DSP56366 becomes the next bus master. When BG asserted, the DSP56366 must wait until BB serted before taking bus mastership. When BG deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution.

For proper BG tration enable bit (ABE) in the OMR register must be set.

is asserted when the DSP requests bus

is deasserted when the DSP no longer

may be asserted or deasserted

to be deas-

signal

to be asserted under software control

is only affected by DSP

is deasserted and the

is deas-

operation, the asynchronous bus arbi-

Frees

MOTOROLA DSP56366 Advance Information 1-9

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions Interrupt and Mode Control

Table 1-7 External Bus Control Signals (continued)

Signal

Name

nc...

Type

Input/Output Input Bus Busy—BB is a bidirectional active-low input/out-

1.6 INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After RESET

cale Semiconductor,

Signal

Name

is deasserted, these inputs are hardware interrupt request lines.

State

Type

during

Reset

State

during

Reset

put. BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master may keep BB ity regardless of whether BR serted. This is called “bus parking” and allows the current bus master to reuse the bus without rearbitration until another device requires the bus. The deassertion of BB (i.e., BB by an external pull-up resistor).

For proper BB tration enable bit (ABE) in the OMR register must be set.

Table 1-8 Interrupt and Mode Control

indicates that the bus is active. Only after BB

is driven high and then released and held high

requires an external pull-up resistor.

Signal Description

asserted after ceasing bus activ-

is done by an “active pull-up” method

operation, the asynchronous bus arbi-

Signal Description

is asserted or deas-

Frees

MODA/IRQA Input Input Mode Select A/External Interrupt Request A—MODA/IRQA is

an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET the stop standby state and the MODA/IRQA the processor will exit the stop state.

This input is 5 V tolerant.

1-10 DSP56366 Advance Information MOTOROLA

selects the initial chip operating mode

signal is deasserted. If the processor is in

pin is pulled to GND,

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table 1-8 Interrupt and Mode Control (continued)

Signal/Connection Descriptions

Interrupt and Mode Control

nc...

cale Semiconductor,

Frees

Signal

Name

MODB/IRQB Input Input Mode Select B/External Interrupt Request B—MODB/IRQB is

MODC/IRQC

MODD/IRQD

RESET

Type

Input Input Mode Select C/External Interrupt Request C—MODC/IRQC is

Input Input Mode Select D/External Interrupt Request D—MODD/IRQD is

Input Input Reset—RESET is an active-low, Schmitt-trigger input. When

State

during

Reset

Signal Description

an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET

This input is 5 V tolerant.

an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET

This input is 5 V tolerant.

an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET

This input is 5 V tolerant.

asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When the RESET ating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET up. A stable EXTAL signal must be supplied while RESET asserted.

signal is deasserted.

selects the initial chip operating mode

signal is deasserted, the initial chip oper-

signal must be asserted during power

is being

This input is 5 V tolerant.

MOTOROLA DSP56366 Advance Information 1-11

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)

1.7 PARALLEL HOST INTERFACE (HDI08)

The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The HDI08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware.

Table 1-9 Host Interface

nc...

cale Semiconductor,

Frees

Signal Name Type

H0–H7 Input/

output

HAD0–HAD7 Input/

output

PB0–PB7 Input, outp ut,

disconnected

HA0 Input GPIO

HAS/

HAS Input GPIO

State during

Reset

GPIO

disconnected

GPIO

disconnected

GPIO

disconnected

Signal Description

Host Data—When HDI08 is programmed t o interface a

nonmultiplexed host bus and the HI funct ion is sel ected, these signals are lines 0–7 of the bidirectional, tri-state data bus.

Host Address/Data—When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, these signals are lines 0–7 of the address/data bidirectional, multiplexed, tri-state bus.

Port B 0–7—When the HDI08 is configured as GPIO, these signals are individually programmable as input, output, or internally disconnected.

The default state after reset for these signals is GPIO disconnected.

These inputs are 5 V tolerant. Host Address Input 0—When the HDI08 is programmed

to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 0 of the host addres s inp ut bus.

Host Address Strobe—When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is the host address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is programmable, but is configured active-low (HAS ing reset.

) follow-

PB8 Input, output,

disconnected

1-12 DSP56366 Advance Information MOTOROLA

GPIO

disconnected

Port B 8—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table 1-9 Host Interface (continued)

Signal/Connection Descriptions

PARALLEL HOST INTERFACE (HDI08)

nc...

cale Semiconductor,

Frees

Signal Name Type

HA1 Input GPIO

HA8 Input GPIO

PB9 Input, output,

disconnected

HA2 Input GPIO

HA9 Input GPIO

PB10 Input, Output,

Disconnected

State during

Reset

disconnected

GPIO

disconnected

GPIO

disconnected

Signal Description

Host Address Input 1—When the HDI08 is programmed

to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 1 of the host address (HA1) input bus.

Host Address 8—When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 8 of the host address (HA8) input bus.

Port B 9—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant. Host Address Input 2—When the HDI08 is programmed

to interface a non-multiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus.

Host Address 9—When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 9 of the host address (HA9) input bus.

Port B 10—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant.

MOTOROLA DSP56366 Advance Information 1-13

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)

Table 1-9 Host Interface (continued)

nc...

cale Semiconductor,

Frees

Signal Name Type

HRW Input GPIO

HRD

PB11 Input, Output,

HDS

HWR

PB12 In put, outp ut,

Input GPIO

Disconnected

Input GPIO

disconnected

State during

Reset

disconnected

GPIO

disconnected

GPIO

disconnected

Signal Description

Host Read/Write—When HDI08 is programmed to inter-

face a single-data-strobe host bus and the HI function is selected, this signal is the Host Read/Write

Host Read Data—When HDI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the host read data strobe (HRD) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HRD after reset.

Port B 11—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant. Host Data Strobe—When HDI08 is programmed to inter-

face a single-data-strobe host bus and the HI function is selected, this signal is the host data strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HDS lowing reset.

Host Write Data—When HDI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the host write data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HWR lowing reset.

Port B 12—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

(HRW) input.

)

) fol-

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant.

1-14 DSP56366 Advance Information MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table 1-9 Host Interface (continued)

Signal/Connection Descriptions

PARALLEL HOST INTERFACE (HDI08)

nc...

cale Semiconductor,

Frees

Signal Name Type

HCS Input GPIO

HA10 Input GPIO

PB13 Input, output,

disconnected

HOREQ

HTRQ

PB14 Input, output,

Output GPIO

disconnected

State during

Reset

disconnected

GPIO

disconnected

GPIO

disconnected

Signal Description

Host Chip Select—When HDI08 is programmed to inter-

face a nonmultiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable, but is configured active-low (HCS

Host Address 10—When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 10 of the host address (HA10) input bus.

Port B 13—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant. Host Request—When HDI08 is programmed to interface

a single host request host bus and the HI function is selected, this signal is the host request (HOREQ) output. The polarity of the host request is programmable, but is configured as active-low (HOREQ host request may be programmed as a driven or open-drain output.

Transmit Host Request—When HDI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the transmit host request (HTRQ) output. The polarity of the host request is programmable, but is configured as active-low (HTRQ following reset. The host request may be programmed as a driven or open-drain output.

Port B 14—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

) after reset.

) following reset. The

)

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant.

MOTOROLA DSP56366 Advance Information 1-15

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)

Table 1-9 Host Interface (continued)

Signal Name Type

HACK/

HACK

HRRQ

nc...

PB15 In put, outp ut,

Input GPIO

Output GPIO

disconnected

cale Semiconductor,

State during

Reset

disconnected

GPIO

disconnected

Signal Description

Host Acknowledge—When HDI08 is programmed to

interface a single host request host bus and the HI function is selected, this signal is the host acknowledge (HACK) Schmitt-trigger input. The polarity of the host acknowledge is programmable, but is configured as active-low (HACK

Receive Host Request—When HDI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the receive host request (HRRQ) output. The polarity of the host request is programmable, but is configured as active-low (HRRQ reset. The host request may be programmed as a driven or open-drain output.

Port B 15—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 5 V tolerant.

) after reset .

) after

Frees

1-16 DSP56366 Advance Information MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions

Serial Host Interface

1.8 SERIAL HOST INTERFACE

The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.

Table 1-10 Serial Host Interface Signals

nc...

cale Semiconductor,

Frees

Signal

Name

SCK Input or

SCL Input or

MISO Input or

SDA Input or

Signal

Type

output

open-drain

output

State during

Reset

Tri-stated SPI Serial Clock—The SCK signal is an output when the SPI is config-

ured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol.

Tri-stated I

Tri-stated

Tri-stated I2C Data and Acknowledge—In I2C mode, SDA is a Schmitt-trigger

C Serial Clock—SCL carries the clock for I2C bus transactions in the

C mode. SCL is a Schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. SCL should be connected to V

This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state.

This input is 5 V tolerant.

SPI Master-In-Slave-Out

MISO is the master data input line. The MISO signal is used in conjunction with the MOS I sign a l for tran sm itt ing an d rec eivin g serial da ta. T h is signal is a Schmitt-trig ger inp u t whe n co nf igure d fo r the SP I M a ste r mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS pull-up resistor is not required for SPI operation.

input when receiving and an open-drain output when transmitting. SDA should be connected to V data for I high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique situation, and is defined as the start event. A low-to-high transition of SDA while SCL is high is a unique situation defined as the stop event.

This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state.

C transactions. The data in SDA must be stable during the

through a pull-up resistor.

Signal Description

—When the SPI is configured as a master,

is deasserted. An external

through a pull-up resistor. SDA carries the

)

This input is 5 V tolerant.

MOTOROLA DSP56366 Advance Information 1-17

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions Serial Host Interface

Table 1-10 Serial Host Interface Signals (continued)

nc...

cale Semiconductor,

Frees

Signal

Name

MOSI Input or

HA0 Input I2C Slave Address 0—This signal uses a Schmitt-trigger input when

HA2 Input I

HREQ

Signal

Type

output

Input Tri-stated SPI Slave Select—This signal is an active low Schmitt-trigger input

Input or

Output

State during

Reset

Tri-stated

Tri-stated Host Request—This signal is an active low Schmitt-trigger input when

SPI Master-Out-Slave-In

MOSI is the m a ster d a ta o utpu t line . The MOSI signal is u se d in co nju n ction with the MISO signal for transmitting and receiving serial data. MOSI is the slave d ata input line when the SPI is configure d as a slave . This signal is a Schmitt-trigger input when configured for the SPI Slave mode.

configured for the I HA0 signal is used to form the slave device address. HA0 is ignored when configured for the I

This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state.

This input is 5 V tolerant.

when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI master mode, this signal should be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged. If SS clocks and keeps the MISO output signal in the high-impedance state.

C Slave Address 2—This signal uses a Schmitt-trigger input when configured for the I the HA2 signal is used to form the slave device address. HA2 is ignored in the I

This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state.

This input is 5 V tolerant.

configured for the master mode but an active low output when configured for the slave mode.

When configured for the slave mode, HREQ the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the master mode, HREQ device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ

This signal is tri-stated during hardware, software, personal reset, or when the HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in this state.

This input is 5 V tolerant.

C master mode.

Signal Description

—When the SPI is configured as a master,

C mode. When configured for I2C slave mode, the

C master mode.

is deasserted, the SHI ignores SCK

C mode. When configured for the I2C Slave mode,

is asserted to indicate that

is an input. When asserted by the external slave

to proceed to the next transfer.

1-18 DSP56366 Advance Information MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions

Enhanced Serial Audio Interface

1.9 ENHANCED SERIAL AUDIO INTERFACE

Table 1-11 Enhanced Serial Audio Interface Signals

Signal

Name

HCKR Input or output GPIO

nc...

PC2 Input, output,

HCKT Input or output GPIO

PC5 Input, output,

Signal Type

disconnected

cale Semiconductor,

State during

Reset

disconnected

GPIO

disconnected

GPIO

disconnected

Signal Description

High Frequency Clock for Receiver

input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock.

Port C 2

individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

High Frequency Clock for Transmitter—When programmed as an input, this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock.

Port C 5—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This input is 5 V tolerant.

—When the E S AI is co n figure d as G P IO , this sign al is

—When programmed as an

Frees

MOTOROLA DSP56366 Advance Information 1-19

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions Enhanced Serial Audio Interface

Table 1-11 Enhanced Serial Audio Interface Signals (continued)

nc...

cale Semiconductor,

Frees

Signal

Name

FSR Input or output GPIO

PC1 Input, output,

FST Input or output GPIO

PC4 Input, output,

Signal Type

disconnected

State during

Reset

disconnected

GPIO

disconnected

Signal Description

Frame Sync for Receiver—This is the receiver frame sync

input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1).

When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode.

Port C 1—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This input is 5 V tolerant.

Frame Sync for Transmitter—This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR).

Port C 4—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This input is 5 V tolerant.

1-20 DSP56366 Advance Information MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table 1-11 Enhanced Serial Audio Interface Signals (continued)

Signal/Connection Descriptions

Enhanced Serial Audio Interface

Signal

Name

SCKR Input or output GPIO

nc...

PC0 Input, output,

SCKT Input or output GPIO

PC3 Input, output,

cale Semiconductor,

Signal Type

disconnected

State during

Reset

disconnected

GPIO

disconnected

GPIO

disconnected

Signal Description

Receiver Serial Clock—SCKR provides the receiver serial

bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1).

When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode.

Port C 0—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This input is 5 V tolerant.

Transmitter Serial Clock—This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode.

Port C 3—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This input is 5 V tolerant.

Frees

SDO5 Output GPIO

disconnected

SDI0 Input GPIO

disconnected

PC6 Input, output,

disconnected

MOTOROLA DSP56366 Advance Information 1-21

GPIO

disconnected

Serial Data Output 5—When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register.

Serial Data In put 0

used to receive serial data into the RX0 serial receive shift register. Port C 6—When the ESAI is configured as GPIO, this signal

is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This input is 5 V tolerant.

—When programmed as a receiver, SDI0 is

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions Enhanced Serial Audio Interface

Table 1-11 Enhanced Serial Audio Interface Signals (continued)

nc...

cale Semiconductor,

Frees

Signal

Name

SDO4 Output GPIO

SDI1 Input GPIO

PC7 Input, output,

SDO3/S

DO3_1

SDI2/

SDI2_1

PC8/PE8 Input, output,

Signal Type

disconnected

Output GPIO

Input GPIO

disconnected

State during

Reset

disconnected

GPIO

disconnected

GPIO

disconnected

Signal Description

Serial Data Output 4—When programmed as a transmitter,

SDO4 is used to transmit data from the TX4 serial transmit shift register.

Serial Data Input 1—When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register.

Port C 7—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This input is 5 V tolerant.

Serial Data Output 3—When programmed as a transmitter, SDO3 is used to transmit data from the TX3 serial transmit shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 3.

Serial Data Input 2—When programmed as a receiver, SDI2 is used to receive serial data into the RX2 serial receive shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input 2.

Port C 8—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

When enabled for ESAI_1 GPIO, this is the Port E 8 signal. The default state after reset is GPIO disconnected. This input is 5 V tolerant.

1-22 DSP56366 Advance Information MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table 1-11 Enhanced Serial Audio Interface Signals (continued)

Signal/Connection Descriptions

Enhanced Serial Audio Interface

Signal

Name

SDO2/

SDO2_1

SDI3/SDI

3_1

nc...

PC9/PE9 Input, output,

SDO1/

SDO1_1

PC10/

PE10

Signal Type

Output GPIO

Input GPIO

disconnected

Output GPIO

Input, output,

disconnected

cale Semiconductor,

State during

Reset

disconnected

GPIO

disconnected

GPIO

disconnected

Signal Description

Serial Data Output 2—When programmed as a transmitter,

SDO2 is used to transmit data from the TX2 serial transmit shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 2.

Serial Data Input 3—When programmed as a receiver, SDI3 is used to receive serial data into the RX3 serial receive shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input 3.

Port C 9—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

When enabled for ESAI_1 GPIO, this is the Port E 9 signal. The default state after reset is GPIO disconnected. This input is 5 V tolerant.

Serial Data Output 1—SDO1 is used to transmit data from the TX1 serial transmit shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 1.

Port C 10—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

When enabled for ESAI_1 GPIO, this is the Port E 10 signal. The default state after reset is GPIO disconnected. This input is 5 V tolerant.

Frees

SDO0/S

DO0_1

PC11/

PE11

MOTOROLA DSP56366 Advance Information 1-23

Output GPIO

disconnected

Input, output,

disconnected

GPIO

Serial Data Output 0—SDO0 is used to transmit data from the TX0 serial transmit shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 0.

Port C 11—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

When enabled for ESAI_1 GPIO, this is the Port E 11 signal. The default state after reset is GPIO disconnected. This input is 5 V tolerant.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions Enhanced Serial Audio Interface_1

ENHANCED SERIAL AUDIO INTERFACE_1

Table 1-12 Enhanced Serial Audio Interface_1 Signals

nc...

cale Semiconductor,

Frees

Signal

Name

FSR_1 Input or output GPIO

PE1 Input, output,

FST_1 Input or output GPIO

Signal Type

disconnected

State during

Reset

disconnected

GPIO

disconnected

Signal Description

Frame Sync for Receiver_1—This is the receiver frame sync

Port E 1—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This input cannot tolerate 5 V.

Frame Sync for Transmitter_1—This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR).

PE4 Input, output,

disconnected

1-24 DSP56366 Advance Information MOTOROLA

GPIO

disconnected

Port E 4—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This input cannot tolerate 5 V.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table 1-12 Enhanced Serial Audio Interface_1 Signals

Signal/Connection Descriptions

Enhanced Serial Audio Interface_1

nc...

cale Semiconductor,

Frees

Signal

Name

SCKR_1 Input or output GPIO

PE0 Input, output,

SCKT_1 Input or output GPIO

PE3 Input, output,

SDO5_1 Output GPIO

Signal Type

disconnected

State during

Reset

disconnected

GPIO

disconnected

GPIO

disconnected

Signal Description

Receiver Serial Clock_1—SCKR provides the receiver serial

bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1).

Port E 0—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This input cannot tolerate 5 V.

Transmitter Serial Clock_1—This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode.

Port E 3—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This input cannot tolerate 5 V.

Serial Data Output 5_1

SDO5 is used to transmit data from the TX5 serial transmit shift register.

—When programmed as a transmitter,

SDI0_1 Input GPIO

disconnected

PE6 Input, output,

disconnected

MOTOROLA DSP56366 Advance Information 1-25

GPIO

disconnected

Serial Data Inpu t 0 _1

used to receive serial data into the RX0 serial receive shift register.

Port E 6

vidually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 5 V.

—When the ESAI is configured as GPIO, this signal is indi-

—When programmed as a receiver, SDI0 is

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Signal/Connection Descriptions spdif tRANSMITTER Digital Audio Interface

Table 1-12 Enhanced Serial Audio Interface_1 Signals

nc...

cale Semiconductor,

Frees

Signal

Name

SDO4_1 Output GPIO

SDI1_1 Input GPIO

PE7 Input, output,

Signal Type

disconnected

State during

Reset

disconnected

GPIO

disconnected

Signal Description

Serial Data Output 4_1—When programmed as a transmitter,

SDO4 is used to transmit data from the TX4 serial transmit shift register.

Serial Data Input 1_1—When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register.

Port E 7—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This input is 5 V tolerant.

1.10 SPDIF TRANSMITTER DIGITAL AUDIO INTERFACE

Table 1-13 Digital Audio Interface (DAX) Signals

Signal

Name

ACI Input GPIO

PD0 Input,

Type

output, or

disconnected

State During

Reset

Disconnected

GPIO

Disconnected

Signal Description

Audio Clock Input—This is the DAX clock input. When pro-

grammed to use an external clock, this input supplies the DAX clock. The external clock frequency must be 256, 384, or 512 times the audio sampling frequency (256 × Fs, 384 × Fs or 512 × Fs, respectively).

Port D 0—When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This input is 5 V tolerant.

ADO Output GPIO

Disconnected

PD1 Input,

output, or

disconnected

1-26 DSP56366 Advance Information MOTOROLA

GPIO

Disconnected

Digital Audio Data Output—This signal is an audio and non-audio output in the form of AES/EBU, CP340 and IEC958 data in a biphase mark format.

Port D 1

vidually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.

—When the DAX is configured as GPIO, this signal is indi-

For More Information On This Product,

Go to: www.freescale.com

+ 122 hidden pages