Motorola 89FC5815 Users manual

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User / Operational Manual

Operational or User’s Manual

The manual should include instruction, installation, operator, or technical manuals with required ‘information to the
users’. This manual should include a statement that cautions the user that changes or modifications not expressly
approved by the party responsible for compliance could void the user’s authority to operate the equipment. The
manual shall include RF Hazard warning statements, if applicable.

The instruction and service manual for this base radio are not published at this time. However, draft copy of some
of the manual information has been assembled and has been included as part of this filing package.

Upon request, published and/or printed manuals will be sent to the commission and/or telecommunication
certification body (TCB) as soon as they become available. All of the descriptions, block diagram s, and
schematics that are included in this filing package are current as of the package submittal date.

EXHIBIT DESCRIPTION

D1-1 Manual Front Matter (Draft)
D1-2 Specifications (Draft)
D1-3 Field Replaceable Units and Orderable Parts (Draft)
D1-4 Tune-Up Procedure
D1-5 Functional Description / Operation of Modules (Draft)

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User / Operational Manual

Manual Front Matter (Draft)

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User / Operational Manual

Manual Front Matter (Draft, Continued)

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User / Operational Manual

Manual Front Matter (Draft, Continued)

EXHIBIT D1-1

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User / Operational Manual

Manual Front Matter (Draft, Continued)

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User / Operational Manual

Manual Front Matter (Draft, Continued)

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User / Operational Manual

Manual Front Matter (Draft, Continued)

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User / Operational Manual

Specifications (Draft)

Gen3 Base Radio General Specifications

Gen3 Base Radio Receive Specifications

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User / Operational Manual

Specifications (Draft) (Continued

Gen3 Base Radio Receive Specifications (Continued)

Gen3 Base Radio Transmit Specifications

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User / Operational Manual

Field Replaceable Units and Orderable Parts (Draft)

Field replaceable units, or FRUs, include special packaging to allow shipment to cu stomers. Parts and
FRUs available for customer order are listed in this section. All parts and FRUs are sourced through the
Radio Products and Service Division (RPSD).

Structure of Part / FRU # Description
T7423A iDEN Gen3 800 / 900 MHz Base Radio

CLF1847A Power Amplifier Tanapa

CLF6542A Combiner board (New kit number for 800/900)
CLF6506E PA Driver module
CLF6530B PA Final
CLF6531C PA Low Pass Filter
CLN8053E PA DC Board
CLN8117C NULL Modulator Board
CLF6547A PA Housing Kit

0174000A75 PA Mechanics specific

0173000A19 PA Heatsink and Cover
PCUF1003B Transceiver, Single Carrier 800 / 900 MHz
MCPN1085A BR DC/DC Power Supply Tanapa
0180706H71 Chassis and Backplane
CLN8251B BR Card Cage Kit

0173000A67 RF cable, retainer clip, and RJ45 plugs
CLN8332A Blank Panel 2U rack filler w/ Hardware
CLN8333A FCC Label

CLN1834A iDEN Gen3 800 / 900 MHz Base Radio Super Tanapa

0180706H35 Fan Assembly
X899AF BR FRU packing option (must be added to order for BR to ship standalone)

CBN6250B BR Packing kit

DLN1399A iDEN Gen3 Transceiver FRU number

PCUF1003B Transceiver, 6 Channel 800 / 900 MHz
CBN6239A PA / Transceiver Packing kit

DLN1401A Power Amplifier FRU number

CLF1847A Power Amplifier Tanapa
CBN6239A PA / Transceiver Packing kit

DLN1400A iDEN Gen3 DC Power Supply FRU number

MCPN1085A BR DC/DC Power Supply Tanapa
CBN6240A Power Supply Packing kit

DLN6657A Fan Assembly FRU number

0180706H35 Fan Assembl y Tanapa
CBN6244A Fan Packing kit

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User / Operational Manual

Tune-Up Procedure

There is no field tune-up procedure. All adjustments are software controlled and are pre-set at the factory. Certain
station operating parameters can be changed via man-machine interface (MMI) commands, within predetermined
limits. Examples include transmit / receiver operating frequencies and transmitter power level.

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User / Operational Manual

Functional Description / Operation of Modules (Draft)

The following pages are excerpts from the manual and are intended to give an overview of the base radio and the
modules that comprise the base radio.

The Gen3 Base Radio is very similar to a previous product, the Quad+2 Base Radio. The main differences
between the two products are 1) the power supply is DC-only; and 2) the Gen3 BR is capable of a single Tran smit /
Receive RF channel, whereas the Quad+2 BR was capable of up to 6 contiguou s RF channels. What follows is
draft copy of the Quad+2 BR manual sections edited for use with Gen3. The content of the finalized Gen3 BR
manual will be similar to what is shown here.

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Base Radio Volume 2G

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Gen3 Base Radio Overview

Gen3 Base Radio

Theory of Operation

The Gen3 BR operates together with other site controllers and

equipment that are properly terminated. The following description assumes
such a configuration. Figure 1-11 shows an overall block diagram of the BR.

Power is applied to the DC Power inputs located on the Gen3 BR

backplane. The DC Power input is connected if -48 VDC or batteries are used
in the site.

Power is applied to the BR by setting the Power Supply power switch to the

ON position. Upon power-up, the Gen3 BR performs self-

diagnostic tests to ensure the integrity of the unit. These tests, which include
memory and Ethernet verification routines, primarily examine the EX /
CNTL.

After completing self-diagnostic tests, the Gen3 BR reports

alarm conditions on any of its modules to the site controller via Ethernet.
Alarm conditions may also be verified locally. Local verification involves

using the service computer and the STATUS port located on the front of the Gen3

BR.

The software resident in FLASH on the XCVR registers the BR with the site
controller via Ethernet. After BR registration on initial power-up, the BR
software downloads via Ethernet and executes from RAM. The download
includes operating parameters for the BR. These param­eters allow the BR to perform call processing functions.

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Base Radio Overview

After software downloads to the BR via Ethernet, FLASH memory stores the
software object. Upon future power-ups, the software object in FLASH loads
into RAM for execution.

The BR operates in a TDMA (Time Division Multiple Access) mode. This
mode, combined with voice compression techniques, increases channel
capacity by a ratio of as much as six to one. TDMA divides both the receive
and transmit signals of the BR into six individual time slots. Each receive slot
has a corresponding transmit slot. This pair of slots comprises a logical RF
channel.

The BR uses diversity reception for increased coverage area and improved
quality. The Receiver module
receive
branch diversity sites use three Receiver paths.

All Receiver paths within the Transceiver module are programmed to the
same receiver frequency. Signals from each receiver are diversity combined
and undergo error-correction. Then, via Ethernet, the site controller acquires
the signal, along with control information about signal destination.

r paths. Two-branch diversity sites use two Receiver paths, and three-

within the Gen3 BR contains three

5-May-08

Two separate FRUs comprise the transmit section of the
BR. These are the Exciter and Control (XCVR) portion of the Transceiver and
the Power Amplifier (PA). The Exciter processes commands from the CNTL,
assuring transmission in the proper modulation format. Then the low-level
signal enters the PA. The PA amplifies this signal to the desired output power
level. The PA is a continuously keyed linear amplifier. A power control
routine monitors the output power of the BR. The routine adjusts the power as
necessary to maintain the proper output level.

Gen3

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Overview

Overview 3

This chapter provides information on the Gen3 Base Radio Transceiver

(XCVR).

FRU Number to Kit
Number Cross
Reference

Base Radio Transceiver (XCVR) Field Replaceable Units (FRUs) are
available for the iDEN EBTS. The FRU contains the XCVR kit and required
packaging. Table 3-1provides a cross reference between XCVR FRU numbers
and kit numbers.

Table 3-1 FRU Number to Kit Number Cross Reference

FRU

Description

Gen3 Base Radio Transceiver DLN1399 PCUF1003

Number

Kit

Number

G

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Gen3 Base Radio Transceiver

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Gen3 Base Radio Transceiver 3

Gen3 Base Radio

Overview

The transceiver (XCVR) module provides the control, exciter and receiver
functions for the Base Radio.

The XCVR generates the station reference which typically needs to be locked
on to one of many possible external sources. The external source can be either
the site controller 20 MHz TDM clocks or the external reference operating at
5 or 10 MHz.

The XCVR SPI bus allows communication with its receiver and exciter
circuitry, as well as the power supply and power amplifier modules.

The XCVR circuit board contains two major sections:

n XCVR Control : Performs the control management, digital signal

processing, and transmit and receive data formatting for the Base Radio.

n XCVR RF : Contains DC power conversion/regulation and performs

receiver and exciter functions.

Figure 3-1shows a top view of the Transceiver.

Figure 3-1 800/900 MHz Gen3 Channel Transceiver (Front View)

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Gen3 Base Radio Transceiver

Transceiver Control
Section

Figure 3-2 800/900 MHz Gen3 Transceiver Information Flow

R
F
D
S

The main operating software for the base radio is loaded in the XCVR’s
control section. As the main manager for the base radio, the XCVR control
provides operational control over the other station modules. It handles three
types of information flow, in the following ways:

n Serves as a gateway between the network and RF functionality, by

distributing the RF payload to and from the network

n Supports operational and diagnostic functions with digital control data (for

example: site information, channel assignments, and identification numbers
for call processing)

n Ensures the flow of other network management configuration information

Figure 3-2 shows the information flow through the transceiver Control and
RF sections for HPD systems.

ControlRF

Host

P

DSP

PA

ADC

DAC

Ethernet via
Site Controller

Transceiver RF
Section

In addition to DC power conversion/regulation, the XCVR RF section
provides circuitry for the following receiver and exciter functions.

Exciter

The exciter on the XCVR RF section provides the transmitter functions for
the base radio. The exciter circuitry generates a low-level, modulated RF
signal that passes to the power amplifier. It supports various modulation types
as well as bandwidths up to 25 kHz, through software programming.

The exciter also provides a controlled output power level to the power
amplifier.

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Base Radio (XCVR)

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Gen3 Base Radio Transceiver

Receiver

The Gen3 receiver provides multiple receiver inputs for one to three

diversity branches with multiple channels of up to six channels within each
branch. The receiver is tuned to pass frequenies anywhere between 806 MHz
and 901 MHz. The receiver is best suited for:

n Low density RF environments

n Stations with external multicouplers

n Stations with requirements for multi-frequency operation beyond 14 MHz

Controls and
Indicators

Figure 3-3 800/900 MHz Gen3 Transceiver (with access door opened)

The transceiver external interfaces include 2 external ports, a switch and
LEDs. The ports and switch are described here. The LED states are listed in
the reference section of the documentation. Figure 3-3 shows the port, switch
and LED locations when the access door is opened. Figure 3-4 shows the Rear
View connectors.

Status LED

Alarm LED

5-May-08

Reset Switch

LEDs

Ports

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Gen3 Channel Base Radio Transceiver

Figure 3-4 800/900 MHz Gen3 Transceiver Backplane (Rear View)

RF and Ethernet Digital

Transceiver Ports - Front

Two ports are accessible via a dropdown door to the left of the fans. An
asynchronous port and a synchronous port.

Table 3-2 Transceiver Connections

XCVR Port /

Type

RJ-45 10/100BaseT port Ethernet port for future use.

Service port,
DB-9

Transceiver Ports - Rear

The transceiver interconnects to the backplane using a 120–pin HVDML
digital connector and 8–pack RF connector, as shown in Figure 3-4. These
connections handle multiple signals including power, power supply communi­cations, power amplifier communications, 10Base2 Ethernet, fan interface
and peripheral interface. The digital connection receives alarm data and the
site controllers’ TDM signals, which are used to pass reference and control
data to the station.

Transceiver Switch

There is one multifunction switch on the front of the transceiver module,
accessible via the dropdown door to the left of the fans.

Connects to this

Device/Port

Service PC, RS-232
port

Description

Serial service port for
configuration.

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Table 3-3 lists the Transceiver Front Switch Functions.

Table 3-3 XCVR Front Switch Functions

User Action Result

Press switch for less than 1 second Access Disable

Press switch for greater than 3
seconds

Transceiver LEDs

Table 3-4 and Table 3-5 lists the Transceiver LEDs. \

Table 3-4 Gen3 Base Radio Status and Alarm LED

Indications

Condition Status LED Alarm LED

No Power Off Off

Lamp Test Green Red

Transceiver Control Module Reset

5-May-08

Failure Off Red

Impaired Green Red (blinking)

Booting Up Green (blinking) Off

Online Green Off

Table 3-5 Gen3 Base Radio Transceiver LED Indications

Label LED State Description

Green

1

2

Green (Blinking) Channel 1 is not keyed

Off

Green

Green (Blinking) Channel 2 is not keyed

Off

Proper Base Radio operation with no alarm conditions and
channel 1 is keyed

Channel 1 is not in operation or the Base Radio is out of
service or power is removed

Proper Base Radio operation with no alarm conditions and
channel 2 is keyed

Channel 2 is not in operation or the Base Radio is out of
service or power is removed

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Gen3 Base Radio Transceiver

Table 3-5 Gen3 Base Radio Transceiver LED Indications (continued)

Label LED State Description

3

4

5

(See Note)

6

(See Note)

Green

Green (Blinking) Channel 3 is not keyed

Off

Green

Green (Blinking) Channel 4 is not keyed

Off

Green

Green (Blinking) Channel 5 is not keyed

Off

Green

Green (Blinking) Channel 6 is not keyed

Off

Proper Base Radio operation with no alarm conditions and
channel 3 is keyed

Channel 3 is not in operation or the Base Radio is out of
service or power is removed

Proper Base Radio operation with no alarm conditions and
channel 4 is keyed

Channel 4 is not in operation or the Base Radio is out of
service or power is removed

Proper Base Radio operation with no alarm conditions and
channel 5 is keyed

Channel 5 is not in operation or the Base Radio is out of
service or power is removed

Proper Base Radio operation with no alarm conditions and
channel 6 is keyed

Channel 6 is not in operation or the Base Radio is out of
service or power is removed

Note Five and six carrier operation is only supported in Test Application mode and requires licensing

agreement with Motorola for activation in Call Processing mode.

Transceiver Band States

Table 3-6 lists the Transceiver Band States

Table 3-6 Gen3 Base Radio Band State

Label LED State BR Band

Solid Red Install Band Failure

7

Solid Green 800 MHz

Solid Amber 900 MHz

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Table 3-3 lists the Transceiver Front Switch Functions.

Table 3-3 XCVR Front Switch Functions

User Action Result

Press switch for less than 1 second Access Disable

Press switch for greater than 3
seconds

Transceiver LEDs

Table 3-4 and Table 3-5 lists the Transceiver LEDs. \

Table 3-4 Gen3 Base Radio Status and Alarm LED

Indications

Condition Status LED Alarm LED

No Power Off Off

Lamp Test Green Red

Transceiver Control Module Reset

5-May-08

Failure Off Red

Impaired Green Red (blinking)

Booting Up Green (blinking) Off

Online Green Off

Table 3-5 Gen3 Base Radio Transceiver LED Indications

Label LED State Description

Green

1

2

Green (Blinking) Channel 1 is not keyed

Off

Green

Green (Blinking) Channel 2 is not keyed

Off

Proper Base Radio operation with no alarm conditions and
channel 1 is keyed

Channel 1 is not in operation or the Base Radio is out of
service or power is removed

Proper Base Radio operation with no alarm conditions and
channel 2 is keyed

Channel 2 is not in operation or the Base Radio is out of
service or power is removed

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Gen3 Base Radio Transceiver

Figure 3-5 Controller Section (with housing removed)

Host Microprocessor

The host microprocessor is the main controller for the BR. The processor
operates at a 266-MHz core clock speed. The processor controls Base Radio
operation according to station software in memory. Station software resides in
FLASH memory. For normal operation, the system transfers this software to
volatile S-DRAM memory.

Note At BR power-up and normal conditions, the Status and Alarm LEDs

transition through the Conditions stated in Table 3-4 as follows: Power
Off, Failure, Lamp Test, Booting Up and Online states as indicated in
Table 3-4. Any other sequence of Conditions indicates an impairment
or failure.

Serial Communication Buses

The microprocessor provides a general-purpose SMC serial management
controller bus.

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Table 3-3 lists the Transceiver Front Switch Functions.

Table 3-3 XCVR Front Switch Functions

User Action Result

Press switch for less than 1 second Access Disable

Press switch for greater than 3
seconds

Transceiver LEDs

Table 3-4 and Table 3-5 lists the Transceiver LEDs. \

Table 3-4 Gen3 Base Radio Status and Alarm LED

Indications

Condition Status LED Alarm LED

No Power Off Off

Lamp Test Green Red

Transceiver Control Module Reset

5-May-08

Failure Off Red

Impaired Green Red (blinking)

Booting Up Green (blinking) Off

Online Green Off

Table 3-5 Gen3 Base Radio Transceiver LED Indications

Label LED State Description

Green

1

2

Green (Blinking) Channel 1 is not keyed

Off

Green

Green (Blinking) Channel 2 is not keyed

Off

Proper Base Radio operation with no alarm conditions and
channel 1 is keyed

Channel 1 is not in operation or the Base Radio is out of
service or power is removed

Proper Base Radio operation with no alarm conditions and
channel 2 is keyed

Channel 2 is not in operation or the Base Radio is out of
service or power is removed

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Gen3 Base Radio Transceiver

Non-Volatile Memory

Base Radio software resides in a minimum of 32M x 16 bits of Compact
FLASH memory and 16M x 16 bits of additional board FLASH. The Host
Microprocessor addresses the Compact FLASH memory with 4 of the host
address bus’ 32 lines in conjunction with the data lines. The host accesses
FLASH data over the 16-line host data bus. A host-operated chip-select line
provides control signals for these transactions.

FLASH memory contains the operating system and application code. The
system stores application code in Compact FLASH for fast recovery from
reset conditions. Application code transfers from network or site controllers
may occur in a background mode. Background mode transfers allow the
station to remain operational during new code upgrades.

The data that determines the station personality (codeplug) resides in the 16M
x 16 bit FLASH. The microprocessor addresses the FASH with 24 of the host
address bus’ 32 lines. The host accesses FLASH data with 16 of the data bus’
32 lines. A host-operated chip-select line provides control signals for these
transactions.

During the manufacturing process, the factory programs the codeplug’s
default data. The BRC must download field programming data from network
and site controllers. This data includes operating frequencies and output
power level. The station permits adjustment of many station parameters, but
the station does not store these adjustments. Refer to the Software Commands
chapter for additional information.

Volatile Memory

Each BRC contains 16MB x 32 bits of SDRAM. The BRC downloads station
software code into SDRAM for station use. SDRAM also provides short-term
storage for data generated and required during normal operation. SDRAM is
volatile memory. A loss of power or system reset destroys SDRAM data.

The system performs read and write operations over the Host Address and
Data buses. These operations involve column and row select lines under
control of the Host processor’s DRAM controller. The Host address bus and
column row signals sequentially refresh SDRAM memory locations.

Ethernet Interface

The Host processor’s Communications Processor Module (CPM) provides the
Local Area Network (LAN) Controller for the Ethernet Interface. The LAN
function implements the CSMA/CD access method, which supports the IEEE

802.3 10Base2 standard.

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The LAN coprocessor supports all IEEE 802.3 Medium Access Control,
including the following:

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n framing

n preamble generation

n stripping

n source address generation

n destination address checking

The PCM LAN receives commands from the CPU.

The Ethernet Serial Interface works directly with the CPM LAN to perform
the following major functions:

n 10 MHz transmit clock generation (obtained by dividing the 20 MHz signal

provided by on-board crystal)

n Manchester encoding/decoding of frames

n electrical interface to the Ethernet transceiver

An isolation transformer provides high-voltage protection. The transformer
also isolates the Ethernet Serial Interface (ESI) and the transceiver. The pulse
transformer has the following characteristics:

n Minimum inductance of 75 µH

n 2000 V isolation between primary and secondary windings

n 1:1 Pulse Transformer

5-May-08

The Coaxial Transceiver Interface (CTI) is a coaxial cable line driver and
receiver for the Ethernet. CTI provides a 10Base2 connection via a coaxial
connector on the board. This device minimizes the number of external compo­nents necessary for Ethernet operations.

A DC/DC converter provides a constant voltage of -9 Vdc for the CTI from a

3.3 Vdc source.

The CTI performs the following functions:

n Receives and transmits data to the Ethernet coaxial connection

n Reports any collision that it detects on the coaxial connection

n Disables the transmitter when packets are longer than the legal length

(Jabber Timer)

Digital Signal Processors

The BRC includes one Digital Signal Processor for receive and transmit
processing. This DSP and related circuitry process compressed station
transmit and receive audio and data. The related circuitry includes the
Integrated Circuit (2QIC). The DSP only accepts input and output
signals in digitized form.

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The DSP inputs are digitized receiver signals. The DSP outputs are digitized
voice audio and data (modulation signals). These signals pass from the DSP to
the Exciter section of the Gen3. DSP communicates with the Micropro­cessor via a 32-bit, host data bus on the host
communication between the

The DSP operate from an external 49 MHz clock, provided by the CPLD and
phase locked to the 16.8 MHz local station reference clock. The DSP internal
core operating clock signal is 394MHz, produced by an internal Phase­Locked Loop (PLL).

The DSP accepts receive digitized signals from the 2QIC through the Time­Division Multiplexing (TDM) interface ports. The Gen3 uses 3 of these
ports. All 3 ports use the same clock and framesync signals to input data.
Each port handles digital data for 1 of the 3 branches. Each port handles
digitized data for 6 channels, 2 status words, and 2 power detect words.

The Gen3 accesses its DSP program and signal-processing algorithms in
1440 kB of internal memory. The DSP communicates with the host bus over
an 32-bit interface.

DSP and the host.

processor side. Interrupts drive

5-May-08

The DSP communicates with the 2QIC to provide serial communications to
the receiver paths for receiver control over a Serial Peripheral Interface (SPI)
link. The 2QIC provides a parallel-to-serial conversion circuit that accepts
parallel data from the DSP and serial data to the receive circuitry.

The DSP sends up to six carriers of digitized signal to the 2QIC along with
embedded control signals. Two framed and synchronized data streams are
output. One data stream is I-data, and the other is the Q-data stream. The
control bits are appendended at the end of the data streams. The 2QIC extracts
and applies the control signals. The 2QIC synchronizes the 2QIC I and Q
output frames with system timing signals that exist in the 2QIC. The synchro­nized outputs are sent to a Digital to Analog Converter (DAC) in the exciter
section that converts the digital signals to analog.

2QICplus

The 2QIC controls internal DSP operations. This circuit provides the
following functions:

The 2QICplus is a DSP programmable FPGA that provides the circuit
integration needed to condition, route and control receive and transmit data
between the RF circuitry and the DSP, and provide consolidated monitoring
and control for transceiver. Following are the major functions of
the 2QICplus

n For nitialization and control, the 2QICplus interfaces with the DSP through

address and data buses.

n Provides six Independent Abacus III receiver data and control interfaces

with fault detection and handling

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Gen3 Base Radio Transceiver

n RF Signal Gain Control for 18 receiver paths

n Programmable General-Purpose Input/Output pins for monitor and control

of the transceiver

n Provides clocks required for the transceiver

n Phase detector for the 16.8MHz Synthesizer and PLL with PLL steering

line gate control

n Inputs a site reference signal, demodulates a 1PPS timing marker from this

signal and outputs the 1PPS signal for network timing alignment.

n 15 ms and 7.5 ms timing signals generation. (These signals are synchronize

to the 1 PPS time mark. The system decodes the time mark from the site
reference. Then the system routes the reference to the DSP.)

n Programmable Interrupt Controller for metering and status.

n Provides serial transmit data translation and tranmit control and

synchronization to the network timing

n Complex Mixer capability to translate each of the six receive channels to

DC

n Polyphase 256 FIR filter with decimation by 10 for enhancing channel

selectivity

n Signal Energy detector for signal strength indication used for system signal

path attenuator control

n Provides output serializers to Time Division Multiplex information for six

channels two status values and two Energy Detection values for each
branch

5-May-08

Station Reference Circuitry

The Station Reference Circuitry is a phase-locked loop (PLL). This PLL
consists of a high-stability, Voltage-Controlled, Crystal Oscillator (VCXO)
and a PLL IC. GPS output from the iSC connects to the 5 MHz/1 PPS BNC
connector on the BR backplane. Wiring at this connector routes signals to
EXBRC station reference circuitry.

The PLL compares the 5 MHz reference frequency to the 16.8 MHz VCXO
output. Then the PLL generates a DC correction voltage. The PLL applies this
correction voltage to the VCO through an analog gate. The analog gate closes
when three conditions coexist: (1) The 5 MHz tests stable. (2) The PLL IC is
programmed. (3) Two PLL oscillator and reference signal output alignments
occur.

A loss of the 5 MHz/1PPS signal causes the control voltage enable switch to
open. This permits the PLL to free run, which allows the BR to retain a clock
for control purposes.

When the gate enables, the control voltage from the PLL can adjust the high­stability VCXO frequency. The adjustment can achieve a stability nearly
equivalent to that of the external, 5 MHz frequency reference.

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The correction voltage from the PLL continuously adjusts the VXCO
frequency. The VXCO outputs a 16.8 MHz clock signal. The circuit applies
this clock signal to the receiver, 48 MHz reference and TISIC.

The receivers use the 16.8MHz as the clock input and synthesizer reference.

The 48 MHz EXBRC synthesizer uses the 16.8 MHz as its synthesizer
reference. The 48 MHz synthesizer output is the clock input for the TXDSP I
and Q data reclock circuitry.

The TISIC divides the 16.8 MHz signal by seven, and outputs a 2.4 MHz
signal. This output signal then becomes the 2.4 MHz reference for the Exciter.

Input Ports

One general-purpose input register provides for BRC and station circuit input
signals. The register has 16 input ports. The Host Data Bus conveys input
register data to the Host Microprocessor. Typical inputs include 16.8 and 48
MHz Station Reference Circuitry status outputs and reset status outputs.

Output Ports

Two general-purpose output registers distribute control signals from the Host
Microprocessor to the BRC and station circuitry. One register has 32 output
ports and the other register has 8 output ports. Control signal distribution
occurs over the backplane. The Host Data Bus drives the output ports’ latched
outputs. Typical control signals include front-panel LED signals and SPI
peripheral enable and address lines.

Remote Station Shutdown

The BRC contains power supply shutdown circuitry. This circuitry can send a
shutdown pulse to the Base Radio Power Supply. BRC software generates the
shutdown control pulse.

After receiving a shutdown pulse, the power supply turns off BR power. Shut
down power sources include 3.3, 28.6 and 14.2 Vdc sources throughout the
BR. Due to charges retained by BR storage elements, power supply voltages
may not reach zero. The shutdown only assures that the host processor enters
a power-on-reset state.

A remote site uses the shutdown function to perform a hard reset of all BR
modules.

5-May-08

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3-16 6880801E35- 5-May-08

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Gen3 Base Radio Transceiver

Theory of Operation

- Exciter and Power
Amplifier Section

RF- Exciter Board Table 3-8 describes the basic circuitry of the Exciter. Figure 3-6 shows the

The Exciter and the Power Amplifier (PA) provide the transmitter functions of

the Gen3 800/900 MHz Base Radio. The Exciter module

consists of a printed circuit board, a slide in housing, and associated hardware.
The BRC shares the printed circuit board and housing.

The Exciter connects to the Base Radio backplane through a 168-pin
connector and two blindmate RF connectors. Controller and exciter circuitry
also interconnect on the Exciter/Controller module. Two Torx screws on the
front of the Exciter secure it to the chassis.

An LED identifies the Exciter’s operational condition, as described in the
manual’s Controller section. The Base Radio section of the manual provides
specifications for transmitter circuitry. This information includes data on the
Exciter and PAs.

Exciter with the housing removed. Figure 3-9 show the Exciter’s functional
block diagram.

Table 3-8 Exciter Board Circuitry

5-May-08

Circuit Description

LNODCT IC

Memory & A/D Converter

Frequency Synthesizer
Circuitry

1025 MHz VCO (900 MHz
BR)

• Up-converts baseband data to the transmit
frequency

• Down-converts the PA feedback signal to
baseband

• Uses a baseband Cartesian feedback loop
system, necessary to obtain linearity from the
transmitter and avoid splattering power into
adjacent channels

• Performs training functions for proper
linearization of the transmitter

Serves as the main interface between the
synthesizer, Tranlin IC, A/D, and EEPROM on
the Exciter, and the BRC via the SPI bus

• Consists of a phase-locked loop and VCO

• Provides a LO signal to the LNODCT IC for
the second up-conversion and first down­conversion of the feedback signal from the
PA

Provides a LO signal to the LNODCT IC, for up­conversion to the transmit frequency

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Table 3-8 Exciter Board Circuitry

Circuit Description

Provides a LO signal to LNODCT IC, for the up-

90.3 MHz VCO (900 MHz
BR)

conversion and for the down-conversion of the
feedback signal.
The mixed output becomes the LO signal for
Transmit signal up- and down- conversion

Regulator Circuitry

Linear RF amplifier Stages

Figure 3-6 Exciter Board (with housing removed)

Provides a regulated voltage to various ICs and
RF devices located on the Exciter

Amplifies the RF signal from the Exciter IC to an
appropriate level for input to the PA

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Enhanced Base Transceiver System (EBTS)

3-18 6880801E35- 5-May-08

Memory Circuitry

The memory circuitry is an EEPROM on the Controller portion of the Exciter/
Controller module. The Controller performs memory read and write opera­tions over the parallel bus. The memory device stores the following data...

n kit number

n revision number

n module specific scaling and correction factors

n serial number

n free form information (scratch pad)

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A/D Converter Circuitry

Analog signals from various areas throughout the Exciter board enter the A/D
converter (A/DC). The A/DC converts these analog signals to digital form.
Upon request of the BRC, A/DC output signals enter the BRC via SPI lines.
The Controller periodically monitors all signals.

Some of the monitored signals include amplifier bias and synthesizer signals.

Low Noise Offset Direct Conversion Transmit (LNODCT) IC
Circuitry

The Low Noise IC is a main interface between the Exciter and BRC. The
BRC’s Digital Signal Processor (DSP) sends digitized signals (baseband data)
to the Exciter over the DSP data bus.

The differential data clock signal serves as a 2.4 MHz reference signal to the
Low Noise IC’s internal synthesizer. The Low Noise IC compares the
reference signal with the outputs of Voltage Controlled Oscillators (VCOs).
The Low Noise IC might sense that a VCO’s output is out of phase or off­frequency. If so, then the Low Noise IC sends correction pulses to the VCO.
The pulses adjust VCO output, thereby matching phase and frequency with
the reference.

5-May-08

The Low Noise IC up-converts baseband data from the BRC to the transmit
frequency. The Low Noise IC also down-converts the Transmit signal from
the Power Amplifier to baseband data for cartesian feedback linearization.

The BRC uses the Serial Peripheral Interface (SPI) bus to communicate with
the Low Noise IC. The SPI bus serves as a general purpose, bi-directional,
serial link between the BRC and other Base Radio modules, including the
Exciter. The SPI carries control and operational data signals to and from
Exciter circuits.

Synthesizer Circuitry

The synthesizer circuit consists of the Phase-Locked Loop (PLL) IC and
associated circuitry. This circuit’s controls the 1025 MHz VCO signal. An
internal phase detector generates a logic pulse. This pulse is proportional to
the phase or frequency difference between the reference frequency and loop
pulse signal.

The charge pump circuit generates a correction signal. The correction signal
moves up or down in response to phase detector output pulses. The correction
signal passes through the low-pass loop filter. The signal then enters the 1025
MHz Voltage Controlled Oscillator (VCO) circuit.

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Gen3 Base Radio Transceiver

1025 MHz Voltage Controlled Oscillator (VCO)

For proper operation, the VCO requires a very low-noise, DC supply voltage.
An ultra low-pass filter prepares the necessary low-noise voltage and drives
the oscillator.

A portion of the oscillator output signal enters the synthesizer circuitry. The
circuitry uses this feedback signal to generate correction pulses.

The 1025MHz VCO output mixes with the 90.3 MHz VCO output. The result
is a Local Oscillator [LO) signal for the Low Noise IC. The LNODCT uses
this LO signal to up-convert the programmed transmit frequency. The Low
Noise IC also uses the LO signal to down-convert the PA feedback signal.

90.3 MHz Voltage Controlled Oscillator (VCO)

The synthesizer within the Low Noise IC sets the 90.3 MHz signal. The 90.3
MHz VCO provides a LO signal to the LNODCT IC. The Low Noise IC uses
this signal in up-converting and down-converting the feedback signal.

Regulator Circuitry

The voltage regulators generate three regulated voltages: +3 Vdc, +5 Vdc and
+11.7 Vdc. The regulators obtain input voltages from the +3.3 Vdc and +14.2
Vdc backplane voltages. The regulated voltages power various ICs and RF
devices in the Exciter.

Linear RF Amplifier Stages

The linear RF amplifiers boost the RF signal from the Low Noise IC. The RF
Amplifier generates an appropriate signal level to drive the PA.

5-May-08

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Volume 2 Base Radio Transceiver

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Gen3 Base Radio Transceiver

RF- Receiver Board Table 3-9 lists the Receiver circuitry. Figure 3-7 shows the Receiver Board

with the housing removed. Figure 3-10 shows the Receiver’s functional block
diagram.

Table 3-9 Receiver Circuitry

Circuit Description

Frequency Synthesizer
Circuitry

Receiver Front-End
Circuitry

Custom Receiver IC
Circuitry

Consists of a phase-locked loop and VCO. It
generates the 1st LO injection signal for all
three receivers.

Provides filtering, amplification, and the 1st
down conversion of the receive RF signal. This
block includes digital step attenuators at the 1st
IF.

Consists of a custom IC to perform the 2nd
down conversion, filtering, amplification, and
conversion of the receive signal. This block
outputs the receive signal as differential data to
the BRC.

5-May-08

Address Decode, A/D
Converter, & Memory
Circuitry

Local Power Supply
Regulation

Frequency Synthesizer and VCO Circuitry

The synthesizer and VCO circuitry generate the RF signal used to produce the
1st LO injection signal for the first mixer in all the Receiver front end circuits.
Functional operation of these circuits involves a Phase-Locked Loop (PLL)
and VCO.

The PLL IC receives frequency selection data from the BRC module micro­processor via the SPI bus. Once programmed, the PLL IC compares a

2.1 MHz reference signal from the BRC with a feedback sample of the VCO
output from its feedback buffer.

The PLL ICC generates correction pulses, depending on whether the feedback
signal is higher or lower in frequency than the 2.1 MHz reference. The width
of these pulses depends on the amount of difference between the 2.1 MHz
reference and the VCO feedback.

Performs address decoding for board and chip­select signals. Converts analog status signals
to digital format for use by the BRC. A memory
device holds module-specific information.

Accepts +14.2 VDC input from the backplane
interconnect board. Also generates two
+10 VDC, a +11.5 VDC, and two +5 VDC
signals for the receiver.

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Figure 3-7 Receiver Board (with housing removed)

5-May-08

The up/down pulses enter a charge pump circuit. The charge pump outputs a
DC voltage proportional to the pulse widths. After low-pass filtering, this DC
voltage enters the VCO circuit as the control voltage. The control voltage
measures between +2.5 VDC and +7.5 VDC.

The DC control voltage from the synthesizer enters the VCO. The VCO
generates the RF signal that the circuit uses to produce the 1st LO injection
signal. The VCO responds to the DC control voltage by generating the appro­priate RF signal. This signal passes through a buffer to the 1st LO injection
amplifier. A sample of this signal returns to the PLL IC through a buffer to
close the VCO feedback loop.

Receiver Front End Circuitry

The station receive RF signal enters the Receiver through the RF-type
connector on the back of the Receiver board. The circuit low-pass filters and
amplifies this signal. The amplified output passes through an image filter
before entering the 1st mixer. The signal mixes with the 1st LO injection
signal to produce a 73.35 MHz 1st IF signal.

The 1st IF signal passes through a four-pole, bandpass filter and enters a
buffer amplifier. The buffer amplifier output signal again undergoes four­pole, bandpass filtering. The resultant signal then passes through a digital
attenuator. The BRC determines the amount of attenuation. The resulting
signal then enters the RF input of the custom Receiver IC.

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Custom Receiver IC Circuitry

The custom Receiver IC provides additional amplification, filtering, and a
second down-conversion. The IC converts the 2nd IF signal to a digital
signal. The digital signal exits the receiver IC via differential driver circuitry,
and passes to the BRC. This data signal contains I and Q information, AGC
information, and other data transfer information. The BRC uses this infor­mation to facilitate processing of the receive signal.

The remainder of the custom Receiver IC circuitry consists of timing and tank
circuits. These circuits support the internal oscillator, 2nd LO synthesizer, and
2nd IF circuitry.

A serial bus provides data communications between the custom Receiver IC
and the DSP Glue ASIC (DGA). These circuits are on the BRC. The serial
bus enables the DGA to perform several control functions...

n control various current and gain settings

n establish the data bus clock rate

n program the 2nd LO

n perform other control functions

5-May-08

Address Decode Circuitry

Address decode circuitry enables the BRC to use the SPI bus to select a
specific device on a specific Receiver for control or data communication
purposes.

If board-select circuitry decodes address lines A2 through A5 as the Receiver
address, it enables the chip select circuitry. The chip select circuitry then
decodes address lines A0 and A1. The decoding process generates the chip
select signals for the EEPROM, A/D converter, and PLL IC.

Memory Circuitry

The memory circuitry consists of three EEPROMs located on the Receiver.
The BRC performs memory read and write operations via the SPI bus. Infor­mation stored in this memory device includes...

n the kit number

n revision number

n module specific scaling and correction factors

n free form module information (scratch pad)

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A/D Converter Circuitry

Analog signals from various strategic operating points throughout the
Receiver board pass through the A/D converter. These analog signals become
a digital signal. Upon request of the BRC, this signal travels to the BRC via
the SPI lines.

Voltage Regulator Circuitry

The voltage regulator circuitry consists of two +10 VDC, a +10.8 VDC, and
two +5 VDC regulators. The two +10 VDC and the +10.8 VDC regulators
accept the +14.2 VDC input from the backplane interconnect board. These
regulators produce operating voltages for the Receiver circuitry.

The +10 VDC regulators each feed a +5 VDC regulator. One of these
regulators outputs Analog +5 VDC. The other regulator outputs Digital +5
VDC operating voltages for use by the custom Receiver IC.

The backplane interconnect board also produces a +5.1 VDC operating
voltage. This voltage powers the remainder of the Receiver circuitry.

Gen3

Receiver Diversity
Uses and Cautions

The Gen3 BR Receiver board can be used in one, two, or three-

branch diversity systems. The
active receivers. To view the
(See software commands.) Each repeater’s configuration can be changed in
the field to match the number of receivers connected to antennas. To change

diversity parameter, use the command (see software commands). For

the
the iDEN system to work optimally, the
number of receivers connected to antennas.

diversity parameter determines the number of

diversity parameter, use the MMI command.

diversity parameter must match the

CAUTION

Improperly setting the diversity parameter will cause serious
system degradation.

Modifying Base Radios from Three Branch to Two Branch
Diversity

When modifying a three-branch Base Radio to a two-branch Base Radio,
observing all precautionary statements in the previous paragraph is important.

To modify a three-branch Base Radio to a two-branch Base Radio:

5-May-08

Enhanced Base Transceiver System (EBTS)

3-24 6880801E35- 5-May-08

1. Disconnect the RF cable from the RX3 connector on the Base Radio.

Volume 2 Base Radio Transceiver

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Gen3 Base Radio Transceiver

2. Connect an SMA male load (Motorola part number 5882106P03) to the

RX3 connector on the Base Radio.

The SMA male load is required to limit the amount of radiated emissions.

3. Verify that the

Diversity Uses and Caution paragraph above.

Modifying Base Radios from Two Branch to Three Branch
Diversity

1. Remove the SMA male load from the RX3 connector of the Base Radio

that you wish to convert from two-branch diversity to three-branch
diversity.

2. Connect the Receive Antenna #3 RF cable to the RX3 connector on the

Base Radio.

3. Verify that the

Diversity Uses and Cautions paragraph.

diversity parameter is set properly, according to the

diversity parameter is set properly, according to the

5-May-08

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PA Theory of Operation

Fan Module The PA contains a fan assembly to maintain normal operating temperature

through the use of a cool air intake. The fan assembly consists of three
individual fans in which airflow is directed across the PA heatsink.

The current draw of the fans is monitored by the DC/Metering Board. A
voltage representative of the current draw is monitored by the BRC. The BRC
flags the iSC if an alarm is triggered. The PA LED on the front panel of the
BRC also lights, however the PA does not shut down due to a fan failure
alone.

DC Core Board

Driver Board

Final Board

The Core Board communicates with the other base radio modules as well as
internal PA modules. It utilizes non-volatile memory (NVM) via an EEPROM
to store unique PA calibration information.

The Driver Amplifier Board provides the first two stages of RF amplification
within the PA. It accepts the output RF signal from the transceiver module
(via the core board) and amplifies it to an intermediate power level. The
Driver Amplifier Board also provides:

■ Gain compensation over temperature.

■ On-board DC regulation.

■ Transmitter standby functionality

The Final Amplifier Board provides the last two stages of RF amplification,

including the second RF gain stage (parallel stage). Final utilizes two

Final Amplifier Boards:

■ RF power splitting (4–way)

■ RF power combining (4–way)

■ Diagnostics

■ Transmitter standby functionality

Isolator Board

5-May-08

Enhanced Base Transceiver System (EBTS)

5-14 6880801E35- 5-May-08

The Isolator provides proper RF loading to the final module output regardless
of the load presented to the output of the PA itself. The Isolator contains a
load resistor to dissipate any reflected power caused by load mismatches at
the output of the PA.

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Low Pass Filter
(LPF) Board

Null Board

Distribution Board

PA Theory of Operation

5-May-08

The LPF Board reduces harmonic power levels conducted through the PA RF
output connector to acceptable levels. The LPF Board has forward and
feedback RF power detectors to monitor forward and reflected output power
from the PA, in reference to its output connector. It has a single stage isolator
that provides > 20dB isolation with < 0.35dB insertion loss. It also provides a
low pass filter with < 0.54dB of in-band insertion loss.

The Null Board provides the +28Vdc supply routing from the Core board to
the Distribution board (which routes it to the Final board). It also provides the
necessary bulk capacitance that is warranted by the Final board.

The Distribution Board provides for all signal routing from the Core and the
Null boards to the Final and LPF boards:

■ RF signal from the driver module is split and provided as the input to each

of the two final modules.

■ RF output from both of the final modules is combined to a single path and

provided as the input to the isolator.

■ RF power is coupled off the combined port and fed back to the XCVR

■ DC Power routing from the NULL board to the Final board

■ Forward and reverse DC signaling from the LPF board

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DC Power Supply for Gen3 Base Radios

DC Power Supply for Gen3 Base Radio

Gen3

Power Supply
Overview

When operating from a DC source (43.2 VDC to 60 VDC, positive or negative
ground), the supply generates two DC output voltages of 29 VDC with
reference to output ground. The battery charger is not usable when operating
from a DC input power source.

Figure 6-3 shows the Gen3 Power Supply.

5-May-08

5-May-08 6880801E35- 6-9

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DC Power Supply for Gen3 Base Radios

Figure 6-3 Gen3 Power Supply (Front and Rear Views)

Gen3

Power Supply
Controls and

Indicators

FRONT REAR

Table 6-8 summarizes LED indications on the Gen3 Power

Supply during normal operation. Table 6-9 summarizes the Power Supply and

Battery Charger states of the Gen3 Power Supply during normal

operation .

Table 6-8 Power Supply Indicators

LED Condition Indications

Power Supply is on, and operating under
normal conditions with no alarms

Power Supply is turned off or required power
is not available

Power Supply fault or load fault on any
output, or input voltage is out of range

Green

Red

Solid (on)

Off

Solid (on)

Blinking Power Supply is impaired

Enhanced Base Transceiver System (EBTS)

6-10 6880801E35- 5-May-080

Off

Power Supply is operating normally, with no
alarms

Volume 2 Power Supply

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DC Power Supply for Gen3 Base Radio

Table 6-11 Normal Operational Parameters (continued)

Description Value or Range

Battery Charger Ripple

Efficiency

Note “Load Ohms” corresponds to the setting on the electronic load for the

equivalent Aux DC or battery charger output current, based on a maximum
expected Aux DC voltage of 29.72V and a maximum battery charger output
of 57.6VDC.

Table 6-12 Normal DC Operational Parameters

Description Value or Range

43.0 VDC (minimum)

DC Input Voltage

Main DC Ouput Load

54.3 VDC (nominal)

62.4 VDC (maximum)

0.1 ADC (minimum)

10.5 ADC (nominal)

21.0 ADC (maximum)

0

0.1 ADC / 290 Load Ohms (minimum)

Aux DC Output Load

Main DC Output Voltage

Aux DC Output Voltage

Main DC Output VDC Ripple 250 mVp-p

Aux DC Output Ripple 250 mVp-p

Efficiency

Low Voltage Disconnect

DC Input Overvoltage Lockout

1.5 ADC / 19 Load Ohms (nominal)

3.0 ADC / 9.5 Load Ohms (maximum)

28.16 VDC (minimum)

28.94 VDC (nominal)

29.72 VDC (maximum)

28.07 VDC (minimum)

28.94 VDC (nominal)

29.81 VDC (maximum)

82 % (minimum)
85% (nominal)

41 VDC (minimum)
42 VDC (nominal)
43 VDC (maximum)

62.4 VDC (minimum)

62.7 VDC (nominal)

63.0 VDC (maximum)

5-May-08 6880801E35- 6-13

Note “Load Ohms” corresponds to the setting on the electronic load for the

equivalent Aux DC output current, based on a maximum expected Aux DC
voltage of 29.72V.

Enhanced Base Transceiver System (EBTS)

Power Supply Volume 2

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DC Power Supply for

Gen3 Base Radios

Table 6-11 Normal Operational Parameters (continued)

Description Value or Range

Startup Settle Time 5 seconds

0.1 ADC (minimum)

Main DC Output Load

Aux DC Output Load

Battery Charger Load

Main DC Output Voltage

Aux DC Output Voltage

9.0 ADC (nominal)

18.0 ADC (maximum)

0.1 ADC / 290 Load Ohms (minimum)

1.5 ADC / 19 Load Ohms (nominal)

3.0 ADC / 9.5 Load Ohms (maximum)

0.1 ADC / 576 Load Ohms (minimum)

1.5 ADC / 38 Load Ohms (nominal)

3.0 ADC / 19 Load Ohms (maximum)

28.16 VDC (minimum)

28.94 VDC (nominal)

29.72 VDC (maximum)

28.07 VDC (minimum)

28.94 VDC (nominal)

29.81 VDC (maximum)

Battery Charger Output Voltage

Main DC Output Overcurrent

Aux DC Overcurrent

Battery Charger Overcurrent

Main DC Output Open Circuit
Voltage

Aux DC Open Circuit Voltage 32.5 VDC

Battery Charger Open Circuit
Voltage

Main DC Output Overvoltage Limit

Battery Charger Overvoltage Limit 32.5 VDC

-42.00 VDC (minimum)

-60.00 VDC (maximum)

20.0 ADC (minimum)

23.0 ADC (nominal)

26.0 ADC (maximum)

4.0 ADC (minimum)

5.0 ADC (nominal)

6.0 ADC (maximum)

3.0 ADC (minimum)

3.5 ADC (nominal)

4.0 ADC (maximum)

32.5 VDC

62.5 VDC

30.0 VDC (minimum)

32.5 VDC (maximum)

8

Enhanced Base Transceiver System (EBTS)

6-12 6880801E35- 5-May-08

Main DC Output VDC Ripple 250 mVp-p

Aux DC Output Ripple 250 mVp-p

Volume 2 Power Supply

EXHIBIT D1-5

EQUIPMENT TYPE: ABZ89FC5815

APPLICANT: MOTOROLA

Gen3

Power Supply
Performance
Specifications

DC Power Supply for Gen3 Base Radio

Table 6-9 Power Supply ON/OFF Switch

Switch

Position

On

Off

Power Supply State

■ Power Factor Correction (PFC)

section is active (AC input only)

■ Main DC converter runs to

create the MAIN and AUX DC
outputs

■ Main DC converter is turned

OFF and the MAIN and AUX
DC outputs become 0.0VDC

■ PFC section continues to run in

an idle mode

Battery Charger

State

Can be started if desired

(DC input only)

Disabled (DC input only)

Table 6-10 through Table 6-12 lists the specifications for the Gen3
Power Supply.

5

Table 6-10 Environmental Specifications

Operational

Description

Temperature -30° to 60° C 60° to 70° C

Relative Humidity

Altitude

(No Derating)

5 to 95%
Non-condensing

Sea Level to
10,000 ft.
(3050 Meters)

Functional

(With Derating)

5 to 95%
Non-condensing

Sea Level to
10,000 ft.
(3050 Meters)

Storage Shipment

-40° to 85° C
Non-condensing

5 to 95%
Non-condensing

Sea Level to
10,000 ft.
(3050 Meters)

40° to 85° C

5 to 95%
Non-condensing

Sea Level to
10,000 ft.
(3050 Meters)
nonpressurized,
50,000 ft.
(15250 Meters)
pressurized

5-May-08 6880801E35- 6-11

Enhanced Base Transceiver System (EBTS)