Motorola 89FC5794 Users manual

APPLICANT: MOTOROLA INC. EQUIPMENT TYPE: ABZ89FC5794

INSTRUCTION MANUALS

The instruction and service manual for this base radio are not published at this time. However, draft copy of the
manual is available and has been included as part of the filing package in the form of an electronic pdf document.

Upon request, published and/or printed manuals will be sent to the commission and/or telecommunication
certification body (TCB) as soon as they become available. All of the descriptions and schematics included this
filing package are up to date.

EXHIBIT 8

APPLICANT: MOTOROLA INC. EQUIPMENT TYPE: ABZ89FC5794

TUNE-UP PROCEDURE

There is no field tune-up procedure. All adjustments are software controlled and are pre-set at the factory. Certain
station operating parameters can be changed via man-machine interface (MMI) commands, within predetermined
limits. Examples include transmit / receiver operating frequencies and power level.

EXHIBIT 9

Network Solutions Sector

ENHANCED BASE TRANSCEIVER SYSTEM (EBTS)

VOLUME 2 OF 3

BASE RADIOS

© 2000 Motorola, Inc.
All Rights Reserved
Printed in U.S.A.

68P81099E10-D

ECCN 5E992

FCC INTERFERENCE WARNING

The FCC requires that manuals pertaining to Class A computing devices must contain warnings about possible interference with local residential radio and TV reception. This
warning reads as follows:

Note: This equipment has been tested and found to comply with the limits for a Class A digital device , pursuant to Part 15 of the FCC Rules. These limits
are designed to provide reasonable protection against harmful interference when the equipment generates, uses, and can radiate radio frequency
energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of
this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own
expense.

INDUSTRY OF CANADA NOTICE OF COMPLIANCE

This Class A digital apparatus meets all requirements of the Canadian Interference-Causing Equipment Regulations.

Cet appareil numérique de la classe A respecte toutes les exigences du Règlement sur le matériel brouilleur du Canada.

COMMERCIAL WARRANTY (STAND ARD)

Motorola radio communications products (the “Product”) is warranted to be free from defects in material and workmanship for a period of ONE (1) YEAR (except for crystals and
channel elements which are warranted for a period of ten (10 y ears) from the date of shipment. Parts including crystals and channel elements, will be replaced free of charge f or
the full warranty period but the labor to replace defective parts will only be provided for One Hundred-Twenty (120) days from the date of shipment. Thereafter purchaser must
pay for the labor involved in repairing the Product or replacing the parts at the prevailing rates together with any transportation charges to or from the place where warranty
service is provided. This express warranty is extended by Motorola, 1301 E. Algonquin Road, Schaumburg, Illinois 60196 to the original end use purchaser only, and only to
those purchasing for purpose of leasing or solely for commercial, industrial, or governmental use.

THIS WARRANTY IS GIVEN IN LIEU OF ALL OTHER WARRANTIES EXPRESS OR IMPLIED WHICH ARE SPECIFICALLY EXCLUDED, INCLUDING WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL MOTOROLA BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL DAMAGES TO
THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW.

In the event of a defect, malfunction or failure to conform to specifications established by Motorola, or if appropriate to specifications accepted by Motorola in writing, during the
period shown, Motorola, at its option, will either repair or replace the product or refund the purchase price thereof. Repair at Motorola's option, may include the replacement of
parts or boards with functionally equivalent reconditioned or new parts or boards. Replaced parts or boards are warranted for the balance of the original applicable warranty
period. All replaced parts or product shall become the property of Motorola.

This express commercial warranty is extended by Motorola to the original end user purchaser or lessee only and is not assignable or transferable to any other party. This is the
complete warranty for the Product manufactured by Motorola. Motorola assume no ob ligations or liability for additions or modifications to this warranty unless made in writing and
signed by an officer of Motorola. Unless made in a separate agreement between Motorola and the original end user purchaser, Motorola does not warrant the installation,
maintenance or service of the Products.

Motorola cannot be responsible in any way for any ancillary equipment not furnished by Motorola which is attached to or used in connection with the Product, or for operation of
the Product with any ancillary equipment, and all such equipment is expressly excluded from this warranty. Because each system which may use Product is unique, Motorola
disclaims liability for range, coverage, or operation of the system as a whole under this warranty.

This warranty does not cover:

a) Defects or damage resulting from use of the Product in other than its normal and customary manner.

b) Defects or damage from misuse, accident, water or neglect

c) Defects or damage from improper testing, operation, maintenance installation, alteration, modification, or adjusting.

d) Breakage or damage to antennas unless caused directly by defects in material workmanship.

e) A Product subjected to unauthorized Product modifications, disassemblies or repairs (including without limitation, the addition to the Product of non-Motorola supplied
equipment) which adversely affect performance of the Product or interfere with Motorola's normal warranty inspection and testing of the Product to verify any warranty claim.

f) Product which has had the serial number removed or made illegible.

g) A Product which, due to illegal to unauthorized alteration of the software/firmware in the Product, does not function in accordance with Motorola's published specifications or
the FCC type acceptance labeling in effect for the Product at the time the Product was initially distributed from Motorola.

This warranty sets forth the full extent of Motorola's responsibilities regarding the Product. Repair, replacement or refund of the purchase date, at Motorola’s option is the
exclusive remedy. IN NO EVENT SHALL MOTOROLA BE LIABLE FOR DAMAGES IN EXCESS OF THE PURCHASE PRICE OF THE PRODUCT, FOR ANY LOSS OF USE,
LOSS OR TIME, INCONVENIENCE, COMMERCIAL LOSS, LOST PROFITS OR SAVINGS OR OTHER INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGE ARISING
OUT OF THE USE OR INABILITY TO USE SUCH PRODUCT, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW.

SOFTWARE NOTICE/WARRANTY

Laws in the United States and other countries preserve for Motorola certain exclusiv e rights f or cop yrighted Motorola softw are such as the e xclusive rights to reproduce in copies
and distribute copies of such Motorola software. Motorola software may be used in only the Product in which the software was originally embodied and such software in such
Product may not be replaced, copied, distributed, modified in any w ay, or used to produce an y deriv ativ e thereof. No other use including without limitation alteration, modification,
reproduction, distribution, or reverse engineering of such Motorola software or exercise of rights in such Motorola software is permitted. No license is granted by implication,
estoppel or otherwise under Motorola patent rights or copyrights.

This warranty extends only to individual products: batteries are excluded, but carry their own separate limited warranty.

In order to obtain performance of this warranty, purchaser must contact its Motorola salesperson or Motorola at the address first above shown, attention Quality Assurance
Department.

This warranty applies only within the fifty (50) United States and the District of Columbia.

1 Contents

Contents.......................................................................................................................... i

List of Figures .............................................................................................................. iv

List of Tables................................................................................................................vi

Foreword................................................................................................................................. ix

General Safety Information .................................................................................................... xi

800/900/1500 MHz

Base Radio Overview...............................................................................................1-1

Single Carrier Base Radio Overview.................................................................................... 1-4

QUAD Channel Base Radio Overview ................................................................................ 1-9

800/900/1500 MHz Base Radio Controller – CLN1469;

1500 MHz MC1 Base Radio Controller – TLN3425 ................................................2-1

800 MHz QUAD Channel Base Radio Controller .............................................................2-12

800 MHz Exciter – TLN3337;

900 MHz Exciter – CLN1357;

1500 MHz Exciter – TLN3428...................................................................................5-1

QUAD Channel 800 MHz Exciter ....................................................................................... 5-7

QUAD-Channel Power Amplifiers: 40W, 800 MHz – TLF2020 (TTF1580);

70W, 800 MHz – TLN3335 (CTF1040);
60W, 900 MHz – CLN1355 (CLF1300);
40W, 1500 MHz – TLN3426;

800 MHz QUAD – CLF1400 ......................................................................................6-1

Theory of Operation .............................................................................................................6-6

DC Power Supply for QUAD Channel Base Radios...............................................7-1

QUAD CHANNEL DC Power Supply.................................................................................7-4

AC Power Supply.......................................................................................................8-1

800 MHz 3X Receiver – CLN1283;

900 MHz 3X Receiver – CLN1356............................................................................9-1

1500 MHz Receiver – TLN3427..........................................................................................9-8

Network Solutions Sector

68P81099E10-D 4/1/2000-UP

1301 E. Algonquin Road, Schaumburg, IL 60196

i

Contents EBTS System Manual - Vol 2

800 MHz QUAD Channel Receiver – CLN1283;..............................................................9-12

Troubleshooting Single Channel Base Radios ....................................................10-1

Base Radio/Base Radio FRU Replacement Procedures.....................................................10-5

Station Verification Procedures..........................................................................................10-9

Single Channel BR Backplane..........................................................................................10-35

Troubleshooting QUAD Channel Base Radios..................................................... 11-1

Base Radio/Base Radio FRU Replacement Procedures.....................................................11-5

Station Verification Procedures........................................................................................11-10

QUAD Channel BR Backplane........................................................................................ 11-22

QUAD Base Radio Signals............................................................................................... 11-35

Transmitter & Receiver Verification Procedures for Beta- Release Equipment 12-1

Acronyms .....................................................................................................................13

Index ....................................................................................................................Index-1

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68P81099E10-D 4/1/2000

Contents EBTS System Manual - Vol 2

List of Figures

List of Figures

Figure:1-1 Base Radio (Typical) ..................................................................................................................... 1-4

Figure:1-2 QUAD Channel Base Radio (Typical) .......................................................................................... 1-9

Figure:1-3 800/900 MHz Base Radio Functional Block Diagram................................................................ 1-15

Figure:1-4 1500 MHz Base Radio Functional Block Diagram ..................................................................... 1-16

Figure:1-5 800 MHz QUAD Channel Base Radio Functional Block Diagram ............................................ 1-17

Figure:2-1 Base Radio Controller, version CLN1469 (with cover removed) ................................................. 2-2

Figure:2-2 Base Radio Controller, version TLN3425 (with cover removed).................................................. 2-2

Figure:2-3 BR Controller (Front View)........................................................................................................... 2-3

Figure:2-4 Base Radio Controller, version CLN1469 (with cover removed) ............................................... 2-12

Figure:2-5 BR Controller (Front View)......................................................................................................... 2-13

Figure:2-6 800/900 MHz Base Radio Controller Functional Block Diagram

(Sheet 1 of 2) ................................................................................................................................2-23

Figure:2-6 800/900 MHz Base Radio Controller Functional Block Diagram

(Sheet 2 of 2) ................................................................................................................................2-24

Figure:2-7 1500 MHz Base Radio Controller Functional Block Diagram

(Sheet 1 of 2) ................................................................................................................................2-25

Figure:2-8 1500 MHz Base Radio Controller Functional Block Diagram (Sheet 2 of 2)............................. 2-26

Figure:2-7 QUAD CHANNEL Base Radio Controller Functional Block Diagram

(Sheet 1 of 2) ................................................................................................................................2-27

Figure:2-7 QUAD CHANNEL Base Radio Controller Functional Block Diagram

(Sheet 2 of 2) ................................................................................................................................2-28

Figure:3-1 800/900 MHz Exciter (with cover removed)................................................................................. 5-2

Figure:3-2 1500 MHz Exciter, version TLN3428 (with top removed) ........................................................... 5-3

Figure:3-3 800 MHz QUAD Channel Exciter (with cover removed)............................................................. 5-7

Figure:3-4 Exciter Functional Block Diagram .............................................................................................. 3-11

Figure:3-5 Exciter Functional Block Diagram .............................................................................................. 3-12

Figure:3-6 Exciter Functional Block Diagram .............................................................................................. 3-13

Figure:3-7 Exciter Functional Block Diagram .............................................................................................. 3-14

Figure:4-1 70W, 800 MHz PA – TLN3335 (with cover removed)................................................................. 6-2

Figure:4-2 60W, 900 MHz PA – CLN1355 (with cover removed)................................................................. 6-3

Figure:4-3 40W, 1500 PA (with cover removed)............................................................................................ 6-4

Figure:4-4 QUAD Channel PA (with cover removed).................................................................................... 6-5

Figure:4-5 TLF2020 (TTF1580B) 40 W, 800 MHz Power Amplifier Functional Block Diagram

(Sheet 1 of 1)................................................................................................................................ 4-13

Figure:4-6 TLN3335 (CTF1040) 70 W, 800 MHz Power Amplifier Functional Block Diagram

(Sheet 1 of 1)................................................................................................................................ 4-14

Figure:4-7 60W, 900 MHz Power Amplifier Functional Block Diagram

(Sheet 1 of 1)................................................................................................................................ 4-15

iv

68P81099E10-D 1/15/2000

EBTS System Manual - Vol 2 Contents

List of Figures

Figure:4-8 Power Amplifier Functional Block Diagram............................................................................... 4-16

Figure:4-9 QUAD Channel Power Amplifier Functional Block Diagram (Sheet 1 of 1)............................. 6-17

Figure:5-1 DC Power Supply .......................................................................................................................... 7-2

Figure:5-2 Quad Carrier Power Supply........................................................................................................... 7-4

Figure:5-3 DC Power Supply Functional Block Diagram

(Sheet 1 of 2) ..................................................................................................................................7-7

Figure:5-3 DC Power Supply Functional Block Diagram

(Sheet 2 of 2) ..................................................................................................................................7-8

Figure:5-3 QUAD Channel DC Power Supply Functional Block Diagram

(Sheet 1 of 2).................................................................................................................................. 7-9

Figure:5-3 QUAD Channel DC Power Supply Functional Block Diagram

(Sheet 2 of 2) ................................................................................................................................7-10

Figure:6-1 AC Power Supply (front view)...................................................................................................... 8-2

Figure:6-2 AC Power Supply Functional Block Diagram (Sheet 1 of 2)........................................................ 8-5

Figure:6-2 AC Power Supply Functional Block Diagram

(Sheet 2 of 2) ..................................................................................................................................8-6

Figure:7-1 QUAD Channel Receiver (with cover removed)........................................................................... 9-1

Figure:7-2 Receiver (with top removed) ......................................................................................................... 9-8

Figure:7-3 3X Receiver (with cover removed).............................................................................................. 9-12

Figure:7-4 3X Receiver Functional Block Diagram...................................................................................... 9-17

Figure:7-5 Receiver Functional Block Diagram............................................................................................ 9-18

Figure:7-6 3X Receiver Functional Block Diagram...................................................................................... 9-19

Figure:7-7 Receiver Functional Block Diagram............................................................................................ 9-20

Figure:8-1 Procedure 1 Troubleshooting Flowchart...................................................................................... 10-3

Figure:8-2 Procedure 2 Troubleshooting Flowchart...................................................................................... 10-4

Figure:8-3 Transmitted Signal Spectrum (800 MHz BR) ........................................................................... 10-15

Figure:8-4 Transmitted Signal Spectrum (800 MHz BR) ........................................................................... 10-19

Figure:8-5 Transmitted Signal Spectrum (900 MHz BR) ........................................................................... 10-23

Figure:8-6 Transmitted Signal Spectrum (1500 MHz BR) ......................................................................... 10-27

Figure:8-7 Base Radio Backplane Connectors............................................................................................ 10-37

Figure:9-1 Procedure 1 Troubleshooting Flowchart...................................................................................... 11-3

Figure:9-2 Procedure 2 Troubleshooting Flowchart...................................................................................... 11-4

Figure:9-3 Quad Channel Spectrum (800 MHz BR)................................................................................... 11-16

Figure:9-4 Base Radio Backplane Connectors............................................................................................ 11-23

Figure:10-1 Quad Channel Spectrum (800 MHz BR)..................................................................................... 12-5

68P81099E10-D 1/15/2000

v

Contents EBTS System Manual - Vol 2

List of Tables

List of Tables

Table 1-1
Table 1-2
Table 1-3
Table 1-4
Table 1-5
Table 1-6
Table 1-7
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-9
Table 3-1
Table 3-2
Table 4-1
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 5-5
Table 5-6
Table 6-1
Table 6-2
Table 6-3
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
Table 7-6
Table 7-7
Table 8-1
Table 8-2

Chapter Topics............................................................................................................................... 1-1

BR General Specifications............................................................................................................. 1-5

Transmit Specifications ................................................................................................................. 1-6

Receive Specifications................................................................................................................... 1-6

QUAD Channel BR General Specifications................................................................................ 1-10

Transmit Specifications ............................................................................................................... 1-11

Receive Specifications................................................................................................................. 1-11

BR Controller Indicators................................................................................................................ 2-3

BR Controller Controls.................................................................................................................. 2-4

Pin-outs for the STATUS Connector............................................................................................. 2-5

BR Controller Circuitry ................................................................................................................. 2-5

Host Glue ASIC Functions ............................................................................................................ 2-6

BR Controller Indicators.............................................................................................................. 2-13

BR Controller Controls................................................................................................................ 2-14

Pin-outs for the STATUS Connector........................................................................................... 2-15

BR Controller Circuitry ............................................................................................................... 2-15

Exciter Circuitry............................................................................................................................. 5-4

Exciter Circuitry............................................................................................................................. 5-8

Power Amplifier Circuitry............................................................................................................. 6-6

DC Power Supply Indicators ......................................................................................................... 7-1

DC Power Supply Specifications................................................................................................... 7-2

DC Power Supply Circuitry........................................................................................................... 7-3

DC Power Supply Indicators ......................................................................................................... 7-5

DC Power Supply Specifications................................................................................................... 7-5

DC Power Supply Circuitry........................................................................................................... 7-6

AC Power Supply Indicators ......................................................................................................... 8-1

AC Power Supply Specifications................................................................................................... 8-2

AC Power Supply Circuitry........................................................................................................... 8-3

Receiver FRUs............................................................................................................................... 9-2

800 MHz Base Radio Receiver Board/BR Backplane Compatibility ........................................... 9-2

900 MHz Base Radio Receiver Board/BR Backplane Compatibility ........................................... 9-2

Receiver ROM Compatibility........................................................................................................ 9-3

Receiver Circuitry.......................................................................................................................... 9-5

Receiver Circuitry and Functions .................................................................................................. 9-9

Receiver Circuitry........................................................................................................................ 9-14

Recommended Test Equipment................................................................................................... 10-2

40W, 800 MHz PA Transmitter Parameters.............................................................................. 10-13

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68P81099E10-D 4/1/2000

EBTS System Manual - Vol 2 Contents

List of Tables

Table 8-3
Table 8-4
Table 8-5
Table 8-6
Table 8-7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23

70W, 800 MHz PA Transmitter Parameters.............................................................................. 10-17

60W, 900 MHz PA – CLN1355 Transmitter Parameters.......................................................... 10-21

40W, 1500 MHz PA Transmitter Parameters............................................................................ 10-25

Base Radio Backplane Connectors............................................................................................ 10-35

Color Codes for RF Connections on Rear of Base Radio.......................................................... 10-37

P1 Connector Pin-outs ............................................................................................................... 10-38

P1 Connector Pin-outs ............................................................................................................... 10-38

P2 Connector Pin-outs ............................................................................................................... 10-39

P3 Connector Pin-outs ............................................................................................................... 10-39

P2 Connector Pin-outs ............................................................................................................... 10-40

P3 Connector Pin-outs ............................................................................................................... 10-40

P5 Connector Pin-outs ............................................................................................................... 10-40

P6 Connector Pin-outs ............................................................................................................... 10-41

P7 Connector Pin-outs ............................................................................................................... 10-42

P8 Connector Pin-outs ............................................................................................................... 10-43

P13 Connector Pin-outs ............................................................................................................. 10-43

SMA Connectors- Receivers...................................................................................................... 10-43

Blind Mates - BRC..................................................................................................................... 10-43

Blind Mates - Exciter................................................................................................................. 10-43

Blind Mates - PA ....................................................................................................................... 10-44

P9 Connector Pin-outs ............................................................................................................... 10-44

Table 8-24 Base Radio Signal Descriptions................................................................................................. 10-47

Table 9-1
Table 9-2
Table 9-3
Table 9-9

Recommended Test Equipment................................................................................................... 11-2

QUAD BRTransmitter Parameters............................................................................................ 11-14

Backplane Connectors ............................................................................................................... 11-22

RX1 P2 Pinout, Signal and Power............................................................................................. 11-26

Table 9-10 RX1 P3 Pinout, RF Input and Output Connection..................................................................... 11-26

Table 9-11 RX2 P4 Pinout, Signal and Power............................................................................................. 11-27

Table 9-12 RX2 P5 Pinout, RF Input and Output Connection..................................................................... 11-27

Table 9-13 RX3 P6 Pinout, Signal and Power............................................................................................. 11-28

Table 9-14 RX3 P7 Pinout, RF Input and Output Connection..................................................................... 11-28

Table 9-15 RX4 P8 Pinout, Signal and Power............................................................................................. 11-29

Table 9-16 RX4 P9 Pinout, RF Input and Output Connection..................................................................... 11-29

Table 9-17 PA P10 Pinout, Signal and Power.............................................................................................. 11-30

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68P81099E10-D 4/1/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

Foreword

Foreword

About This Manual

Volume 2 of the Enhanced Base Transceiver System (EBTS) manual, Base Radios ,
provides the experienced service technician with an overview of the EBTS
operation and functions, and contains information regarding the 800 MHz,
900 MHz, or 1500 MHz base radios.

The EBTS System has three major components:

❐

integrated Site Controller (iSC)

❐

Base Radios (BRs)

❐

RF Distribution System (RFDS)

Installation and testing is described in Volume 1, System Installation and Testing ,
and RFDS are described in Volume 3, RF Distribution Systems (RFDS) . Detailed
information about the iSC is contained in the iSC Supplement Manual,

68P81098E05 .

Target Audience

The information in this manual is current as of the printing date. If changes to
this manual occur after the printing date, they will be documented and issued as
Schaumburg Manual Revisions (SMRs).

The target audience of this document includes Þeld service technicians
responsible for installing, maintaining, and troubleshooting the EBTS.

In keeping with MotorolaÕs Þeld replaceable unit (FRU) philosophy, this manual
provides sufÞcient functional information to the FRU level. Please refer to the
appropriate section of this manual for removal and replacement instructions.

68P81099E10-D 4/1/2000

ix

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

Foreword

Maintenance Philosophy

The EBTS has been designed using a Field Replaceable Unit (FRU) maintenance
concept. To minimize system down time, faulty FRUs may be quickly and easily
replaced with replacement FRUs. This helps to restore normal system operation
quickly.

Due to the high percentage of surface mount components and multi-layer circuit
boards, Þeld repair is discouraged. Faulty or suspectFRUs should be returned to
the Motorola Customer Support Center for further troubleshooting and repair.

Each FRU has a bar code label attached to its front panel. This label identiÞes a
sequential serial number for the FRU. Log this number whenever contacting the
Motorola Customer Support Center. For complete information on ordering
replacement FRUs, or instructions on how to return faulty FRUs for repair,
contact:

Nippon Motorola LTD. OR Motorola Customer Support Center
Tokyo Service Center 1311 East Algonquin Road
044-366-8860 Schaumburg, Illinois 60196

[phone] or [phone]

Technical Support Service

Motorola provides technical support services for installation, optimization, and
maintenance of its Þxed network equipment. Before calling the Motorola
Customer Support Center, please note the following information:

❐
❐
❐
❐

Where the system is located.

The date the system was put into service.

A brief description of problem.

Any other unusual circumstances.

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68P81099E10-D 4/1/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

General Safety Information

General Safety Information

The United States Department of Labor, through the provisions of the
Occupational Safety and Health Act of 1970 (OSHA), has established an
electromagnetic energy safety standard which applies to the use of this
equipment.

Proper use of this radio will result in exposure below the OSHA limit, however,
this applies only within the United States of America. Obey all electromagnetic
energy safety standards that have been established by your local governing body.

The following precautions are always recommended:

❐

DO NOT operate the transmitter of a mobile radio when someone outside
the vehicle is within two feet (0.6 meter) of the antenna.

DO NOT operate the transmitter of a Þxed radio (base station, microwave

❐

and rural telephone rf equipment) or marine radio when someone is within
two feet (0.6 meter) of the antenna.

❐

DO NOT operate the transmitter of any radio unless all RF connectors are
secure and any open connectors are properly terminated.

❐

DO NOT operate this equipment near electrical caps or in an explosive
atmosphere.

All equipment must be properly grounded according to Motorola installation
instructions for safe operation.

All equipment should be serviced only by a qualiÞed technician.

Refer to the appropriate section of the product service manual for additional
pertinent safety information.

!

WARNING

POSSIBLE ELECTRICAL SHOCK HAZARD. BEFORE
ATTEMPTING REMOVAL OR INSTALLATION OF
EQUIPMENT, MAKE SURE THE PRIMARY POWER AND
BATTERIES ARE DISCONNECTED.

Refer to publication 68P81106E84, Safe Handling of CMOS Integrated Circuit
Devices, for more detailed information on this subject.

68P81099E10-D 4/1/2000

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68P81099E10-D 4/1/2000

1 800/900/1500 MHz

Base Radio Overview

Overview

This section provides technical information for the 800/900/1500 MHz Base
Radio (BR). Table 1-1 describes covered topics.

Table 1-1

Chapter

Single Carrier Base Radio Overview 1-3 Provides an overview of the BR, performance speciÞcations,

QUAD Channel Base Radio Overview 1-8 Provides an overview of the QUAD Channel BR,

Base Radio Controller 2-1 Describes the functions and characteristics of the Base Radio

Exciter 3-1 Describes the functions and characteristics of the

Power AmpliÞer 4-1 Describes the functions and characteristics of Single Channel

DC Power Supply 5-21 Describes functions and characteristics of DC Power Supply

AC Power Supply 6-33 Describes the functions and characteristics of the AC Power

Chapter T opics

Page Description

and overall theory of operation

performance speciÞcations, and overall theory of operation

Controller (BRC) module

Exciter module

and QUAD Channel Power AmpliÞer modules

modules for Single Channel andQUAD Channel Base Radios

Supply module

68P81095E02-D 11/9/2000-UP

Network Solutions Sector

1301 E. Algonquin Road, Schaumburg, IL 60196

1-1

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

Table 1-1

Chapter

Receiver 7-39 Describes the functions and characteristics of the 800 MHz

Troubleshooting Single Channel Base Radios 8-1 Provides troubleshooting procedures, replacement

Base Radio/Base Radio FRU Replacement Procedures 8-5 Provides instructions and guidelines for Single Channel Base

Station VeriÞcation Procedures 8-9 Provides procedures for verifying station operation

Single Channel BR Backplane 8-35 DeÞnes the pinouts, connectors, and signal names for the

Troubleshooting QUAD Channel Base Radios 9-1 Provides troubleshooting procedures, replacement

Base Radio/Base Radio FRU Replacement Procedures 9-5 Provides instructions and guidelines for QUAD Channel

Station VeriÞcation Procedures 9-10 Provides procedures for verifying station operation

QUAD Channel BR Backplane 9-22 DeÞnes the pinouts, connectors, and signal names for the

Acronyms A-39 DeÞnes technical terms that appear in this manual

Chapter T opics

Page Description

and 900 MHz 3X Receiver modules

procedures, and receiver/transmitter veriÞcation tests for
Single Channel Base Radios

Radio and Base Radio FRU Replacement

following Single Channel Base Radio repairs

Single Channel BR backplane

procedures, and receiver/transmitter veriÞcation tests for
QUAD Channel base radios

Base Radio and Base Radio FRU Replacement

following QUAD Channel Base Radio repairs

QUAD Channel BR backplane

NOTE

The Þrst section covers the 800 MHz, 900 MHz and
1500 MHz versions of the Base Radio (BR).
Generalinformation for all versions appears here. The
text notes information speciÞc to the 800 MHz , 900
MHz or 1500 MHz BR.

NOTE

For QUAD Channel BR use, all Single Carrier BR
modules have undergone a redesign process. Single
Carrier BR modules are incompatible with the QUAD
Channel BR. QUAD Channel BR modules are
incompatible with the Single Carrier BR.

Do not try to insert QUAD Channel BR modules into a
Single Carrier BR or Single Carrier BR modules into a
QUAD Channel BR.

1-2

68P81095E02-D 11/9/2000

EBTS282
101497JNM

CONTROL

RESETBR PS EX PA CTL R1 R2 R3

STATUS

POWER AMPLIFIER

POWER SUPPLY

3X RECEIVER

INSERT ONLY IN SLOT RX2 WITH BACKPLANE 0183625X

EXCITER

Figure:1-1

Base Radio (Typical)

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

Single Carrier Base Radio Overview

Single Carrier Base Radio Overview

The BR provides reliable digital BR capabilities in a compact software-controlled
design. Increased channel capacity is provided through voice compression
techniques and Time Division Multiplexing (TDM).

The BR contains the Þve FRUs listed below:

❐

Base Radio Controller (BRC)

❐

Exciter

❐

Power AmpliÞer

❐

Power Supply (AC/DC)

❐

Receiver

The modular design of the BR also offers increased shielding and provides easy
handling. All FRUs connect to the backplane through blindmate connectors.
Figure 1-1 shows the front view of the BR.

68P81095E02-D 11/9/2000

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800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

Single Carrier Base Radio Overview

Controls and Indicators

The Power Supply and BRC contain controls and indicators that provide a means
for monitoring various status and operating conditions of the BR, and also aid in
fault isolation. The controls and indicators for both modules are discussed in the
Power Supply and BRC sections of this chapter.

The Power Supply contains two front panel indicators; the BRC contains eight
front panel indicators. The Power Supply contains a power switch used to apply
power to the BR. The BRC contains a RESET switch used to reset the BR.

Performance Specifications

General Specifications

Table 1-2 lists general speciÞcations for the BR.

Table 1-2

Dimensions:

Operating Temperature 32û to 104û F (0û to 40û C)

Storage Temperature -22û to 140û F (-30û to 60û C)

Rx Frequency Range:

Tx Frequency Range:

Tx Ð Rx Spacing:

Channel Spacing 25 kHz

Frequency Generation Synthesized

Digital Modulation M-16QAM

Power Supply Inputs:

Diversity Branches Up to 3

BR General Specifications

Specification

Height

Width

Depth

Weight

800 MHz iDEN

900 MHz iDEN

1500 MHz iDEN

800 MHz iDEN

900 MHz iDEN

1500 MHz iDEN

800 MHz iDEN

900 MHz iDEN

1500 MHz iDEN

Vac (option)

Vdc

Value or Range

5 EIA Rack Units (RU)

19" (482.6 mm)

16.75" (425 mm)

76 lbs. (34 kg)

806 - 821 MHz

896 - 901 MHz

1453 - 1465 MHz

851 - 866 MHz

935 - 940 MHz

1501 - 1513 MHz

45 MHz

39 MHz

48 MHz

90 - 140/180 - 230 Vac (@ 47 - 63 Hz)

-48 Vdc (41 - 60 Vdc)

1-4

68P81095E02-D 11/9/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

Single Carrier Base Radio Overview

Transmit Specifications

Table 1-3 lists transmit speciÞcations for the BR.

Table 1-3

Transmit Specifications

Specification Value or Range

Average Power Output:

(800 MHz) 40 W PA

(800 MHz) 70 W PA

(900 MHz) 60 W PA

(1500 MHz) 40 W PA

Transmit Bit Error Rate (BER) 0.01%

Occupied Bandwidth 18.5 kHz

Frequency Stability * 1.5 ppm

RF Input Impedance 50

FCC Designation (FCC Rule Part 90):

(800 MHz) 40 W PA

(800 MHz) 70 W PA

(900 MHz) 60 W PA

* Stability without site reference connected to station.

2 - 40 W

4 - 70 W

5 - 60 W

10 - 40 W

ABZ89FC5772

ABZ89FC5763

ABZ89FC5791

Receive Specifications

Table 1-4 lists the receive speciÞcations.

Ω

(nom.)

Table 1-4

Receive Specifications

Specification

Static Sensitivity :

800 MHz BR

900 MHz BR

1500 MHz BR

BER Floor (BER = 0.01%)

IF Frequencies

1st IF (All bands):

2nd IF:

800/900 MHz

1500 MHz

Frequency Stability * 1.5 ppm

RF Input Impedance 50

FCC Designation (FCC Rule Part 15):

800 MHz BR

900 MHz BR

† Measurement referenced from single receiver input port of BR.
* Stability without site reference connected to station.

-108 dBm (BER = 8%)

-109 dBm (BER = 10%)

-98 dBm (BER = 1%)

-80 dBm

≥

73.35 MHz (1st IF)

450 kHz (2nd IF)

455 kHz (2nd IF)

ABZ89FR5762

ABZ89FR5792

Ω

Value or Range

(nom.)

68P81095E02-D 11/9/2000

1-5

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

Single Carrier Base Radio Overview

NOTE

FCC Compliance Notice : The Base Radio (BR) is FCC

Compliant only when used in conjunction with
Motorola supplied RF Distribution Systems. Motorola
does not recommend that this BR be used without a
Motorola approved RF Distribution System. It is the
customerÕs responsibility to Þle for FCC approval if
the BR is used with a non-Motorola supplied RF
Distribution System.

Theory of Operation

The BR operates in conjunction with other site controllers and equipment that are
properly terminated. The following description assumes such a conÞguration.
Figures 1-3 and 1-4 show an overall block diagram of the BR.

Power is applied to the AC Power or DC Power inputs located on the BR
backplane. The DC Power input is connected if -48 Vdc or batteries are used in
the site. The AC Power input is used when 120/240 Vac service is used as a
power source within the site.

Power is applied to the BR by setting the Power Supply power switch to the on
position. Upon power-up, the BR performs self-diagnostic tests to ensure the
integrity of the unit. These tests are primarily conÞned to the BRC and include
memory and Ethernet veriÞcation routines.

After the self-diagnostic tests are complete, the BR reports any alarm conditions
present on any of its modules to the site controller via Ethernet. Alarm conditions
may also be veriÞed locally using service computer and the STATUS port located
on the front of the BRC.

The software resident in EPROM on the BRC registers the BR with the site
controller via Ethernet. Once registered, the BR software is downloaded via
Ethernet and is executed from RAM. Operating parameters for the BR are
included in this download. This software allows the BR to perform call
processing functions.

The BR operates in a TDMA (Time Division Multiple Access) mode. This mode,
combined with voice compression techniques, provides an increased channel
capacity ratio of as much as 6 to 1. Both the receive and transmit signals of the BR
are divided into 6 individual time slots. Each receive slot has a corresponding
transmit slot; this pair of slots comprises a logical RF channel.

1-6

The BR uses diversity reception for increased coverage area and improved
quality. The Receiver module within the BR contains up to three receivers. Two
Receivers are used with two-branch diversity sites, and three Receivers are used
with three-branch diversity sites.

68P81095E02-D 11/9/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

Single Carrier Base Radio Overview

All Receivers within a given BR are programmed to the same receive frequency.
The signals from each receiver are fed to the BRC where a diversity combining
algorithm is performed on the signals. The resultant signal is processed for error
correction and then sent to the site controller via Ethernet with the appropriate
control information regarding its destination.

The transmit section of the BR is comprised of two separate FRUs, the Exciter and
Power AmpliÞer (PA). Several PA FRUs are available, covering different
applications and power levels; these are individually discussed as applicable in
later subsections.

The Exciter processes the information to transmit from the BRC in the proper
modulation format. This low level signal is sent to the PA where it is ampliÞed to
the desired output power level. The PA is a continuous keyed linear ampliÞer. A
power control routine monitors the output power of the BR and adjusts it as
necessary to maintain the proper output level.

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800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

QUAD Channel Base Radio Overview

QUAD Channel Base Radio Overview

The QUAD Channel BR provides reliable, digital BR capabilities in a compact,
software-controlled design. Voice compression techniques, time division
multiplexing (TDM) and multi-carrier operation provide increased channel
capacity.

The QUAD Channel BR contains the Þve FRUs listed below:

QUAD Channel EX / Cntl

❐

QUAD Channel Power AmpliÞer

❐

QUAD Channel Power Supply (DC)

❐

QUAD Channel Receiver (qty 4)

❐

The modular design of the QUAD Channel BR also offers increased shielding and
provides easy handling. All FRUs connect to the backplane through blindmate
connectors. Figure 1-2 shows the front view of the BR.

1-8

Figure:1-2

QUAD Channel Base Radio (Typical)

68P81095E02-D 11/9/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

QUAD Channel Base Radio Overview

Controls and Indicators

Power Supply and EX / CNTL controls and indicators monitor BR status and
operating conditions, and also aid in fault isolation. The Power Supply and EX /
CNTL sections of this chapter discuss controls and indicators for both modules.

The Power Supply has two front panel indicators. The EX / CNTL has twelve
front panel indicators. The Power Supply power switch applies power to the BR.
The EX / CNTL RESET switch resets the BR.

Performance Specifications

General Specifications

Table 1-5 lists general speciÞcations for the BR.

Table 1-5

Dimensions:

Operating Temperature 32û to 104û F (0û to 40û C)

Storage Temperature -22û to 140û F (-30û to 60û C)

Rx Frequency Range:

Tx Frequency Range:

Tx Ð Rx Spacing:

Carrier Spacing 25 kHz

Carrier Capacity

Frequency Generation Synthesized

Digital Modulation QPSK, M-16QAM, and M-64QAM

Power Supply Inputs:

Diversity Branches Up to 3

QUAD Channel BR General Specifications

Specification

Height

Width

Depth

Weight

800 MHz iDEN 806 - 825 MHz

800 MHz iDEN 851 - 870 MHz

800 MHz iDEN 45 MHz

a

Vdc -48 Vdc (41 - 60 Vdc)

5 EIA Rack Units (RU)

19" (482.6 mm)

16.75" (425 mm)

91 lbs. (40 kg)

1, 2, 3 or 4

Value or Range

a. Multi-carrier operation must utilize adjacent, contiguous RF carriers.

68P81095E02-D 11/9/2000

1-9

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

QUAD Channel Base Radio Overview

Transmit Specifications

Table 1-6 lists the BR transmit speciÞcations.

Table 1-6

Transmit Specifications

Specification Value or Range

Average Power Output:

(800 MHz)Single Carrier

(800 MHz) Dual Carrier

(800 MHz) Triple Carrier

(800 MHz) QUAD Channel

Transmit Bit Error Rate (BER) 0.01%

Occupied Bandwidth 18.5 kHz

Frequency Stability * 1.5 ppm

RF Input Impedance 50

FCC Designation (FCC Rule Part 90):

(800 MHz) QUAD Channel PA ABZ89FC5794

* Transmit frequency stability locks to an external site refernce, which controls ultimate frequency stability to a
level of 50 ppb.

Total PA Per Carrier

5 - 52 W 5 - 52 W

5 - 52 W 2.5 - 26 W

5 - 48 W 1.7 - 16 W

5 - 42 W

Ω

(nom.)

Receive Specifications

Table 1-7 lists the receive speciÞcations.

Table 1-7

Static Sensitivity :

BER Floor (BER = 0.01%)

IF Frequencies

Frequency Stability * 1.5 ppm

RF Input Impedance 50

FCC Designation (FCC Rule Part 15):

† Measurement referenced from single receiver input port of BR.
* Stability without site reference connected to station. Receive frequency stability locks to an external site

refernce, which controls ultimate frequency stability to a level of 50 ppb.

Receive Specifications

Specification

800 MHz BR -108 dBm (BER = 8%)

≥

-80 dBm

1st IF (All bands):

2nd IF:

800 MHz BR ABZ89FR5793

73.35 MHz (1st IF)

450 kHz (2nd IF)

Ω

Value or Range

(nom.)

1-10

68P81095E02-D 11/9/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

QUAD Channel Base Radio Overview

NOTE

FCC Compliance Notice : The Base Radio (BR) is FCC

Compliant only when used with Motorola-supplied
RF Distribution Systems. Motorola does not
recommend using this BR without a Motorola­approved RF Distribution System. If customer uses
the BR with a non-Motorola supplied RF Distribution
System, the customer is responsible for Þling for FCC
approval.

Theory of Operation

The QUAD Channel BR operates together with other site controllers and
equipment that are properly terminated. The following description assumes such
a conÞguration. Figures 1-5 show an overall block diagram of the QUAD Channel
BR.

Power is applied to the DC Power inputs located on the QUAD Channel BR
backplane. The DC Power input is connected if -48 Vdc or batteries are used in the
site.

Power is applied to the BR by setting the Power Supply power switch to the on
position. Upon power-up, the QUAD Channel BR performs self-diagnostic tests
to ensure the integrity of the unit. These tests, which include memory and
Ethernet veriÞcation routines, primarily examine the EX / CN TL.

After completing self-diagnostic tests, the QUAD Channel BR reports alarm
conditions on any of its modules to the site controller via Ethernet. Alarm
conditions may also be veriÞed locally. Local veriÞcation involves using the
service computer and the STATUS port located on the front of the QUAD Channel
EX / CNTL.

The software resident in FLASH on the EX / CNTL registers the BR with the site
controller via Ethernet. After BR registration on initial power-up, the BR software
downloads via Ethernet and executes from RAM. The download includes
operating parameters for the QUAD Channel BR. These parameters allow the
QUAD Channel BR to perform call processing functions.

68P81095E02-D 11/9/2000

After software downloads to the BR via Ethernet, FLASH memory stores the
software object. Upon future power-ups, the software object in FLASH loads into
RAM for execution.

The BR operates in a TDMA (Time Division Multiple Access) mode. This mode,
combined with voice compression techniques, increases channel capacity by a
ratio of as much as six to one. TDMA divides both the receive and transmit
signals of the BR into six individual time slots. Each receive slot has a
corresponding transmit slot. This pair of slots comprises a logical RF channel.

1-11

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

QUAD Channel Base Radio Overview

The BR uses diversity reception for increased coverage area and improved
quality. The Receiver modules within the QUAD Channel BR contain three
receiver paths. Two-branch diversity sites use two Receiver paths, and
three-branch diversity sites use three Receiver paths.

All Receiver paths within a given Receiver module are programmed to the same
receive frequency. Signals from each receiver arrive at the EX / CNTL module.
This module performs a diversity combining algorithm on the signals. The
resultant signal undergoes an error-correction process. Then, via Ethernet, the site
controller acquires the signal, along with control information about signal
destination.

Two separate FRUs comprise the transmit section of the QUAD Channel BR.
These are the Exciter portion of the EX / CNTL and the Power AmpliÞer (PA).
The Exciter processes commands from the CNTL, assuring transmission in the
proper modulation format. Then the low-level signal enters the PA. The PA
ampliÞes this signal to the desired output power level. The PA is a continuously
keyed linear ampliÞer. A power control routine monitors the output power of the
BR. The routine adjusts the power as necessary to maintain the proper output
level.

1-12

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EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

QUAD Channel Base Radio Overview

68P81095E02-D 11/9/2000

1-13

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

QUAD Channel Base Radio Overview

This Page Intentionally

Left Blank

1-14

68P81095E02-D 11/9/2000

POWER AMPLIFIER MODULE

TO/FROM

ETHERNET

BASE RADIO CONTROLLER
MODULE

EXCITER MODULE

DC POWER SUPPLY MODULE

SERIAL BUS

TO/FROM

STATUS

PORT

(RS-232)

TO/FROM

RS-232 PORT

(ON BACKPLANE)

16.8 MHZ

5 MHZ

SPI BUS

5 MHZ

EXTERNAL

REFERENCE

FINAL

LINEAR

AMPS

SPLITTER

LINEAR
DRIVER

ADDRESS DECODE,

MEMORY , A/D CONVERTER

ADDRESS DECODE,

MEMORY , A/D CONVERTER

FROM

RFDS

(RECEIVER

ANTENNA)

#3

3X RECEIVER MODULE

MIXER

DSP BUS

LPF/

PRESELECT/

PREAMP/

IMAGE FILTER

VCO/

SYNTH

ADDRESS DECODE,

MEMORY,

A/D CONVERTER

NON-VOLATILE

MEMORY

(EEPROM,

EPROM)

DRAM

SRAM

HOST

µµ

P

ETHERNET
INTERFACE

HOST
GLUE

ASIC

TRANSMIT

DSP

RECEIVE

DSP

SCI

SSI

PLL/
VCO

SPI BUS

2.1 MHZ

COMBINER

LINEAR RF
AMPLIFIER

EXCITER

IC

IF IN IF OUT

TRANLIN

IC

INPUT FILTER

BOARD

CLOCK

GENERATOR

CIRCUITRY

START-UP
INVERTER

CIRCUITRY

133 KHZ

267 KHZ

+14.2 V

INVERTER

CIRCUITRY

133 KHZ

DIAGNOSTICS

CIRCUITRY

+14.2 VDC
TO BACKPLANE

+5 VDC
TO BACKPLANE

+28 VDC
TO BACKPLANE

EXTERNAL
DC INPUT
41 - 72 VDC

RF OUT

SPI BUS

SPI BUS

SPI BUS

SPI BUS

2.1 MHZ

SPI BUS

DATA/CLOCK

DATA/CLOCK

RF IN

RF OUT

RF FEEDBACK

FEEDBACK IN

DIGITAL

ATTEN.

CIRCUIT

AGC

SPI BUS

RF IN

CUSTOM

RECEIVER

IC

EBTS284
120497JNM

TO

RFDS

(TRANSMIT

ANTENNA)

MAIN INVERTER

CIRCUITRY

+5 V

INVERTER

CIRCUITRY

TISIC

FROM

RFDS
(RECEIVER
ANTENNA)

#2

MIXER

DSP BUS

LPF/

PRESELECT/

PREAMP/

IMAGE FILTER

RF IN

DIGITAL

ATTEN.

CIRCUIT

CUSTOM

RECEIVER

IC

FROM

RFDS

(RECEIVER

ANTENNA)

#1

MIXER

DSP BUS

LPF/

PRESELECT/

PREAMP/

IMAGE FILTER

RF IN

DIGITAL

ATTEN.

CIRCUIT

CUSTOM

RECEIVER

IC

BAND

PASS

FILTER

BAND

PASS

FILTER

BAND

PASS

FILTER

IF

AMP

IF

AMP

IF

AMP

BAND

PASS

FILTER

BAND

PASS

FILTER

BAND

PASS

FILTER

3-WAY

SPLITTER

NOTES:

1. 2-Branch systems must have a 50Ω load (P/N 5882106P03) installed on Antenna Port #3.

2. Set the RX_FRU_CONFIG parameter as follows:
2-Branch Systems: 12
3-Branch Systems: 123

3. Where two frequencies are given, frequency without parentheses applies to 800 MHz BR only and frequency with parentheses applies to 900 MHz BR only.

970 MHZ

(1025 MHZ)

VCO/SYNTH

FREQUENCY

DOUBLER

237 MHZ

(180.6 MHZ)

VCO

Figure:1-3

800/900 MHz Base Radio Functional Block Diagram

800 MHz And 900 MHz

Base Radio

Functional Block Diagram

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

Base Radio Overview

68P81095E02-D 11/9/2000

1-15

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

Base Radio Overview

1500 MHz Base Radio

RECEIVE

ANTENNA

5 MHZ

EXTERNAL

REFERENCE

TO/FROM

ETHERNET

TO/FROM

SERVICE

COMPUTER

TO/FROM

SYNC MODEM

TRANSMIT

ANTENNA

RF IN

RECEIVER MODULE

RECEIVER MODULE

RECEIVER MODULE

TLN3427

PRESELECT/

PERAMP/

IMAGE FILTER

SYNTH/

VCO

LPF/

2X INJECTION

AMP

MIXER

BASE RADIO CONTROLLER
MODULE

CLN1469/TLN3425

ETHERNET

INTERFACE

NON-VOLATILE

HOST

µ

P

MEMORY

(EEPROM, SRAM,

EPROM)

BAND
PASS

FILTER

SPI BUS

SPI BUS

HOST

ASIC

IF

AMP

DRAM

BAND

PASS

FILTER

SPI BUS

CORRECTION SIGNALS

DIGITAL

ATTEN.

CIRCUIT

ADDRESS DECODE,

MEMORY,

A/D CONVERTER

2.1 MHZ

SPI BUS

5 MHZ

PLL/
VCO

TRANSMIT

DSP

SSI

SCI

RECEIVE

DSP

ERROR

CORRECTION

DSP

(TLN3425 ONLY)

CUSTOM

RECEIVER

IC

16.8 MHZ

Functional Block Diagram

POWER SUPPLY MODULE

TLN3429/TLN3339/TLN3338

DSP BUS

SPI BUS

BATTERY CHARGING/

REVERT CIRCUITRY

*

AGC

SERIAL BUS

DIAGNOSTICS

CIRCUITRY

DATA/CLOCK

DSP

GLUE

ASIC

SPI BUS

EXCITER MODULE

MAIN INVERTER

GENERATOR

CIRCUITRY

SPI BUS

CIRCUITRY

CLOCK

267 KHZ

133 KHZ

INPUT FILTER

BOARD

133 KHZ (TLN3338)
67 KHZ (TLN3429/

START-UP
INVERTER

CIRCUITRY

+14.2 V

INVERTER

CIRCUITRY

+5 V

INVERTER

CIRCUITRY

TLN3339)

TLN3428

2.1 MHZ

SPI BUS

DATA/CLOCK

TRANLIN

IC

IF IN IF OUT

700 MHZ

VCO/SYNTH

FREQUENCY

DOUBLER

236 MHZ

VCO

ADDRESS DECODE,

MEMORY, A/D CONVERTER

AC INPUT
47 - 63 HZ
90V/264V

+14.2 VDC
TO BACKPLANE

+5 VDC
TO BACKPLANE

+28 VDC
TO BACKPLANE

TO/FROM STORAGE
BATTERY

POWER AMPLIFIER MODULE

TLN3426

RF OUT

COMBINER

FINAL

LINEAR

AMP

SPLITTER

FINAL

LINEAR

AMP

Battery Charging/Revert Circuitry is contained only in the TLN3429 and TLN3339 AC Power Supplies.

*

Figure:1-4

1500 MHz Base Radio Functional Block Diagram

ADDRESS DECODE,

MEMORY, A/D CONVERTER

1-16

LINEAR
DRIVER

RF IN

SPI BUS

RF FEEDBACK

LINEAR RF
AMPLIFIER

AGC

CIRCUIT

EXCITER

FEEDBACK IN

RF OUT

IC

68P81095E02-D 11/9/2000

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

Base Radio Overview

ABACUS

RECEIVER

RX INTERFACE,

ADDRESS DECODE.

MEMORY, DIAGNOSTICS

IC

ABACUS

RECEIVER

IC

ABACUS

RECEIVER

IC

Host SPI

EXCITER-BASE RADIO
CONTROLLER

STATUS

PORT

RS-232

ETHERNET

5 MHZ

EXTERNAL

REFERENCE

HOST

u’P

ETHERNET
INTERFACE

PLL/VCOs

BASE RADIO
CONTROLLER

DC POWER SUPPLY MODULE

EXTERNAL
DC INPUT
41 - 60 VDC

INPUT FILTER

START-UP
INVERTER

CIRCUITRY

Figure:1-5

IF FILTER

AMP, AGC

IF FILTER

AMP, AGC

VCO SYNTH

SPLITTER

IF FILTER

AMP, AGC

MIXER

MIXER

MIXER

RX4 DATA

LPF, AMP,

FILTER

LPF, AMP,

FILTER

LPF, AMP,

FILTER

RECEIVER 4

PREAMPLIFIER

SPLITTER
/ BYPASS

RX3 DATA

16.8MHz

SDRAM

RECEIVE

DSP

BUFFERS

IO LATCHES

FLASH

EEPROM

16.8MHz

48MHz

Host SPI

ADDRESS DECODE,

MEMORY, ADC

133 KHZ

800 MHz QUAD Channel Base Radio Functional Block
Diagram

Exciter

CLOCK

GENERATOR

LINEAR RF
AMPLIFIER

Main Converter

267 KHZ

133 KHZ

TISIC

TRANSMIT

DSP

ODCT

RF IN

Rx1&2

Rx3&4

RX SPI

1PPS & SLOT TIMING

TX RECLOCK

Tx_I Tx_Q

I
Q

RF FEEDBACK

14.2 V

CONVERTER

DAC

3.3 V

CONVERTER

RX2 DATA

RX1 DATA

RECEIVE

DSP

2.4MHz

VCOs/Synths

RECEIVER 3

RF IN

FROM RFDS
(BRANCH 3)

PREAMPLIFIER

SPLITTER
/ BYPASS

QUAD RX IN DISTRIBUTION

SPI BUS

RECEIVER 2

RF IN

FROM RFDS

(BRANCH 2)

SPI BUS

RF IN

FROM RFDS

(BRANCH 1)

+28 VDC
TO BACKPLANE

+14.2 VDC
TO BACKPLANE

+3.3 VDC
TO BACKPLANE

SPI BUS

SPI BUS

PREAMPLIFIER

SPLITTER
/ BYPASS

RECEIVER 1

PREAMPLIFIER

SPLITTER
/ BYPASS

LPF, AMP,

FILTER

LPF, AMP,

FILTER

LPF, AMP,

FILTER

LPF, AMP,

FILTER

LPF, AMP,

FILTER

LPF, AMP,

FILTER

LPF, AMP,

FILTER

LPF, AMP,

FILTER

LPF, AMP,

FILTER

ADDRESS DECODE,

MEMORY, ADC

LINEAR
DRIVER

MIXER

MIXER

MIXER

MIXER

MIXER

MIXER

MIXER

MIXER

MIXER

SPLITTER

IF FILTER

AMP, AGC

IF FILTER

AMP, AGC

VCO SYNTH

SPLITTER

IF FILTER

AMP, AGC

IF FILTER

AMP, AGC

IF FILTER

AMP, AGC

VCO SYNTH

SPLITTER

IF FILTER

AMP, AGC

ABACUS

RECEIVER

IC

ABACUS

RECEIVER

IC

ABACUS

RECEIVER

IC

ABACUS

RECEIVER

IC

ABACUS

RECEIVER

IC

ABACUS

RECEIVER

IC

MEMORY, DIAGNOSTICS

16.8MHz

IF FILTER

AMP, AGC

IF FILTER

AMP, AGC

VCO SYNTH

SPLITTER

IF FILTER

AMP, AGC

ABACUS

RECEIVER

IC

ABACUS

RECEIVER

IC

ABACUS

RECEIVER

IC

MEMORY, DIAGNOSTICS

POWER AMPLIFIER MODULE

COMBINER

FINAL

LINEAR

AMPS

RX INTERFACE,

ADDRESS DECODE.

RX INTERFACE,

ADDRESS DECODE.

MEMORY, DIAGNOSTICS

RX INTERFACE,

ADDRESS DECODE.

RF OUT

TO RFDS

(TX ANTENNA)

1-17

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Base Radio Overview

1-18

68P81095E02-D 11/9/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

2 Base Radio Controller

Overview

This section provides technical information for the Base Radio Controller (BRC).
Table 2-1 describes covered topics.

Table 2-1

Chapter

800/900/1500 MHz Base Radio Controller Ð
CLN1469; 1500 MHz MC1 Base Radio Controller Ð
TLN3425

800 MHz QUAD Channel
Base Radio Controller

Single Channel Base Radio Controller 2-25 Functional Block Diagram for the Single Channel Base Radio

QUAD Channel Base Radio Controller 2-29 Functional Block Diagram for the QUAD Channel Base

Chapter T opics

Page Description

2-2 Describes the functions and characteristics of the Base Radio

Controller (BRC) module for the single channel Base Radio
(BR).

2-13 Describes the functions and characteristics of the Base Radio

Controller (BRC) module for the QUAD channel Base Radio
(BR).

Controller (BRC)

Radio Controller (BRC)

FRU Number to Kit Number Cross Reference

Base Radio Controller (BRC) Field Replaceable Units (FRUs) are available for the
iDEN EBTS. The FRU contains the BRC kit and required packaging. Table 2-2
provides a cross reference between BRC FRU numbers and kit numbers.

Table 2-2

Description

Single Channel Base Radio Controller
(800/ 900/ 1500 MHz)

Single Channel Base Radio Controller
(1500 MHz MCI)

QUAD Channel Exciter/Base Radio Controller
(800 MHz)

FRU Number to Kit Number Cross Referece

FRU Number Kit Number

TLN3334 CLN1469

TLN3425 CLN1472

CLN1497 CLF1560

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800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

800/900/1500 MHz Base Radio Controller – CLN1469; 1500 MHz MC1 Base Radio Controller – TLN3425

800/900/1500 MHz Base Radio Controller – CLN1469;
1500 MHz MC1 Base Radio Controller – TLN3425

Overview

The Base Radio Controller (BRC) provides signal processing and operational
control for other Base Radio modules. Figure 2-1 shows a top view of the BRC
with the cover removed. The BRC module consists of two printed circuit boards
(BRC board and LED/display board), a slide-in housing, and associated
hardware.

The BRC memory contains the operating software and codeplug. The software
deÞnes operating parameters for the BR, such as output power and operating
frequency.

The BRC interconnects to the Base Radio backplane using one 96-pin, DIN
connector and one blindmate, RF connector. Two Torx screws secure the BRC to
the Base Radio chassis.

NOTE

BRC Modules with board level kit number CLN6989
require System Software Release version SR 3.3 or
higher. Using these modules with System Software
versions older than 3.3 causes a PENDULUM lock
error. The Base Radio will not function.

Two BRC modules serve as the main controller for the 1500 MHz Base Radio. The
standard model is the same module that the 800/900 MHz Base Radio uses.
Model TLN3425 contains additional Digital Signal Processing power. This
additional power supports applications that require a modiÞed error correction
routine (available for speciÞc customers only). Figure 2-2 shows a top view of the
BRC (model TLN3425) with the cover removed.

2-2

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EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

800/900/1500 MHz Base Radio Controller – CLN1469; 1500 MHz MC1 Base Radio Controller – TLN3425

Figure:2-1

Base Radio Controller, version CLN1469 (with cover removed)

68P81095E02-D 12/6/2000

Figure:2-2

1.5GHZ-A859

Base Radio Controller, version TLN3425 (with cover removed)

2-3

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800/900/1500 MHz Base Radio Controller – CLN1469; 1500 MHz MC1 Base Radio Controller – TLN3425

Controls and Indicators

The BRC monitors the functions of other Base Radio modules. Front panel LEDs
indicate the status of modules that the BRC monitors. Upon initial power-up, all
front panel LEDs normally ßash three times. A RESET switch allows a manual
reset of the Base Radio. Figure 2-3 shows the BRC front panel.

STATUS

Figure:2-3

BR Controller (Front View)

Indicators

Table 2-3 lists and describes the BRC LEDs.

Table 2-3

LED Color Module

BR Green BR Solid (on) Station is keyed

PS Red Power

BR Controller Indicators

Condition Indications

Monitored

Flashing (on) Station is not keyed

Off Station is out of service or power is

Solid (on) FRU failure indication - Power Supply has

Supply

Flashing (on) Power Supply has a minor alarm, and may

Off Power Supply is operating normally (no

removed

a major alarm, and is out of service

be operating at reduced performance

alarms)

RESETBR PS EX PA CTL R1 R2 R3

CONTROL

EBTS316
122796JNM

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EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

800/900/1500 MHz Base Radio Controller – CLN1469; 1500 MHz MC1 Base Radio Controller – TLN3425

Table 2-3

LED

EX Red Exciter Solid (on) FRU failure indication - Exciter has a major

PA Red Power

CTL Red Controller Solid (on) FRU failure indication - BRC has a major

R1

R2

R3

BR Controller Indicators (Continued)

Color Module

Monitored

AmpliÞer

Red Receiver #1,

#2, or #3

Condition Indications

Flashing (on) Exciter has a minor alarm, and may be

Off Exciter is operating normally

Solid (on) FRU failure indication - PA has a major

Flashing (on) PA has a minor alarm and may be

Off PA is operating normally (no alarms)

Flashing (on) BRC has a minor alarm, and may be

Off BRC is operating normally (no alarms)

Solid (on) FRU failure indication - Receiver (#1, #2,

Flashing (on) Receiver (#1, #2, or #3) has a minor alarm,

Off Receiver (#1, #2, or #3) is operating

alarm, and is out of service

operating at reduced performance

(no alarms)

alarm, and is out of service

operating at reduced performance

alarm, and is out of service

operating at reduced performance

or #3) has a major alarm, and is out of
service

and may be operating at reduced
performance

normally (no alarms)

Controls

Table 2-4 lists the controls and descriptions.

Table 2-4

RESET Switch A push-button switch used to manually reset the BR.

STATUS
connector

BR Controller Controls

Control

Description

A 9-pin connector used for connection of a service computer. Provides a
convenient means for testing and conÞguring.

STATUS Connector

Table 2-5 the pin-outs for the STATUS connector.

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800/900/1500 MHz Base Radio Controller – CLN1469; 1500 MHz MC1 Base Radio Controller – TLN3425

Theory of Operation

Table 2-5

Pin-outs for the STATUS Connector

Pin-out

1CD

2 TXD

3 RXD

4 not used

5 GND

6 not used

7 CTS

8RTS

9 not used

Signal

Table 2-6 brießy describes the BRC circuitry. Figures 2-6 and 2-7 are functional
block diagrams of the Single Channel BRC.

Table 2-6

Host Microprocessor and
Host Glue ASIC

Non-Volatile Memory Consists of:

Volatile Memory Contains DRAM to store station software that executes

Ethernet Interface Provides the BRC with a 10Base2 Ethernet communication port.

RS-232 Interface Provides the BRC with two independent RS-232 serial

Digital Signal Processors and
TISIC

Station Reference Circuitry Generates the 16.8 MHz and 2.1 MHz reference signal used

Input Ports Contains two 16-line input buses. These buses receive

Output Ports Contains three 16-line output buses. These buses provide a path

Remote Station Shutdown Provides software control to cycle power on the BR.

BR Controller Circuitry

Circuit

Description

Contains two integrated circuits that comprise the central
controller of the BRC and station.

¥ EPROMs containing the station operating software

¥ one EEPROM containing the station codeplug data

commands. Contains SRAM which the host microprocessor
uses for general data space.

The interface networks both control and compressed voice
data.

interfaces.

Performs high-speed modulation/demodulation of
compressed audio and signaling data.

throughout the station.

miscellaneous inputs from the BR.

for sending miscellaneous control signals to circuits throughout
the BR.

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800/900/1500 MHz Base Radio Controller – CLN1469; 1500 MHz MC1 Base Radio Controller – TLN3425

Host Microprocessor

The host microprocessor is the the BRÕs main controller. The host operates at a
clock speed of 16.5 MHz. The Host Glue ASIC provides this clock frequency. The
processor controls Base Radio operation according to station software in
non-volatile memory. Two EPROMs contain the station software. An EEPROM
stores the station codeplug.

Serial Communication Buses

The microprocessor provides a general-purpose SCC2 serial communications bus.

The SCC2 serial communications bus is an asynchronous RS-232 interface. The
the BRC front panel includes a 9-pin, D-type connector. This connector provides a
port where service personnel may connect a service computer. The service
computer allows downloading of application code or diagnostic software. Service
personnel can perform programming and maintenance tasks via Man Machine
Interface (MMI) commands. The interface between the SCC2 port and the front
panel STATUS connector is via EIA-232 Bus Receivers/Drivers.

Address and Data Bus

The microprocessor has a 23-line address bus. The processor uses this bus to
access non-volatile and DRAM memory. The processor also uses the bus to
provide control for other BRC circuitry via memory mapping.

A 16-line data bus transfers data to and from the BRC memory. Such bus transfers
may involve other BRC circuitry, too. Buffers on the data bus allow transfers to
and from non-volatile and DRAM memory.

Host Glue ASIC

The Host Microprocessor controls the operations of the Host Glue ASIC. Table 2-7
describes this ASICÕs functions.

Table 2-7

SPI Bus Serves as a general-purpose, serial communications bus. Provides

DRAM Controller Provides signals necessary to access and refresh DRAM memory.

System Reset Generates a BRC Reset at power-up.

Host Microprocessor
Clock

Address Decoding Decodes addresses from the Host Microprocessor. Generates

Interrupt Controller Accepts interrupt signals from various BRC circuits (such as the DSPs).

Host Glue ASIC Functions

Function

communications between the Host Microprocessor and other Base
Radio modules.

Buffers the 33 MHz crystal outputs. Performs a divide-by-2 operation.
Outputs a 16.5 MHz clock signal for the Host Microprocessor.

corresponding chip-select signals for various BRC devices, such as:
DRAM, EPROM, I/O Ports, DSPs, and internal Host Glue ASIC
registers.

Organizes the interrupts based on hardware-deÞned priority ranking.
Sends interrupt and priority level information to the Host
Microprocessor (via IPL lines 1-3).

Description

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800/900/1500 MHz Base Radio Controller – CLN1469; 1500 MHz MC1 Base Radio Controller – TLN3425

Non-Volatile Memory

The Base Radio software resides in two 512K x 8 byte EPROMs. The Host
Microprocessor addresses these EPROMs via 19 of 23 host address bus lines. The
host accesses EPROM data over the 16-line host data bus.

The data that determines the station personality resides in an 8K x 8 byte
codeplug EEPROM. The microprocessor addresses the EEPROM over 15 of 23
host address bus lines. The host accesses EEPROM data over the 16-line data bus.

Stations ship with default data programmed into the codeplug. The BRC must
download Þeld programming information from network and site controllers. This
data includes operating frequencies and output power level. The station permits
adjustment of many station parameters, but the station does not store
adjustments. Refer to this manualÕs Software Commands chapter for additional
information.

Volatile Memory

Each BRC contains 2MB of DRAM. The BRC downloads station software code
into DRAM for station use. Since DRAM is volatile memory, it loses data during a
system reset or power failure.

DRAM also provides short-term storage for data generated and required during
normal operation. The BRC performs read and write operations over the Host
Address and Data buses. Read and write operations also involve column and row
select lines. The Host Glue ASIC controls these lines. The Host Glue ASIC also
controls address bus and column row signals. During normal operation, the
address bus and column row signals sequentially refresh DRAM memory
locations.

The BRC also includes two 32K x 8 byte fast Static RAM (SRAM) ICs. The
microprocessor accesses SRAM over the Data Bus and Host Address Bus. Access
requires the entire Data Bus, and 15 of the Host Address BusÕ 23 lines.

Ethernet Interface

The Ethernet Interface includes a Local Area Network (LAN) Controller. This
LAN Controller is a 32-bit address, 16-bit data LAN coprocessor. The LAN
coprocessor implements the CSMA/CD access method, which supports the IEEE

802.3 10Base2 standard. The LAN coprocessor communicates with the Host
Microprocessor via DRAM. The LAN coprocessor uses 22 of its 32 address lines
for the Ethernet interface.

2-8

The LAN coprocessor supports all IEEE 802.3 Medium Access Control, including
the following:

framing

❐

preamble generation

❐
❐

stripping

❐

source address generation

❐

destination address checking

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800/900/1500 MHz Base Radio Controller – CLN1469; 1500 MHz MC1 Base Radio Controller – TLN3425

The LAN coprocessor receives commands from the CPU by reading a speciÞed
memory block. The LAN ControllerÕs internal FIFOs optimize microprocessor bus
performance.

The LAN coprocessor includes an on-chip, Direct Memory Access (DMA)
controller. The DMA controller automatically transfers data blocks (buffers and
frames) from Ethernet to DRAM. These automatic data transfers relieve the host
CPU of byte transfer overhead.

The Ethernet Serial Interface works with the LAN coprocessor to perform these
major functions:

❐

10 MHz transmit clock generation (obtained by dividing the 20 MHz signal
provided by an on-board crystal)

Manchester encoding and decoding of frames

❐
❐

electrical interface to the Ethernet transceiver

An isolation transformer provides high voltage protection. The transformer also
isolates the Ethernet Serial Interface (ESI) and the transceiver. The pulse
transformer has the following characteristics:

❐

Minimum inductance of 75

❐

2000 V isolation between primary and secondary windings

❐

1:1 Pulse Transformer

The Coaxial Transceiver Interface (CTI) is a coaxial cable line driver/receiver for
the Ethernet. CTI provides a 10Base2 connection via a coaxial connector on the
board. This device minimizes the number of external components necessary for
Ethernet operations.

A DC/DC converter provides a constant voltage of -9 Vdc for the CTI. The
converterÕs input source voltage is 5 Vdc.

The CTI performs the following functions:

Receives and transmits data to the Ethernet coaxial connection

❐

Reports any collision that it detects on the coaxial connection

❐
❐

Disables the transmitter when packets are longer than the legal length
(Jabber Timer)

µ

H

Digital Signal Processors

The BRC includes a Receive Digital Signal Processor (RXDSP) and a Transmit
Digital Signal Processor (TXDSP). These DSPs and related circuitry process
compressed station transmit and receive audio or data. The related circuitry
includes the TDMA Infrastructure Support IC (TISIC) and the TISIC Interface
Circuitry. The DSPs only accepts input and output signals in digitized form.

68P81095E02-D 12/6/2000

The inputs are digitized receiver signals. The outputs are digitized voice audio
and data (modulation signals). The output DSP sends these signals to the Exciter.
DSPs communicate with the Microprocessor via an 8-bit host data bus. This bus is
on the Host Processor side. For all DSPs, interrupts drive communication.

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The RXDSP operates from a 40 MHz clock provided by an on-board crystal. The
RXDSP accepts redigitized signal from the receivers. The RXDSP also provides
address and data buses. These buses receive digitized audio from the TISIC.

The DSP program and signal processing algorithms reside in three 32K x 8 SRAM
ICs. The RXDSP accesses this software there. The RXDSP communicates with the
host bus via an 8-bit interface.

The Synchronous Serial Interface (SSI) port offers a serial data path to the TXDSP.
The Serial Communications Interface (SCI) port provides a serial control path
from the TXDSP.

The TXDSP operates at a clock speed of 40 MHz, provided by a clock oscillator.
The TXDSP sends the digitized signal to the TISIC. The TSCI then passes the
signal to the Exciter.

The TXDSP contains its own address and data buses. It uses these buses to access
its DSP program and signal processing algorithms in local memory. The TXDSP
memory consists of six 32K x 8 SRAM ICs. The TXDSP communicates with the
host bus via an 8-bit interface.

Error Correction Digital Signal Processor

The Error Correction Digital Signal Processor (U30) in the Model TLN3425A
operates at a clock speed of 60 MHz. An on-board oscillator (Y100) operates at 10
MHz. Circuitry inside the ECDSP multiplies this frequency to generate the
required clock signal.

Decoding is the main function of the Error Correction Digital Signal Processor
(ECDSP). The ECDSP accepts data from the Synchronous Serial Interface (SSI)
bus. The ECDSP performs various algorithms on the signal. Then the signal enters
the TXDSP via the SSI bus.

The ECDSP contains its own address and data buses. It uses these buses to access
its DSP program and signal processing algorithms in local memory. Two 32K x 8
SRAM ICs (U27 and U31) comprise the ECDSP memory. The ECDSP
communicates with the host bus via an 8-bit interface.

(

TLN3425 Only)

2-10

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800/900/1500 MHz Base Radio Controller – CLN1469; 1500 MHz MC1 Base Radio Controller – TLN3425

TISIC

The TISIC controls internal DSP operations. This circuit provides a number of
functions, including the following:

❐

Interfaces with the DSPs via the DSP address and data buses.

❐ Accepts a 16.8 MHz signal and a 1 PPS signal from Station

Reference Circuitry.

❐ Outputs a 2.1 MHz reference signal used by the Exciter and Receivers.
❐ Outputs a 4.8 MHz reference signal used by the Exciter to clock data into the

TRANLIN IC.

❐ Accepts differential data from the Receiver (RX1 through RX3) via

interface circuitry.

❐ Accepts and sends serial data from the Receiver (RX1 through RX3) via the

serial data bus.

❐ Accepts and formats differential data from the TXDSP for transmission to

the Exciter via interface circuitry.

❐ Generates 15 ms and 7.5 ms ticks. These synchronize to the 1 PPS time mark

from the iSC. The system routes these ticks to the TXDSP and RXDSP,
respectively.

❐ Generates the Receive SSI (RXSSI) frame sync interrupt for the RXDSP.

Station Reference Circuitry

The Station Reference Circuitry is a phase-locked loop (PLL). This PLL consists of
a high-stability, Voltage Controlled Crystal Oscillator (VCXO) and a Phase Locked
Loop IC. The iSCÕs GPS output connects to the 5 MHz/1 PPS A BNC connector on
the EBTS junction panel.

The PLL compares the reference frequency to the 16.8 MHz VCXO output. The
PLL then generates a DC correction or control voltage. With the control voltage
enable switch closed, the PLLÕs control voltage adjusts the VCXO frequency. This
adjustment achieves a stability equivalent to that of the external 5 MHz frequency
reference.

The control voltage from the PLL continuously frequency-controls the VXCO. The
VXCO outputs a 16.8 MHz clock signal, and applies the signal to the TISIC.

The TISIC divides the 16.8 MHz signal by eight and outputs a 2.1 MHz signal. A
splitter separates and buffers this signal. Then via the backplane, the output
signal enters the Exciter and Receivers as a 2.1 MHz reference .

The 4.8 MHz reference signal generated by the TISIC enters the Exciter module.
There it clocks data into and out of the TRANLIN IC.

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Input Ports

Two general purpose, 16-line input ports provide for various input signals from
the BRC and station circuitry. These inputs connect to the Host Microprocessor.

Input Port P0 -In and Port P1-In each consist of 16 lines. Via the backplane, these
lines carry signals from BRC circuitry and other station modules. The buses
communicate with the buffers to make data available to the Host Microprocessor
via the Host Data Bus. The DIP switch and Station Reference Circuitry are typical
inputs for these ports.

Output Ports

Three general purpose, 16-line output ports provide various control signals from
the Host Microprocessor. Via the backplane, these output ports carry control
signals to the BRC and station circuitry.

Output ports P0-Out through Port P2-Out each consist of 16 lines. These lines
derive from the Host Data Bus via latches.

Typical control signals include front panel LED control signals and SPI peripheral
address select lines.

Remote Station Shutdown

BRC circuitry can send a shutdown pulse to the Base Radio Power Supply. After
receiving this pulse, the power supply cycles BR power. The shutdown affects 5.1
Vdc, 28.6 Vdc and 14.2 Vdc sources. The BRC produces the shutdown pulse by
invoking software control signals. A remote site uses the shutdown function to
perform a hard reset of all BR modules.

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800 MHz QUAD Channel Base Radio Controller

800 MHz QUAD Channel Base Radio Controller

Overview

The Base Radio Controller (BRC) provides signal processing and operational
control for Base Radio modules. The BRC module consists of a printed circuit
board, a slide-in housing, and associated hardware.

The BRC memory contains the operating software and codeplug. The software
deÞnes BR operating parameters, such as output power and operating frequency.

The BRC connects to the Base Radio backplane with one 168-pin FutureBus+
connector and one blindmate RF connector. Two Torx screws secure the BRC in
the Base Radio chassis.

Figure 2-4 shows a top view of the BRC (model CLF6290A) with the cover
removed.

Figure:2-4

Controls and Indicators

The BRC monitors the functions of other Base Radio modules. The LEDs on the
front panel indicate the status of BRC-monitored modules. All LEDs on the BRC
front panel normally ßash three times upon initial power-up. A RESET switch

Base Radio Controller, version CLN1469 (with cover removed)

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800 MHz QUAD Channel Base Radio Controller

allows a manual reset of the Base Radio. Figure 2-5 shows the front panel of the
BRC.

Figure:2-5

BR Controller (Front View)

Indicators

Table 2-8 lists and describes the BRC LEDs.

Table 2-8

LED Color Module

PS Red Power

EXBRC Red Controller/

PA Red Power

REF Red Controller

BR Controller Indicators

Condition Indications

Monitored

Solid (on) FRU failure indication - Power Supply

Supply

Flashing (on) Power Supply has a minor alarm, and

Off Power Supply is operating normally

Solid (on) FRU failure indication - Controller/

Exciter

Flashing (on) Controller/Exciter has a minor alarm,

Off Controller/Exciter is operating

Solid (on) FRU failure indication - PA has a major

AmpliÞer

Flashing (on) PA has a minor alarm, and may be

Off PA is operating normally (no alarms)

Solid (on) FRU failure indication - Controller
Station
Reference

Flashing (on) BRC has a minor alarm, and may be

Off BRC is operating normally (no alarms)

has a major alarm, and is out of service

may be operating at reduced
performance

(no alarms)

Exciter has a major alarm, and is out of
service (Note: Upon power-up of the
BR, this LED indicates a failed mode
until BR software achieves a known
state of operation.)

and may be operating at reduced
performance

normally (no alarms)

alarm, and is out of service

operating at reduced performance

Station Reference has a major alarm,
and is out of service

operating in a marginal region

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800 MHz QUAD Channel Base Radio Controller

Table 2-8

LED Color Module

BR Controller Indicators (Continued)

Condition Indications

Monitored

RX1

RX2

RX3

RX4

TX1 Green BR Solid (on) Station Transmit Carrier #1 is keyed

TX2 Green BR Solid (on) Station Transmit Carrier #2 is keyed

TX3 Green BR Solid (on) Station Transmit Carrier #3 is keyed

TX4 Green BR Solid (on) Station Transmit Carrier #4 is keyed

Red Receiver #1,

#2, #3, or #4

Solid (on) FRU failure indication - Receiver (#1,

#2, #3 or #4) has a major alarm, and is
out of service

Flashing (on) Receiver (#1, #2, #3 or #4) has a minor

alarm, and may be operating at
reduced performance

Off Receiver (#1, #2, #3 or #4) is operating

normally (no alarms)

Flashing (on) Station Transmit Carrier #1 is not

keyed

Off Station is out of service, or power is

removed

Flashing (on) Station Transmit Carrier #2 is not

keyed

Off Station is out of service, or power is

removed

Flashing (on) Station Transmit Carrier #3 is not

keyed

Off Station is out of service, or power is

removed

Flashing (on) Station Transmit Carrier #4 is not

keyed

Off Station is out of service, or power is

removed

Controls

Table 2-9 lists the controls and descriptions.

Table 2-9

RESET Switch A push-button switch used to manually reset the BR.

STATUS
connector

BR Controller Controls

Control Description

A 9-pin connector used for connection of a service computer, providing a
convenient means for testing and conÞguring.

STATUS Connector

Table 2-10 the pin-outs for the STATUS connector.

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800 MHz QUAD Channel Base Radio Controller

Theory of Operation

Table 2-10

Pin-outs for the STATUS Connector

Pin-out Signal

1 not used

2 TXD

3 RXD

4 not used

5 GND

6 not used

7 not used

8 not used

9 not used

Table 2-11 brießy describes the BRC circuitry. Figure 2-9 is a functional block
diagram of the BRC.

Table 2-11

Host Microprocessor Contains integrated circuits that comprise the central controller

Non-Volatile Memory Consists of:

Volatile Memory Contains SDRAM to store station software used to execute

BR Controller Circuitry

Circuit Description

of the BRC and station

¥ FLASH containing the station operating software

¥ EEPROM containing the station codeplug data

commands.

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800 MHz QUAD Channel Base Radio Controller

Table 2-11

Ethernet Interface Provides the BRC with a 10Base2 Ethernet communication port

RS-232 Interface Provides the BRC with an RS-232 serial interface

Digital Signal Processors Performs high-speed modulation/demodulation of

TISIC Contains integrated circuits that provide timing reference

TX Reclock Contains integrated circuits that provide highly stable,

RX DSP SPI Contains integrated circuits that provide DSP SPI capability

Station Reference Circuitry Generates the 16.8 MHz and 48 MHz reference signals used

Input Ports Contains 16 signal input ports that receive miscellaneous

Output Ports Contains 40 signal output ports, providing a path for sending

Remote Station Shutdown Provides software control to cycle power on the BR

BR Controller Circuitry

Circuit Description

to network both control and compressed voice data

compressed audio and signaling data

signals for the station

reclocked transmit signals and peripheral transmit logic

and peripheral transmit logic

throughout the station

inputs from the BR

miscellaneous control signals to circuits throughout the BR

Host Microprocessor

The host microprocessor is the main controller for the BR. The processor operates
at a 50-MHz clock speed. The processor controls Base Radio operation according
to station software in memory. Station software resides in FLASH memory. For
normal operation, the system transfers this software to non-volatile memory. An
EEPROM contains the station codeplug.

NOTE

At BR power-up, the EXBRC LED indicates a major
alarm. This indication continues until BR software
achieves a predetermined state of operation.
Afterward, the software turns off the EXBRC LED.

Serial Communication Buses

The microprocessor provides a general-purpose SMC serial management
controller bus.

The SMC serial communications bus is an asynchronous RS-232 interface with no
hardware handshake capability. The BRC front panel includes a nine-pin, D-type
connector. This connector provides a port where service personnel may connect a
service computer. Service personnel can perform programming and maintenance
tasks via Man-Machine Interface (MMI) commands. The interface between the

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800 MHz QUAD Channel Base Radio Controller

SMC port and the front- panel STATUS connector is via EIA-232 Bus Receivers
and Drivers.

Host Processor

The microprocessor incorporates 4k bytes of instruction cache and 4k bytes of
data cache that signiÞcantly enhance processor performance.

The microprocessor has a 32-line address bus. The processor uses this bus to
access non-volatile memory and SDRAM memory. Via memory mapping, the
processor also uses this bus to control other BRC circuitry.

The microprocessor uses its Chip Select capability to decode addresses and assert
an output signal. The eight chip-select signals select non-volatile memory,
SDRAM memory, input ports, output ports, and DSPs.

The Host SPI serves as a general-purpose, serial communications bus. This bus...

❐ Provides communications between the Host Microprocessor and other Base

Radio modules.

❐ Provides condition signals necessary to access SDRAM, FLASH, and DSP.
❐ Provides refresh capability to SDRAM memory.
❐ Accepts interrupt signals from BRC circuits (such as DSPs).
❐ Organizes the interrupts, based on hardware-deÞned priority ranking.

The Host supports several internal interrupts from its Communications Processor
Module. These interrupts allow efÞcient use of peripheral interfaces.

The Host supports 10 Mbps Ethernet/IEEE 802.3.

A 32-line data bus transfers data to and from BRC memory and other BRC
circuitry. Buffers on this data bus allow transfers to and from non-volatile and
SDRAM memory.

Non-Volatile Memory

Base Radio software resides in 2M x 32 bytes of FLASH memory. The Host
Microprocessor addresses the FLASH memory with 20 of the host address busÕ 32
lines. The host accesses FLASH data over the 32-line host data bus. A
host-operated chip-select line provides control signals for these transactions.

The FLASH contains the operating system and application code. The system
stores application code in FLASH for fast recovery from reset conditions.
Application code transfers from network or site controllers may occur in a
background mode. Background mode transfers allow the station to remain
operational during new code upgrades.

The data that determines the station personality resides in a 32K x eight byte
codeplug EEPROM. The microprocessor addresses the EEPROM with 15 of the
host address busÕ 32 lines. The host accesses EEPROM data with eight of the data
busÕ 32 lines. A host-operated chip-select line provides control signals for these
transactions.

2-18 68P81095E02-D 12/6/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

800 MHz QUAD Channel Base Radio Controller

During the manufacturing process, the factory programs the codeplugÕs default
data. The BRC must download Þeld programming data from network and site
controllers. This data includes operating frequencies and output power level. The
station permits adjustment of many station parameters, but the station does not
store these adjustments. Refer to the Software Commands chapter for additional
information.

Volatile Memory

Each BRC contains 8MB x 32 bytes of SDRAM. The BRC downloads station
software code into SDRAM for station use. SDRAM also provides short-term
storage for data generated and required during normal operation. SDRAM is
volatile memory. A loss of power or system reset destroys SDRAM data.

The system performs read and write operations over the Host Address and Data
buses. These operations involve column and row select lines under control of the
Host processorÕs DRAM controller. The Host Glue ASICÕs address bus and
column row signals sequentially refresh SDRAM memory locations.

Ethernet Interface

The Host processorÕs Communications Processor Module (CPM) provides the
Local Area Network (LAN) Controller for the Ethernet Interface. The LAN
function implements the CSMA/CD access method, which supports the IEEE

802.3 10Base2 standard.

The LAN coprocessor supports all IEEE 802.3 Medium Access Control, including
the following:

❐ framing
❐ preamble generation
❐ stripping
❐ source address generation
❐ destination address checking

The PCM LAN receives commands from the CPU.

The Ethernet Serial Interface works directly with the CPM LAN to perform the
following major functions:

❐ 10 MHz transmit clock generation (obtained by dividing the 20 MHz signal

provided by on-board crystal)

❐ Manchester encoding/decoding of frames
❐ electrical interface to the Ethernet transceiver

An isolation transformer provides high-voltage protection. The transformer also
isolates the Ethernet Serial Interface (ESI) and the transceiver. The pulse
transformer has the following characteristics:

❐ Minimum inductance of 75 µH
❐ 2000 V isolation between primary and secondary windings
❐ 1:1 Pulse Transformer

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800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

800 MHz QUAD Channel Base Radio Controller

The Coaxial Transceiver Interface (CTI) is a coaxial cable line driver and receiver
for the Ethernet. CTI provides a 10Base2 connection via a coaxial connector on the
board. This device minimizes the number of external components necessary for
Ethernet operations.

A DC/DC converter provides a constant voltage of -9 Vdc for the CTI from a

3.3 Vdc source.

The CTI performs the following functions:

❐ Receives and transmits data to the Ethernet coaxial connection
❐ Reports any collision that it detects on the coaxial connection
❐ Disables the transmitter when packets are longer than the legal length

(Jabber Timer)

Digital Signal Processors

The BRC includes two Receive Digital Signal Processors (RXDSPs) and a Transmit
Digital Signal Processor (TXDSP). These DSPs and related circuitry process
compressed station transmit and receive audio or data. The related circuitry
includes the TDMA Infrastructure Support IC (TISIC) and the TISIC Interface
Circuitry. The DSPs only accept input and output signals in digitized form.

The inputs are digitized receiver signals. The outputs are digitized voice audio
and data (modulation signals). These signals pass from the DSP to the Exciter
portion of the EXBRC. DSPs communicate with the Microprocessor via an
eight-bit, host data bus on the host processor side. For all DSPs, interrupts drive
communication with the host.

The RXDSPs operate from an external 16.8 MHz clock, provided by the local
station reference. The RXDSP internal operating clock signal is 150MHz,
produced by an internal Phase-Locked Loop (PLL).

The RXDSPs accept digitized signals from the receivers through Enhanced
Synchronous Serial Interface (ESSI) ports. Each of two ESSI ports on a RXDSP
supports a single carrier (single receiver) digital data input. The DSP circuitry
includes two RXDSPs. These allow processing of up to four carriers (four
receivers).

The RXDSP accesses its DSP program and signal-processing algorithms in 128k
words of internal memory. The RXDSPs communicate with the host bus over an
8-bit interface.

Each RXDSP provides serial communications to its respective receiver module for
receiver control via a Serial Peripheral Interface (SPI). The SPI is a
parallel-to-serial conversion circuit, connected to the RXDSP data bus. Each
RXDSP communicates to two receive modules through this interface.

Additionally, a serial control path connects the two RXDSPs and the TXDSP. The
Synchronous Communications Interface (SCI) port facilitates this serial control
path.

For initialization and control purposes, one RXDSP connects to the TISIC device.

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EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

800 MHz QUAD Channel Base Radio Controller

The TXDSP operates at an external clock speed of 16.8 MHz, provided by the
EXBRC local station reference. The TXDSP internal operating clock is 150MHz,
produced by an internal Phase Lock Loop (PLL).

The TXDSP sends up to four carriers of digitized signal to the EX11 exciter. The
exciter converts the digital signal to analog. Also at the exciter, a highly stable
clock reclocks the digital data. Reclocking enhances transmit signal integrity. Two
framed and synchronized data streams result. One data stream is I-data, and the
other is the Q-data stream.

The TXDSP contains its own, internal address and data memory. The TXDSP can
store 128k words of DSP program and data memory. An eight-bit interface
handles TXDSP-to-host bus communications.

68P81095E02-D 12/6/2000 2-21

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

800 MHz QUAD Channel Base Radio Controller

TISIC

The TISIC controls internal DSP operations. This circuit provides the following
functions:

❐ For initialization and control, interfaces with one RXDSP via the DSP

address and data buses.

❐ Accepts a 16.8 MHz signal from Station Reference Circuitry.
❐ Accepts a 5 MHz signal, modulated with one pulse per second (1 PPS) from

the site reference.

❐ Demodulates the 1 PPS
❐ Outputs a 1 PPS signal and a windowed version of this signal for network

timing alignment.

❐ Outputs a 2.4 MHz reference signal used by the Exciter.l
❐ Generates 15 ms and 7.5 ms ticks. (These ticks synchronize to the 1 PPS time

mark. The system decodes the time mark from the site reference. Then the
system routes the reference to the TXDSP and RXDSPs.)

Station Reference Circuitry

The Station Reference Circuitry is a phase-locked loop (PLL). This PLL consists of
a high-stability, Voltage-Controlled, Crystal Oscillator (VCXO) and a PLL IC. GPS
output from the iSC connects to the 5 MHz/1 PPS BNC connector on the BR
backplane. Wiring at this connector routes signals to EXBRC station reference
circuitry.

The PLL compares the 5 MHz reference frequency to the 16.8 MHz VCXO output.
Then the PLL generates a DC correction voltage. The PLL applies this correction
voltage to the VCO through an analog gate. The analog gate closes when three
conditions coexist: (1) The 5 MHz tests stable. (2) The PLL IC is programmed. (3)
Two PLL oscillator and reference signal output alignments occur.

A loss of the 5 MHz / 1 PPS signal causes the control voltage enable switch to
open. This complex PLL control allows the BR to maintain call-handover
capability during short disconnects (approximately one minute) of the 5 MHz/1
PPS signal. (For example, during 5 MHz/1 PPS cable maintenance work.)

When the gate enables, the control voltage from the PLL can adjust the
high-stability VCXO frequency. The adjustment can achieve a stability nearly
equivalent to that of the external, 5 MHz frequency reference.

The correction voltage from the PLL continuously adjusts the VXCO frequency.
The VXCO outputs a 16.8 MHz clock signal. The circuit applies this clock signal to
the receiver, 48 MHz reference and TISIC.

The receivers use the 16.8MHz as the clock input and synthesizer reference.

The 48 MHz EXBRC synthesizer uses the 16.8 MHz as its synthesizer reference.
The 48 MHz synthesizer output is the clock input for the TXDSP I and Q data
reclock circuitry.

The TISIC divides the 16.8 MHz signal by seven, and outputs a 2.4 MHz signal.
This output signal then becomes the 2.4 MHz reference for the Exciter.

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EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

800 MHz QUAD Channel Base Radio Controller

Input Ports

One general-purpose input register provides for BRC and station circuit input
signals. The register has 16 input ports. The Host Data Bus conveys input register
data to the Host Microprocessor. Typical inputs include 16.8 and 48 MHz Station
Reference Circuitry status outputs and reset status outputs.

Output Ports

Two general-purpose output registers distribute control signals from the Host
Microprocessor to the BRC and station circuitry. Each register has 40 output ports.
Control signal distribution occurs over the backplane. The Host Data Bus drives
the output portsÕ latched outputs. Typical control signals include front-panel LED
signals and SPI peripheral enable and address lines.

Remote Station Shutdown

The BRC contains power supply shutdown circuitry. This circuitry can send a
shutdown pulse to the Base Radio Power Supply. BRC software generates the
shutdown control pulse.

After receiving a shutdown pulse, the power supply turns off BR power. Shut
down power sources include 3.3, 28.6 and 14.2 Vdc sources throughout the BR.
Due to charges retained by BR storage elements, power supply voltages may not
reach zero. The shutdown only assures that the host processor enters a
power-on-reset state.

A remote site uses the shutdown function to perform a hard reset of all BR
modules.

68P81095E02-D 12/6/2000 2-23

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

This Page Intentionally

Left Blank

2-24 68P81095E02-D 11/9/2000

S

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

2

ingle Channel Base Radio Controller

ADDR BUS

FROM
HOST

MICROPROCESSOR

A2-A23
DATA BUS

D0-D15

COPROCESSOR

ADDR BUS

INTERFACE

ETHERNET

COPROCESSOR

(82596DX)

ETHERNET INTERFACE

LED CONTROL

LINES

(P/O I/O PORT

P0 OUT)

FRONT PANEL LEDS

REMOTE STATION

SHUTDOWN CIRCUITRY

FROM HOST

MICROPROCESSOR

I/O PORT P0 IN

VARIOUS INPUTS

FROM BRC &

STATION CIRCUITRY

I/O PORT P1 IN

16

16

INPUT/OUTPUT PORTS CIRCUITRY

HOST

LANIIC

COPROCESSOR

DATA BUS

8

BASE

RADIO

28V

I/O PORT

P2 OUT

HOST DATA BUS

BUFFERS

ETHERNET

SERIAL

INTERFACE

ETHERNET

SERIAL

INTERFACE

POWER

SUPPLY

SHUTDOWN

CIRCUITRY

EXCITER PA

SHUTDOWN
(TO POWER

SUPPLY)

BUFFERS

CLSN

RCV

TRMT

ISOLATION

TRANSFORMER

CTL

R1 R2 R3

I/O PORT P0 OUT

I/O PORT P1 OUT

I/O PORT P2 OUT

CD

RX

TX

16

16

16

TRANSCEIVER

10BASE2

COAX

VARIOUS

CONTROL

LINES TO BRC &

STATION

CIRCUITRY

HOST MICROPROCESSOR / HOST ASIC

HOST

MICRO-

PROCESSOR

HOST ADDRESS BUS

NON-VOLATILE MEMORY

EPROM

512K X 8

A1-A19

8K X 8

EEPROM

CODEPLUG

32K X 8

SRAM

HOST

ADDRESS

A1-A18

A1-A19

A1-A15

A1-A15

A1-A15

16.5 MHZ CLK

SERIAL COMMUNICATIONS BUS

4

SERIAL COMMUNICATIONS BUS

8

HOST ADDRESS BUS

HOST DATA BUS

BUFFERS

HOST BUFFERED DATA BUS

EPROM

512K X 8

32K X 8

SRAM

CIRCUITRY

D0-D15

D0-D7

D0-D15

D0-D15

33 MHZ
TIMING

HOST
GLUE

ASIC

HOST

ADDRESS

1-23

A1-A11

A10-A22

COLUMN/ROW

SELECT

EIA-232

BUS

RECEIVERS/

DRIVERS

EIA-232

BUS

RECEIVERS/

DRIVERS

VCC

3

SPI BUS

HOST BUFFERED DATA BUS

DRAM

DRAM

ADDRESS

DRAM ADDRESS

1M X 16

COL

SELECT

(CAS*)

HOST ADDRESS BUS

MULTIPLEXER

BUFFERS

BUFFERS

STATUS PORT
(9 PIN D CONNECTOR
ON BRC FRONT PANEL)

4

RS-232 PORT
(9 PIN D CONNECTOR
ON BACKPLANE)

8

RESET SWITCH
(FRONT PANEL)

SPI BUS

TO/FROM

STATION MODULES

A

ROW

SELECT

(RAS*)

DRAM

COLUMN

ADDRESS

DRAM

ROW

ADDRESS

DRAM MEMORY

68P81095E02-D 4/16/99

Figure:2-6

800/900 MHz Base Radio Controller Functional Block Diagram
(Sheet 1 of 2)

EBTS286
010397SN

2-25

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

Base Radio Controller

SYNCHRONOUS

SERIAL INTERFACE (SSI)

3

HOST

DATA

BUS

FROM
HOST

MICRO-

PROCESSOR

SERIAL

COMMUNICATIONS

INTERFACE (SCI)

DIGITAL SIGNAL PROCESSOR
(DSP) / DSP ASIC

HOST

ADDRESS

BUS

3

HOST
PORT

TRANSMIT

DIGITAL
SIGNAL

PROCESSOR

(TXDSP)

CLOCK

OSCILLATOR

ADDRESS

DATA

3

32K X 8

32K X 8

32K X 8

RAM

RAM

RAM

TRANSMIT SYNCHRONOUS
SERIAL INTERFACE (TXSSI)

32K X 8

RAM

32K X 8

RAM

32K X 8

RAM

RX1 DATA

RX1 SERIAL

RX2 DATA

RX2 SERIAL

RX3 DATA

TISIC

RX3 SERIAL

4.8 MHz TXLIN

TXLIN

DATA

CLOCK

SERIAL BUS

6

SERIAL BUS

6

SERIAL BUS

6

TISIC INTERFACE CIRCUITRY

BUFFERS

BUFFERS

BUFFERS

SERIAL BUS

6

SERIAL BUS

6

SERIAL BUS

6

TTL-TO-DIFFERENTIAL
CONVERTER/BUFFER

TTL-TO-DIFFERENTIAL
CONVERTER/BUFFER

DIFFERENTIAL DATA

FROM RECEIVER MODULE #1

VIA BACKPLANE

SERIAL BUS

TO/FROM

RECEIVER

MODULE #1

DIFFERENTIAL DATA

FROM RECEIVER MODULE #2

VIA BACKPLANE

SERIAL BUS

TO/FROM

RECEIVER

MODULE #2

DIFFERENTIAL DATA

FROM RECEIVER MODULE #3

VIA BACKPLANE

SERIAL BUS

TO/FROM

RECEIVER

MODULE #3

DIFFERENTIAL-TO-TTL

CONVERTER/BUFFER

DIFFERENTIAL-TO-TTL

CONVERTER/BUFFER

DIFFERENTIAL-TO-TTL

CONVERTER/BUFFER

DIFFERENTIAL DATA

TO EXCITER MODULE

VIA BACKPLANE

4.8 MHz TRANLIN CLOCK
TO EXCITER MODULE

VIA BACKPLANE

RX1 DATA

RX2 DATA

RX3 DATA

HOST

DATA

FROM
HOST

MICRO-

PROCESSOR

SERIAL

COMMUNICATIONS

INTERFACE (SCI)

SYNCHRONOUS SERIAL

INTERFACE (SSI)

BUS

HOST

ADDRESS

BUS

HOST
PORT

RECEIVE

DIGITAL

SIGNAL

PROCESSOR

(RXDSP)

3

3

ADDRESS

DATA

DIGITAL SIGNAL PROCESSOR (DSP) / DSP ASIC

Figure:2-7

800/900 MHz Base Radio Controller Functional Block Diagram
(Sheet 2 of 2)

AGC

RECEIVE SYNCHRONOUS

SERIAL INTERFACE BUS

(RXSSI)

3

ADDRESS

DSP DATA BUS

DATA

32K X 8

RAM

RESET

2.1 MHZ
OUT

16.8 MHZ
IN

1PPS

4

32K X 8

RAM

32K X 8

TO RECEIVERS (1-3)

2.1 MHZ FROM DSP ASIC

16.8 MHZ TO ASIC

5 MHz/1PPS

BNC CONNECTOR

ON BACKPLANE

5MHz/1PPS COMBINED SIGNAL

2.1 MHZ REF TO EXCITER

BUFFER/

SPLITTER

SPI BUS

3

HIGH

STABILITY

VCXO

A

3

CONTROL VOL TAGE

MODULE VIA BACKPLANE

2.1 MHZ REF TO RECEIVER

MODULE #1, 2, 3 VIA BACKPLANE

5 MHZ REF

16.8 MHZ

OSC

F

IN

16.8 MHZ TO ASIC

IN

PHASE

LOCKED

LOOP

IC

ENABLE
INPUT

RAM

STATION REFERENCE CIRCUITRY

CONTROL VOL TAGE

ENABLE SWITCH

EBTS292
122094JNM

26

68P81095E02-D 4/16/99

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

Base Radio Controller

Functional Block Diagram

Model TLN3425

(Includes Front Panel Board)

FROM

HOST

MICROPROCESSOR

ADDR BUS

DATA BUS

COPROCESSOR

ADDR BUS

HOST

INTERFACE

82596DX

ETHERNET

COPROCESSOR

ETHERNET INTERFACE

LED CONTROL

LINES

(P/O I/O PORT

P0 OUT)

FRONT PANEL LEDS (Part of TRN7769)

REMOTE STATION

SHUTDOWN CIRCUITRY

FROM HOST

MICROPROCESSOR

I/O PORT P0 IN

VARIOUS INPUTS

FROM BRC &

STATION CIRCUITRY

I/O PORT P1 IN

16

16

INPUT/OUTPUT PORTS CIRCUITRY

COPROCESSOR

DATA BUS

8

BASE

RADIO

28V

I/O PORT

P3 OUT

HOST DATA BUS

BUFFERS

ETHERNET

SERIAL

INTERFACE

XMT CLK
(10 MHZ)

20 MHZ
TIMING

CIRCUIT

ETHERNET

SERIAL

INTERFACE

POWER
SUPPLY

SHUTDOWN

CIRCUITRY

20 MHz

EXCITER PA

SHUTDOWN

(TO POWER

SUPPLY)

LATCHES

CLSN

RCV

TRMT

5 VDC

ISOLATION

TRANSFORMER

BRC

RX1 RX2 RX3

I/O PORT P0 OUT

I/O PORT P1 OUT

I/O PORT P2 OUT

I/O PORT P3 OUT

CD

RX

TX

16

16

16

16

DC/DC

CONVERTER

-9 VDC

TRANSCEIVER

10BASE2

COAX

VARIOUS

CONTROL

LINES TO BRC &

STATION

CIRCUITRY

HOST MICROPROCESSOR / HOST ASIC

HOST

MICRO-

PROCESSOR

HOST ADDRESS BUS

NON-VOLATILE MEMORY

EPROM

256K X 8

A1-A18

8K X 8

EEPROM

CODEPLUG

8K X 8
SRAM

A1-A13

HOST

ADDRESS

A1-A23

A1-A18

A1-A15

A1-A13

4

8

23

16

BUFFERS

HOST BUFFERED DATA BUS

EPROM

256K X 8

8K X 8
SRAM

16.5 MHZ CLK

SERIAL COMMUNICATIONS BUS (SCC2)

SERIAL COMMUNICATIONS BUS (SCC3)

HOST ADDRESS BUS

HOST DATA BUS

33 MHZ
TIMING

CIRCUITRY

STATIC RAM

HOST

ASIC

HOST

ADDRESS

1-23

A1-A11

A10-A22

COLUMN/ROW

SELECT

EIA-232

BUS

RECEIVERS/

DRIVERS

EIA-232

BUS

RECEIVERS/

DRIVERS

3

SPI BUS

HOST BUFFERED DATA BUS

DRAM

ADDRESS

DRAM

ADDRESS

DRAM

1M X 8

COL

SELECT

(CAS*)

HOST ADDRESS BUS

DRAM ADDRESS

MULTIPLEXER

BUFFERS

BUFFERS

6

9

SPI BUS

TO/FROM

STATION MODULES

A

ROW

SELECT

(RAS*)

1M X 8

COL

SELECT

(CAS*)

DYNAMIC RAM

STATUS
(9 PIN D CONNECTOR
ON BRC FRONT PANEL)

RS232
(9 PIN D CONNECTOR
ON BACKPLANE)

DRAM

ROW

SELECT

(RAS*)

DRAM

COLUMN

ADDRESS

DRAM

ROW

ADDRESS

68P81095E02-D 4/16/99

Figure:2-8

1500 MHz Base Radio Controller Functional Block Diagram
(Sheet 1 of 2)

2-27

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

Base Radio Controller

Functional Block Diagram
Model TLN3425
(Includes Front Panel Board)

40 MHZ
TIMING

CIRCUITRY

SCI

HOST DATA BUS

FROM HOST

MICROPROCESSOR

LATCH ADDRESS

BUS

SSI

3

3

HOST
PORT

ADDRESS

TRANSMIT

DIGITAL

SIGNAL

PROCESSOR

DIGITAL SIGNAL PROCESSOR (DSP) / DSP ASIC

10 MHZ TIMING

HOST DATA BUS

FROM HOST

MICROPROCESSOR

HOST ADDRESS

BUS FROM HOST

MICROPROCESSOR

LATCH ADDRESS BUS

CIRCUITRY

SSI

3

LATCH

SSI

3

DIGITAL SIGNAL PROCESSOR (DSP) / DSP ASIC

DATA

ERROR

CORRECTION

DIGITAL
SIGNAL

PROCESSOR

ADDRESS

DATA

3

32K X 8

RAM

32K X 8

RAM

32K X 8

RAM

TRANSMIT SYNCHRONOUS

SERIAL INTERFACE (TXSSI)

32K X 8

RAM

32K X 8

RAM

32K X 8

RAM

32K X 8

RAM

32K X 8

RAM

RX1 SERIAL

RX2 SERIAL

DSP

GLUE

ASIC

RX3 SERIAL

RX1 DATA

RX2 DATA

RX3 DATA

TXLIN

DATA

TXLIN

CLOCK

AGC

SERIAL BUS

6

SERIAL BUS

6

SERIAL BUS

6

DSP ASIC INTERFACE CIRCUITRY

BUFFERS

BUFFERS

BUFFERS

SERIAL BUS

6

SERIAL BUS

6

SERIAL BUS

6

FROM RECEIVER MODULE #3

TTL-TO-DIFFERENTIAL

CONVERTER/BUFFER

TTL-TO-DIFFERENTIAL

CONVERTER/BUFFER

DIFFERENTIAL DATA

FROM RECEIVER MODULE #1

VIA BACKPLANE

SERIAL BUS

TO/FROM

RECEIVER

MODULE #1

DIFFERENTIAL DATA

FROM RECEIVER MODULE #2

VIA BACKPLANE

SERIAL BUS

TO/FROM

RECEIVER

MODULE #2

DIFFERENTIAL DATA

VIA BACKPLANE

SERIAL BUS

TO/FROM

RECEIVER

MODULE #3

DIFFERENTIAL-TO-TTL

CONVERTER/BUFFER

DIFFERENTIAL-TO-TTL

CONVERTER/BUFFER

DIFFERENTIAL-TO-TTL

CONVERTER/BUFFER

DIFFERENTIAL DATA

TO EXCITER MODULE

VIA BACKPLANE

DIFFERENTIAL DATA

TO EXCITER MODULE

VIA BACKPLANE

RX1 DATA

RX2 DATA

RX3 DATA

AGC

TO RECEIVER

VIA BACKPLANE

28

LATCH ADDRESS

HOST DATA BUS

FROM HOST

MICROPROCESSOR

40 MHZ
TIMING

CIRCUITRY

SCI

BUS

SSI

HOST
PORT

3

3

ADDRESS

RECEIVE

DIGITAL

SIGNAL

PROCESSOR

DIGITAL SIGNAL PROCESSOR (DSP) / DSP ASIC

Figure:2-9

1500 MHz Base Radio Controller Functional Block Diagram
(Sheet 2 of 2)

DATA

BUFFER/

SPLITTER

1 PPS

STRIPPER

PAL

3

32K X 8

RAM

DSP DATA BUS

32K X 8

RAM

ADDRESS

DATA

2.1 MHZ
OUT

16.8 MHZ
IN

1 PPS

IN

2.1 MHZ FROM DSP ASIC

16.8 MHZ TO ASIC

5 MHZ FROM

EXTERNAL

REFERENCE

(FOR NETTING

PENDULUM)

1 PPS

BNC CONNECTOR

ON BACKPLANE

32K X 8

RAM

3

RECEIVE SYNCHRONOUS

SERIAL INTERFACE BUS

(RXSSI)

A

STATION REFERENCE CIRCUITRY

SPI BUS

3

3

STABILITY

FREQUENCY NET ENABLE

2.1 MHZ REF TO EXCITER
MODULE VIA BACKPLANE

2.1 MHZ REF TO RECEIVER

MODULE #1, 2, 3 VIA BACKPLANE

5 MHZ REF

SPI BUS

HIGH

16.8 MHZ

VCO

CONTROL VOL TAGE

(I/O PORT P1 OUT)

OSC

IN

PHASE
LOCKED
LOOP IC

F

IN

16.8 MHZ TO ASIC

CONTROL VOL TAGE

ENABLE SWITCH

68P81095E02-D 4/16/99

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

Base Radio Controller

2

QUAD Channel Base

Radio Controller

Functional Block Diagram

LED
CONTROL
LINES

HOST
LATCH
P0 OUT

12

POWER

SUPPLY

EXCITER/
CONTROL

PA REF RX1 RX2 RX3 RX4 TX1 TX2 TX3 TX4

3.3V

P0_OUT

SHUTDOWN
CIRCUITRY

SHUTDOWN
(TO POWER
SUPPLY)

FRONT PANEL LEDS

5MHZ_1PPS
BASE RADIO
INPUT

5MHZ
1PPS

G
A
T
I
N
G

STATION REFERENCE CIRCUITRY

SYNTHESIZER
IC / CIRCUITRY

SPI
BUS

PHASE
DETECTION/
FILTERING/
CONTROL

DISCONNECT/
CONNECT
CONTROL

STEARING
LINE

HIGH
STABILITY
VCXO

16.8 MHZ

REMOTE STATION
SHUTDOWN CIRCUITRY

SYNTHESIZER

16.8MHZ

TRANSMIT REFERENCE CIRCUITRY

IC / CIRCUITRY

SPI
BUS

PHASE
DETECTION/
FILTERING

STEARING
LINE

HIGH
STABILITY
VCXO

48 MHZ

68P81095E02-D 12/4/2000

Figure:2-10

QUAD CHANNEL Base Radio Controller Functional Block Diagram
(Sheet 1 of 2)

2--29

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

Base Radio Controller

QUAD Channel
Base Radio Controller

Functional Block Diagram

SERIAL MANAGEMENT CONTROLLER (SMC2)

SCC1
ETHERNET
SERIAL
INTERFACE

8

HOST

MICRO-

PROCESSOR

CS2

CS3

D[0:31]

CS4

CS0
CS1

ETHERNET

SERIAL

INTERFACE

SERIAL PERIPHERAL INTERFACE

HOST ADDRESS BUS

GPLA0, A[8,9,17,18,20:29],RAS,CAS,WE

SDRAM
4M x 16

SDRAM
4M x 16

D[16:31]

HOST DATA BUS

HOST BUFFERED ADDRESS BUS

MA[2:21]

FLASH
1M x 16

2

CLSN

RCV RX

ISOLATION

TRANSFORMER

TRMT TX

3

DRAM MEMORY

D[0:15]

SDRAM
4M x 16

SDRAM
4M x 16

D[16:31]

MA[2:21]

MD[0:15]

FLASH
1M x 16

EIA-232
BUS
RECEIVERS/
DRIVERS

ETHERNET INTERFACE

CD

BUFFER

D[0:15]

MD[0:15]

2

TRANS­CEIVER

3

A[0:7]

D[0:31]

D[0:7]

MA[0:14]

STATUS PORT
(9 PIN D CONNECTOR
ON BRC FRONT PANEL)

SPI
BUS

A[10:31]

16

EXTENDED HOST

BUS BUFFERS

BUFFER

BUFFER

16

BUFFER

16

BUFFER

BUFFER

16

BUFFER

RX1 SERIAL DATA

RX2 SERIAL DATA

RX3 SERIAL DATA

10BASE2
COAX

SPI BUS
TO/FROM
STATION MODULES

16

16

RX4 SERIAL DATA

16

MA[21:0]

16

P0_IN
BUFFER

DSP_A[31:24]

MD[31:0]

DSP_D[31:24]

DIFFERENTIAL
TO SINGLE END

DIFFERENTIAL
TO SINGLE END

DIFFERENTIAL
TO SINGLE END

DIFFERENTIAL
TO SINGLE END

DIGITAL SIGNAL PROCESSING

CIRCUITRY

HOST-DSP BUFFERED ADDRESS BUS

HOST-DSP BUFFERED DATA BUS

HOST BUFFERED DATA BUS

MD[0:32]

P0_OUT
LATCH

32

RECEIVE
DIGITAL
SIGNAL
PROCESSOR
(RX DSP 2)

RECEIVE
DIGITAL
SIGNAL
PROCESSOR
(RX DSP 1)

NETWORKED

SCI

TRANSMIT
DIGITAL
SIGNAL
PROCESSOR
(TX DSP)

DIGITAL SIGNAL PROCESSING

CIRCUITRY

D[16:23]

PARALLEL
TO SERIAL

D[16:23]

D[0, 23]

D[0, 8:23]

A[0:5]

1 PPS TIMING, CONTROL/ SLOT TIMING/RESET

5MHZ

FRONT PANEL

RESET

1PPS

TRANSMIT

CIRCUITRY

TISIC

48 MHZ

CLOCK AND
FRAME SYNCH
CIRCUITRY

I/Q DATA

DSP SPI

SINGLE END
TO DIFFERENTIAL

EXCITER

SPI
BUS

SPI
CONTROL

16.8MHZ

SPI BUS TO
RECEIVER 3 & 4

SPI BUS TO
RECEIVER 1 & 2

2.4 MHz
TO EXCITER

SERIAL DATA
TO EXCITER

SPI BUS
TO EXCITER

50 MHZ
CLOCK

STATION MODULES

2--30

P0_IN

STATUS BUS

FROM

FLASH
1M x 16

NON-VOLATILE MEMORY

Figure:2-11

QUAD CHANNEL Base Radio Controller Functional Block Diagram
(Sheet 2 of 2)

MD[16:31]

FLASH
1M x 16

MD[16:31]

EEPROM
32k x 8

MD[24:31]

8

MD[16,17,20-24,28-31]

EXPANDED STATUS INPUT

AND OUTPUT CONTROL CIRCUITRY

MD[24:31]

P1_OUT
LATCH

8

40

P0_OUT/P1_OUT
CONTROL BUS

TO
STATION MODULES

68P81095E02-D 12/4/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

3 Exciter

Overview

This section provides technical information for the Exciter (EX). Table 3-1
describes covered topics.

Table 3-1

Chapter

800 MHz Exciter Ð TLN3337;
900 MHz Exciter Ð CLN1357;
1500 MHz Exciter Ð TLN3428

QUAD Channel 800 MHz Exciter 3-7 Describes the functions and characteristics of the Exciter

Exciter 800 MHz Functional 3-11 Functional Block Diagram for the Single Channel Base Radio

800 MHz QUAD ChannelFunctional Block Diagram 3-13 Functional Block Diagram for the QUAD Channel Base

Chapter T opics

Page Description

3-2 Describes the functions and characteristics of the Exciter

module for the single channel Base Radio (BR).

module for the QUAD channel Base Radio (BR).

Exciter

Radio Exciter

FRU Number to Kit Number Cross Reference

Exciter Field Replaceable Units (FRUs) are available for the iDEN EBTS. The FRU
contains the Exciter kit and required packaging. Table 3-2 provides a cross
reference between Exciter FRU numbers and kit numbers.

Table 3-2

Description

Single Channel Exciter (800 MHz) TLN3337 CLF1490

Single Channel Exciter (900 MHz) CLN1357 CLF1500

Single Channel Exciter (1500 MHz) TLN3428 CTX1120

QUAD Channel Exciter/Base Radio Controller
(800 MHz)

FRU Number to Kit Number Cross Referece

FRU Number Kit Number

CLN1497 CLF1560

68P81095E02-D 11/9/2000

3-1

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

800 MHz Exciter – TLN3337; 900 MHz Exciter – CLN1357; 1500 MHz Exciter – TLN3428

800 MHz Exciter – TLN3337;
900 MHz Exciter – CLN1357;
1500 MHz Exciter – TLN3428

Exciter Overview

The Exciter, together with the Power AmpliÞer (PA), provides the transmitter
functions for the Base Radio. The Exciter module consists of a printed circuit
board, a slide-in housing, and associated hardware.

The Exciter connects to the Base Radio backplane through a 96-pin DIN connector
and two blindmate RF connectors. Two Torx screws on the front of the Exciter
hold it in the chassis.

The Exciter has no controls or indicators. The manualÕs Base Radio section
supplies transmitter circuitry speciÞcations, including Exciter and PA
speciÞcations.

Figures 3-1 and 3-2 show the Exciter with the cover removed.

3-2

Figure:3-1

800/900 MHz Exciter (with cover removed)

68P81095E02-D 11/9/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

800 MHz Exciter – TLN3337; 900 MHz Exciter – CLN1357; 1500 MHz Exciter – TLN3428

Figure:3-2

1500 MHz Exciter, version TLN3428 (with top removed)

Theory of Operation

1.5GHZ-B859

Table 3-3 lists and describes basic Exciter circuitry. Figures 3-4 and 3-5 show the
functional block diagram of the Single Carrier Exciter. Figures 3-6 show the
functional block diagram of the QUAD Carrier Exciter.

Address Decoder Circuitry

The address decoder circuitry enables the BRC to use the address bus to control
Exciter circuitry. The BRC can select a speciÞc device on the Exciter via the SPI
bus for control or data communication purposes.

If board select circuitry decodes address lines A2 through A5 as the Exciter
address, the BRC enables the chip select circuitry. The chip select circuitry then
decodes address lines A0 and A1 to generate the chip select signals for the
EEPROM, A/D converter, Tranlin IC, and PLL IC. Once selected, the BRC uses
the SPI bus to send and receive data to and from the device.

Memory Circuitry

68P81095E02-D 11/9/2000

The memory circuitry consists of an EEPROM located on the Exciter. The BRC
performs all memory read and write operations via the SPI bus. Information

3-3

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

800 MHz Exciter – TLN3337; 900 MHz Exciter – CLN1357; 1500 MHz Exciter – TLN3428

Table 3-3

Tranlin IC Performs the following functions:

Exciter IC Interfaces with Tranlin IC to perform:

Address Decode, Memory, &
A/D Converter

Frequency Synthesizer
Circuitry

970 MHz VCO (800 MHz BR)

1025 MHz VCO (900 MHz BR)

760 MHz VCO (1500 MHz BR)

237 MHz VCO (800 MHz BR)

236 MHz VCO (1500 MHz BR)

180.6 MHz VCO (900 MHz BR) Provides a LO signal to Tranlin IC for the Þrst up-conversion

Regulator Circuitry Provides a regulated voltage to various ICs and RF devices

Linear RF ampliÞer Stages AmpliÞes the RF signal from the Exciter IC to an appropriate

Automatic Gain Control (AGC) provides automatic gain control of the transmitter (Exciter and

Exciter Circuitry

Circuit

Description

¥ up-converts the baseband data to the Þrst IF

¥ down-converts the IF feedback signal to baseband

¥ uses a baseband Cartesian feedback loop system, which is

necessary to obtain linearity from the transmitter and
avoid splattering power into adjacent channels

¥ performs training functions for proper linearization of the

transmitter

¥ up-conversion from the Þrst IF to the transmit operating

frequency

¥ down-conversion to the IF of PA output feedback signal

for input to the Tranlin IC

Serves as the main interface between the synthesizer, Tranlin
IC, A/D, and EEPROM on the Exciter and the BRC via the
SPI bus

Consists of a phase-locked loop and VCO. Provides a LO
signal to the Exciter IC for the second up-conversion and for
the Þrst down-conversion of the feedback signal from the PA

Provides a LO signal to the Exciter IC for the second
up-conversion to the transmit frequency

Provides a LO signal to Tranlin IC for the Þrst up-conversion
and for the second down-conversion of the feedback signal.
The synthesizer and divide by 2 circuitry within the Tranlin
IC set the Þrst IF to 118.5 MHz

and for the second down-conversion of the feedback signal.
The synthesizer and divide by 2 circuitry within the Tranlin
IC set the Þrst IF to 90.3 MHz

located on the Exciter

level for input to the PA

Power AmpliÞer modules) to maintain a level forward gain of
the RF ampliÞer stages.

3-4

stored in this memory device includes the kit number, revision number, module
speciÞc scaling and correction factors, and free form information (scratch pad).

A/D Converter Circuitry

Analog signals from various areas throughout the Exciter board are fed to the
A/D converter. Upon the BRCÕs request, these analog signals are converted to a
digital signal and are output to the BRC via the SPI lines. The BRC periodically
monitors and controls all signals.

68P81095E02-D 11/9/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

800 MHz Exciter – TLN3337; 900 MHz Exciter – CLN1357; 1500 MHz Exciter – TLN3428

The BRC monitors the regulated voltages, the external wattmeter (optional), the
PLL circuit, and other internal signals.

Tranlin IC Circuitry

The Tranlin IC is a main interface between the Exciter and BRC. The Digital Signal
Processors (DSP) of the BRC send Digitized signals (baseband data) to the Exciter
via the DSP data bus. The DSP clock signal from the Receiver clocks these data
signals.

The differential data clock signal also serves as a 4.8 MHz reference signal to the
internal synthesizer circuit of the Tranlin IC. The Tranlin compares the reference
signal with the output of the 237 MHz or 180.6 MHz (900 MHz BR) or 236 MHz
(1500 MHz BR) Voltage Controlled Oscillator (VCO). If the VCO output is out of
phase or differs in frequency, correction pulses arrive at the Oscillator and adjust
the VCO output.

The Tranlin IC up-converts the baseband data received from the BRC to the Þrst IF
of 118.5 MHz (90.3 MHz for 900 MHz BR). It also down-converts an IF feedback
signal from the Exciter IC to baseband data for summing.

The Serial Peripheral Interface (SPI) bus is used to communicate with the Tranlin
IC. The SPI bus serves as a general purpose bi-directional serial link between the
BRC and other modules of the Base Radio, including the Exciter. The SPI bus is
used to send control and operational data signals to and from the various circuits
of the Exciter.

Exciter IC Circuitry

The Exciter IC interfaces directly with the Tranlin IC to perform up-conversion
from the Þrst IF to the programmed transmit operating frequency. The Þrst IF
signal is passed through a band-pass Þlter before it reaches the Exciter IC.

The Exciter IC also down-converts the RF feedback signal from the PA to its IF
signal. The IF signal is then input to the Tranlin IC for conversion to baseband
data, which computes the Cartesian feedback.

Synthesizer Circuitry

The synthesizer circuitry consists of the Phase-Locked Loop (PLL) IC and
associated circuitry. The output of this circuit is combined with the 970 MHz
VCO (1025 MHz for 900 MHz BR, 700 MHz for 1500 MHz BR) to supply a Local
Oscillator (LO) signal to the Exciter IC for the second up-conversion of the
programmed transmit frequency. This signal is also used for the Þrst
down-conversion of the feedback signal from the PA.

68P81095E02-D 11/9/2000

An internal phase detector generates a logic pulse in proportion to the difference
in phase or frequency between the reference frequency and loop pulse signal.

If the reference frequency is faster than the VCO feedback frequency, the PLL IC
outputs an up signal. If the reference frequency is slower than the VCO feedback
frequency, the PLL IC outputs a down signal. These pulses are used as correction
signals and are fed to a charge pump circuit.

3-5

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

800 MHz Exciter – TLN3337; 900 MHz Exciter – CLN1357; 1500 MHz Exciter – TLN3428

The charge pump circuit consists of Þve transistors and its associated biasing
components. This circuit generates the correction signal and causes it to move up
or down in response to the phase detector output pulses. The correction signal
passes through the low-pass loop Þlter to the 970 MHz Voltage Controlled
Oscillator (VCO) circuit (1025 MHz VCO for 900 MHz BR).

970/1025 MHz Voltage Controlled Oscillator (VCO)

The 970 MHz VCO (1025 MHz for 900 MHz BR, 700 MHz for 1500 MHz BR)
generates the second injection frequency for the Exciter IC.

The VCO requires a very low-noise DC supply voltage of +10 Vdc for proper
operation. A Super Filter, which contains an ultra low-pass Þlter, drives the
oscillator. The Super Filter obtains the required low-noise output voltage for the
oscillator.

The output of the oscillator is tapped and sent to the VCO Feedback Filter. This
feedback signal is supplied to the Synthesizer circuitry for the generation of
correction pulses.

The untapped output of the 970 (or 1025) MHz VCO is sent to the second LO
injection circuitry.

236/237/180.6 MHz Voltage Controlled Oscillator (VCO)

The 237 MHz VCO (180.6 MHz for 900 MHz BR, 236 MHz for 1500 MHz BR)
provides a LO signal to Tranlin IC for the Þrst up-conversion and for the second
down-conversion of the feedback signal. The synthesizer and divide by 2
circuitry within the Tranlin IC set the Þrst IF to 118.5 MHz (90.3 MHz for 900 MHz
BR).

Regulator Circuity

This circuit generates three regulated voltages of +5 Vdc, +10 Vdc, and +11.8 Vdc.
All voltages are obtained from the +14.2 Vdc backplane voltage. These voltages
provide power to various ICs and RF devices of the Exciter.

Linear RF Amplifier Stages

This circuitry is used to amplify the RF signal from the Exciter IC to an
appropriate level for input to the PA.

Automatic Gain Control (AGC) (1500 MHz only)

3-6

The Automatic Gain Control (AGC) circuit controls the output gain of the
transmitter (Exciter and Power AmpliÞer modules) so that constant forward gain
of the RF ampliÞer stages is maintained. This is accomplished through the
comparison of feedback signals from the Power AmpliÞer and the Þrst ampliÞer
stage of the Exciter.

The output of the differential ampliÞers is used to adjust the Attenuator and
Image Filter.

68P81095E02-D 11/9/2000

Figure:3-3

800 MHz QUAD Channel Exciter (with cover removed)M

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

QUAD Channel 800 MHz Exciter

QUAD Channel 800 MHz Exciter

Exciter Overview

The Exciter and the Power AmpliÞer (PA) provide the transmitter functions of the
QUAD Channel Base Radio. The Exciter module consists of a printed circuit
board, a slide in housing, and associated hardware. The BRC shares the printed
circuit board and housing.

The Exciter connects to the Base Radio backplane through a 168-pin connector
and two blindmate RF connectors. Controller and exciter circuitry also
interconnect on the Exciter/Controller module. Two Torx screws on the front of
the Exciter secure it to the chassis.

An LED identiÞes the ExciterÕs operational condition, as described in the
manualÕs Controller section. The Base Radio section of the manual provides
speciÞcations for transmitter circuitry. This information includes data on the
Exciter and PAs.

Figures 3-3 shows the Exciter with the cover removed.

68P81095E02-D 11/9/2000

3-7

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

QUAD Channel 800 MHz Exciter

Theory of Operation

Table 3-4 describes the basic circuitry of the Exciter. Figures 3-4 and 3-5 show the
functional block diagram of the Single Carrier Exciter. Figures 3-6 show the
QUAD Carrier ExciterÕs functional block diagram.

Table 3-4

Exciter Circuitry

Circuit Description

LNODCT IC ¥ Up-converts baseband data to the transmit frequency

¥ Down-converts the PA feedback signal to baseband

¥ Uses a baseband Cartesian feedback loop system, necessary

to obtain linearity from the transmitter and avoid
splattering power into adjacent channels

¥ Performs training functions for proper linearization of the

transmitter

Memory & A/D Converter Serves as the main interface between the synthesizer, Tranlin

Frequency Synthesizer
Circuitry

970 MHz VCO (800 MHz BR) Provides a LO signal to the LNODCT IC, for up-conversion

90.3 MHz VCO (800 MHz BR) Provides a LO signal to LNODCT IC, for the up-conversion

Regulator Circuitry Provides a regulated voltage to various ICs and RF devices

Linear RF ampliÞer Stages AmpliÞes the RF signal from the Exciter IC to an appropriate

Automatic Gain Control (AGC) ¥ Provides automatic gain control of the transmitter (Exciter

IC, A/D, and EEPROM on the Exciter, and the BRC via the
SPI bus

¥ Consists of a phase-locked loop and VCO

¥ Provides a LO signal to the LNODCT IC for the second

up-conversion and first down-conversion of the feedback
signal from the PA

to the transmit frequency

and for the down-conversion of the feedback signal.
¥ The LNODCT IC mixes the 970 MHz VCO and 90.3 MHz

VCO

¥ The mixed output becomes the LO signal for Transmit

signal up- and down-conversion

located on the Exciter

level for input to the PA

and Power AmpliÞer modules)

¥ Maintains a level forward gain of the RF ampliÞer stages

3-8

Memory Circuitry

The memory circuitry is an EEPROM on the Controller portion of the Exciter/
Controller module. The Controller performs memory read and write operations
over the SPI bus. The memory device stores the following data...

❐

kit number

❐

revision number

module speciÞc scaling and correction factors

❐

serial number

❐

68P81095E02-D 11/9/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

free form information (scratch pad)

❐

QUAD Channel 800 MHz Exciter

A/D Converter Circuitry

Analog signals from various areas throughout the Exciter board enter the
A/D converter (A/DC). The A/DC converts these analog signals to digital form.
Upon request of the BRC, A/DC output signals enter the BRC via SPI lines. The
Controller periodically monitors all signals.

Some of the monitored signals include ampliÞer bias and synthesizer signals.

LNODCT IC Circuitry

The LNODCT IC is a main interface between the Exciter and BRC. The BRCÕs
Digital Signal Processor (DSP) sends digitized signals (baseband data) to the
Exciter over the DSP data bus.

The differential data clock signal serves as a 4.8 MHz reference signal to the
LNODCT ICÕs internal synthesizer. The LNODCT compares the reference signal
with the outputs of Voltage Controlled Oscillators (VCOs). The LNODCT might
sense that a VCOÕs output is out of phase or off-frequency. If so, then the
LNODCT sends correction pulses to the VCO. The pulses adjust VCO output,
thereby matching phase and frequency with the reference.

The LNODCT IC up-converts baseband data from the BRC to the transmit
frequency. The LNODCT IC also down-converts the Transmit signal from the
Power AmpliÞer to baseband data for summing.

The BRC uses the Serial Peripheral Interface (SPI) bus to communicate with the
LNODCT IC. The SPI bus serves as a general purpose, bi-directional, serial link
between the BRC and other Base Radio modules, including the Exciter. The SPI
carries control and operational data signals to and from Exciter circuits.

Synthesizer Circuitry

The synthesizer circuit consists of the Phase-Locked Loop (PLL) IC and associated
circuitry. This circuitÕs output combines with the 970 MHz VCO signal. The result
is a Local Oscillator (LO) signal for the LNODCT IC. The LNODCT uses this LO
signal to up-convert the programmed transmit frequency. The LNODCT also
uses the LO signal to down-convert the PA feedback signal.

An internal phase detector generates a logic pulse. This pulse is proportional to
the phase or frequency difference between the reference frequency and loop pulse
signal.

If the reference frequency is faster than the VCO feedback frequency, the PLL IC
outputs an up signal. If the reference frequency is slower than the VCO feedback
frequency, the PLL IC outputs a down signal. The synthesizer uses these pulses as
correction signals and feed them to a charge pump circuit.

68P81095E02-D 11/9/2000

The charge pump circuit consists of Þve transistors and associated biasing
components. This circuit generates the correction signal. The correction signal
moves up or down in response to phase detector output pulses. The correction

3-9

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

QUAD Channel 800 MHz Exciter

signal passes through the low-pass loop Þlter. The signal then enters the 970 MHz
Voltage Controlled Oscillator (VCO) circuit.

970 MHz Voltage Controlled Oscillator (VCO)

The 970 MHz VCO generates the second injection frequency for the LNODCT IC.

For proper operation, the VCO requires a very low-noise, DC supply voltage. An
ultra low-pass Þlter prepares the necessary low-noise voltage and drives the
oscillator.

The tapped oscillator output signal enters the VCO Feedback Filter. The
Synthesizer circuitry uses this feedback signal in the generation of correction
pulses.

The untapped output signal of the 970 MHz VCO enters the second LO
injection circuit.

90.3 MHz Voltage Controlled Oscillator (VCO)

The synthesizer within the LNODCT IC sets the 90.3 MHz signal. The 90.3 MHz
VCO provides a LO signal to the LNODCT IC. The LNODCT uses this signal in
up-converting and down-converting the feedback signal.

Regulator Circuitry

The voltage regulator generates three regulated voltages: +3 Vdc, +5 Vdc and
+11.7 Vdc. The regulator obtains input voltages from the +3.3 Vdc and +14.2 Vdc
backplane voltages. The regulated voltages power various ICs and RF devices in
the Exciter.

Linear RF Amplifier Stages

The Linear RF AmpliÞer boosts the RF signal from the LNODCT IC. The RF
AmpliÞer outputs an appropriate signal level to drive the PA.

3-10

68P81095E02-D 11/9/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

Exciter

RF FEEDBACK

FROM PA MODULE

DIFFERENTIAL
DATA & CLOCK

FROM

BRC MODULE

ADDRESS BUS

FROM CONTROL

MODULE

SPI BUS

TO/FROM CONTROL

MODULE

TRANLIN IC CIRCUITRY

TISIC DATA & CLOCK

237 MHZ

(180.6 MHZ)

VCO

CIRCUITRY

OSCILLATOR

ADDRESS DECODE, MEMORY, & A/D

CONVERTER CIRCUITRY

CHIP SELECT

DECODE

CIRCUITRY

BOARD SELECT

DECODE

CIRCUITRY

BUFFER

AMP

CHIP

SELECT

VARIOUS
SIGNALS

TO MONITOR

1ST LO
INJECTION
CIRCUITRY

TRANLIN IC

MEMORY

A/D

CONVERTER

3

c

Exciter

800 MHz Functional

Block Diagram

EXCITER IC CIRCUITRY

IF

OUT

IF

IN

BPF

REGULATOR

CIRCUITRY

+14.2 V

FROM

BACKPLANE

+11.8 V

REGULATOR

EXCITER IC

2ND LO

INJECTION

CIRCUITRY

+10 V

REGULATOR

(U3702)

+5 V

REGULATOR

+10 V

SOURCE

+11.8 V

SOURCE

ANALOG

+5 V SOURCE

970 MHZ

(1025 MHZ)

VCO CIRCUITRY

BUFFER

SYNTHESIZER

CIRCUITRY

2.1 MHZ

BUFFER

AMP

R

F

CHIP

SELECT

PHASE

LOCKED

LOOP

IN

IN

OSCILLATOR

IC

SPI BUS (CLOCK & DATA)

FROM BACKPLANE

CHARGE

PUMP

VCO

FEEDBACK

FILTER

+10 V

SUPER
FILTER

CONTROL VOL TAGE

(+2.5 TO +7.5 VDC)

VCO FEEDBACK

LOW-PASS

LOOP

FILTER

RF OUTPUT

TO PA MODULE

68P81095E02-D 4/1/2000

LINEAR RF AMPLIFIER

CIRCUITRY

NOTE: Where two frequencies are given, frequency without parentheses applies to 800 MHz BR only and frequency with parentheses applies to 900 MHz BR only.

BPF

Figure:3-4

Exciter Functional Block Diagram

EBTS283
101597JNM

3-11

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

Exciter

Exciter

Functional Block Diagram
Model TLN3428

RF FEEDBACK

FROM PA MODULE

RESET FROM

BRC MODULE

DSP DATA AND CLOCK

FROM BRC MODULE

SPI BUS

TO/FROM

BRC MODULE

ADDRESS BUS

FROM BRC

SPI BUS

TO/FROM BRC

TRANLIN IC

CIRCUITRY

DSP DATA & CLOCK

SPI BUS (DATA & CLOCK)

236 MHZ VCO

CIRCUITRY

SUPER
FILTER
(Q3200)

OSCILLATOR

(Q3201)

ADDRESS DECODE, MEMORY, & A/D

CONVERTER CIRCUITRY

CHIP SELECT

DECODE

CIRCUITRY

(U3000)

BOARD SELECT

DECODE

CIRCUITRY

(U3000)

+10 V

TRANLIN IC

1ST LO
INJECTION
CIRCUITRY

(L3201, C3206)

CHIP SELECT

CHIP SELECT

VARIOUS
SIGNALS

TO MONITOR

RESET

(U3600)

CHIP SELECT

IF

OUT

IF

(+2.5 TO +7.5 VDC)

CONTROL VOL T A GE

MEMORY

(U3006)

A/D

CONVERTER

(U3100)

POWER

CONTROL

IN

REGULATOR

CIRCUITRY

CHIP SELECT

EXCITER IC

CIRCUITRY

BAND-PASS

FILTER

+14.2 V

FROM

BACKPLANE

+11.8 V

REGULATOR

(U3701)

EXCITER IC

(U3500)

2ND LO
INJECTION
CIRCUITRY

(C4104, R3513)

+10 V

REGULATOR

(U3702)

+5 V

REGULATOR

(U3703)

RF FEEDBACK

FOR AGC DIFF AMP

+10 V

SOURCE

+11.8 V

SOURCE

ANALOG

+5 V SOURCE

AGC CIRCUITRY

DIFF AMP

(U3801,

U3802)

OPEN LOOP

ALARM
TO A/D

INTEGRATION/ATTN DRIVER

700 MHZ

VCO CIRCUITRY

FREQUENCY

DOUBLER

(U4100, T4100,

CR4100)

SYNTHESIZER

CIRCUITRY

CHIP SELECT

REFERENCE

BUFFER

(Q3401)

2.1 MHZ

PHASE
LOCKED
LOOP IC

(U3400)

R

IN

F

IN

+10 V

SUPER
FILTER
(Q3300)

OSCILLATOR

(Q3301)

VCO FEEDBACK

CHARGE

PUMP

(Q3404, Q3405,

Q3406, Q3407,

Q3408)

SPI BUS (CLOCK & DATA)

VCO

FEEDBACK

FILTER
(U3400)

CONTROL VOL TAGE

(+2.5 TO +7.5 VDC)

LO-PASS

LOOP
FILTER
(U3401)

FROM BACKPLANE

EXTERNAL

2.1 MHZ
REFERENCE

3-12

RF OUTPUT

TO PA MODULE

Figure:3-5

Exciter Functional Block Diagram

LINEAR RF AMPLIFIER

CIRCUITRY

AMP 4

(Q4002, Q4003)

AMP 3

(Q4200, Q4201)

ATTENU A TOR

IMAGE FILTER

(FL4000, FL4001

CR4000, CR4002)

AMP 2

(Q3902, Q3903)

RF FEEDBACK

FOR AGC
DIFF AMP

AMP 1

(Q3900, Q3901)

68P81095E02-D 4/1/2000

E

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

Exciter

3

xciter

800 MHz QUAD ChannelFunctional Block

RF FEEDBACK

FROM PA MODULE

DIFFERENTIAL
DATA & CLOCK

FROM

BRC MODULE

ADDRESS BUS

FROM CONTROL

MODULE

SPI BUS

TO/FROM CONTROL

MODULE

TRANLIN IC CIRCUITRY

TISIC DATA & CLOCK

237 MHZ

(180.6 MHZ)

VCO

CIRCUITRY

OSCILLATOR

ADDRESS DECODE, MEMORY, & A/D

CONVERTER CIRCUITRY

CHIP SELECT

DECODE

CIRCUITRY

BOARD SELECT

DECODE

CIRCUITRY

BUFFER

AMP

CHIP

SELECT

VARIOUS
SIGNALS

TO MONITOR

1ST LO
INJECTION
CIRCUITRY

TRANLIN IC

MEMORY

A/D

CONVERTER

EXCITER IC CIRCUITRY

IF

OUT

IF

IN

ICTURE

BPF

REGULATOR

CIRCUITRY

+14.2 V

FROM

BACKPLANE

+11.8 V

REGULATOR

EXCITER IC

2ND LO
INJECTION
CIRCUITRY

+10 V

REGULATOR

(U3702)

MUST

+5 V

REGULATOR

EE

S

BE

-

MARK

CHANGED

+10 V

UPS

SOURCE

+11.8 V

SOURCE

ANALOG

+5 V SOURCE

970 MHZ

(1025 MHZ)

VCO CIRCUITRY

!

SYNTHESIZER

CIRCUITRY

BUFFER

BUFFER

2.1 MHZ

AMP

R

F

CHIP

SELECT

PHASE

LOCKED

LOOP

IN

IC

IN

OSCILLATOR

FEEDBACK

+10 V

SUPER
FILTER

CONTROL VOL TAGE

(+2.5 TO +7.5 VDC)

SPI BUS (CLOCK & DATA)

FROM BACKPLANE

CHARGE

PUMP

VCO

FILTER

VCO FEEDBACK

LOW-PASS

LOOP

FILTER

RF OUTPUT

TO PA MODULE

68P81095E02-D 11/10/2000

P

HIS

T

NOTE: Where two frequencies are given, frequency without parentheses applies to 800 MHz BR only and frequency with parentheses applies to 900 MHz BR only.

LINEAR RF AMPLIFIER

CIRCUITRY

BPF

Figure:3-6

Exciter Functional Block Diagram

EBTS283
101597JNM

3-13

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

Exciter

This Page Intentionally

Left Blank

68P81095E02-D 11/10/2000

3-14

y

4

Power Amplifier

Overview

This section provides technical information for the Power AmpliÞer (PA). Table
4-1 describes covered topics.

Table 4-1

Chapter

40W, 800 MHz Ð TLF2020 (TTF1580);
70W, 800 MHz Ð TLN3335 (CTF1040);
60W, 900 MHz Ð CLN1355 (CLF1300);
40W, 1500 MHz Ð TLN3426 (TLN3426);
800 MHz QUAD Ð CLF1400 (CLF1400)

40W, 800 MHz Power AmpliÞer Ð TLF2020 (TTF1580) 4-15 Functional Block Diagram for the 40 Watt, 800 MHz, Single

70W, 800 MHz Power AmpliÞer Ð TLN3335 (CTF1040) 4-16 Functional Block Diagram for the 70 Watt, 800 MHz, Single

60W, 900 MHz Power AmpliÞer Ð CLN1355 (CLF1300) 4-17 Functional Block Diagram for the 60 Watt, 900 MHz, Single

40W, 1500 MHz Power AmpliÞer Ð TLN3426 4-18 Functional Block Diagram for the 40 Watt, 1500 MHz, Single

800 MHz QUAD Carrier Power AmpliÞer 4-19 Functional Block Diagram for the 800 MHz QUAD Channel

Chapter T opics

Page Description

4-2 Describes the functions and characteristics of the Base Radio

Power AmpliÞer (PA) module for the single and QUAD
Channel Base Radio (BR).

Channel Base Radio Power AmpliÞer (PA)

Channel Base Radio Power AmpliÞer (PA)

Channel Base Radio Power AmpliÞer (PA)

Channel Base Radio Power AmpliÞer (PA)

Base Radio Power AmpliÞer (PA)

FRU Number to Kit Number Cross Reference

Power Amplifer (PA) Field Replaceable Units (FRUs) are available for the iDEN
EBTS. The FRU contains the PAkit and required packaging. Table 4-2 provides a
cross reference between PA FRU numbers and kit numbers.

Table 4-2

Description

40 W, 800 MHz Single Channel Base Radio PA TLF2020 CLF1772

70 W, 800 MHz Single Channel Base Radio PA TLN3335 CLF1771

60 W, 900 MHz Single Channel Base Radio PA CLN1355 CLN7125

40 W, 1500 MHz Single Channel Base Radio PA TLN3426 TTG1000

800 MHz QUAD Channel Base Radio PA CLF1499 CLF1400

FRU Number to Kit Number Cross Referece

FRU Number Kit Number

y

40W, 800 MHz Ð TLF2020 (TTF1580); 70W, 800 MHz Ð TLN3335 (CTF1040); 60W, 900 MHz Ð CLN1355 (CLF1300); 40W, 1500 MHz
Ð TLN3426 (TLN3426); 800 MHz QUAD Ð CLF1400 (CLF1400)

40W, 800 MHz Ð TLF2020 (TTF1580);
70W, 800 MHz Ð TLN3335 (CTF1040);
60W, 900 MHz Ð CLN1355 (CLF1300);
40W, 1500 MHz Ð TLN3426 (TLN3426);
800 MHz QUAD Ð CLF1400 (CLF1400)

PA Overview

The Power Amplifier (PA), together with the Exciter, provides transmitter functions for
the QUAD Channel Base Radio. The PA accepts the low-level modulated RF signal from
the Exciter and amplifies the signal for transmission via the RF output connector.

The 800 MHz Base Radio can be equipped with either 40 Watt PA, TLF2020 (version
TTF1580) or 70 Watt PA, TLN3335 (version CTF1040). The 40W PA module consists of
five hybrid modules, four pc boards, and a module heatsink/housing assembly. The 70W
PA module consists of eight hybrid modules, four pc boards, and a module heatsink/
housing assembly.

The 900 MHz Base Radio is equipped with 60 Watt PA, CLN1355 (kit no. CLF1300A).
The PA module consists of four hybrid modules, two pc boards, and a module heatsink/
housing assembly.

The 1500 MHz Base Radio is equipped with 40 Watt PA, TLN3426. The PA module
consists of four hybrid modules, two pc boards, and the module heatsink/housing
assembly.

The 800MHz Quad Base Radio is equipped with the Quad PA, CLF1400. The PA module
consists of six hybrid modules, two pc boards, and the module heatsink/housing assembly.

The PA connects to the chassis backplane using a 96-pin DIN connector and three
blindmate RF connectors. Two Torx screws located on the front of the PA hold it in the
chassis.

Specifications of the transmitter circuitry, including the Exciter and PAs, are provided in
Base Radio Overview section. Figure 4-1 shows the 70W, 800 MHz PA. Figure 4-2 shows
the 60W, 900 MHz PA. Figure 4-3 shows the 40W, 1500 MHz PA.

y

40W, 800 MHz Ð TLF2020 (TTF1580); 70W, 800 MHz Ð TLN3335 (CTF1040); 60W, 900 MHz Ð CLN1355 (CLF1300); 40W, 1500 MHz

Ð TLN3426 (TLN3426); 800 MHz QUAD Ð CLF1400 (CLF1400)

NOTE: 70W PA shown. 40W PA is similar.

Figure:4-1 70W, 800 MHz PA Ð TLN3335 (with cover removed)

y

40W, 800 MHz Ð TLF2020 (TTF1580); 70W, 800 MHz Ð TLN3335 (CTF1040); 60W, 900 MHz Ð CLN1355 (CLF1300); 40W, 1500 MHz
Ð TLN3426 (TLN3426); 800 MHz QUAD Ð CLF1400 (CLF1400)

Figure:4-2 60W, 900 MHz PA Ð CLN1355 (with cover removed)

y

40W, 800 MHz Ð TLF2020 (TTF1580); 70W, 800 MHz Ð TLN3335 (CTF1040); 60W, 900 MHz Ð CLN1355 (CLF1300); 40W, 1500 MHz

Ð TLN3426 (TLN3426); 800 MHz QUAD Ð CLF1400 (CLF1400)

Figure:4-3 40W, 1500 PA (with cover removed)

1.5GHZ-Z858

y

40W, 800 MHz Ð TLF2020 (TTF1580); 70W, 800 MHz Ð TLN3335 (CTF1040); 60W, 900 MHz Ð CLN1355 (CLF1300); 40W, 1500 MHz
Ð TLN3426 (TLN3426); 800 MHz QUAD Ð CLF1400 (CLF1400)

Figure:4-4 QUAD Channel PA (with cover removed)

y

Theory of Operation

Table 4-3 describes the basic functions of the PA circuitry. Figures 4-5, 4-6 and 4-9 show
the functional block diagrams of 40W, 800 MHz PA; 70W, 800 MHz PA and the 800MHz,
Quad PA, respectively. Figures 4-7 shows the functional block diagram of the 60W, 900
MHz PA. Figures 4-8 shows a functional block diagram of the 40W, 1500 MHz PA.

Theory of Operation

Table 4-3

Power Amplifier Circuitry

Circuit Description

DC/Metering Board ¥ Serves as the main interface between the PA and the backplane board

¥ Accepts RF input from the Exciter via a blindmate RF connector

¥ Routes the RF input via a 50 ½ stripline to the Linear Driver Module RF

amplifier

¥ Routes the RF feedback from the RF Combiner/Peripheral Module to the

Exciter via a blindmate RF connector

¥ Provides digital alarm and metering information of the PA to the BRC via

the SPI bus

¥ Routes DC power to the fans and PA

Linear Driver Module (LDM) ¥ Contains one Class AB stage which, in turn, drives a parallel Class AB stage

¥ Amplifies the low-level RF signal ~25 mW average power from the Exciter

via the DC/Metering Board (800MHz and 900MHz)

¥ Amplifies the low-level RF signal ~8 mW average power from the Exciter

via the DC/Metering Board (1500MHz)

¥ Provides an output of:

~10 W (800MHz) average power
~8 W (800MHz Quad) average power
~17 W (900MHz) average power
~16 W (1500MHz) average power

Interconnect Board
(800 MHz only)

RF Splitter/DC board ¥ Interfaces with the DC/Metering Board to route DC power to the LFMs

¥ Provides RF interconnection from the LDM to the RF Splitter board

¥ Provides DC supply filtering

¥ Contains splitter circuits that split the RF output signal of the LDM to the

three Linear Final Modules (40W, 800MHz)

¥ Contains splitter circuits that split the RF output signal of the LDM to the

six Linear Final Modules (70W, 800MHz and 800MHz Quad)

¥ Contains a Quadrature splitter circuit to split the RF output signal of the

LDM to the two Linear Final Modules (900 MHz and 1500 MHz)

y

Theory of Operation

Table 4-3

Power Amplifier Circuitry (Continued)

Circuit Description

Linear Final Module
(LFM)

RF Interconnect Board
(40W, 800 MHz PA only)

Combiner Board
(70W, 800 MHz PA and
800MHz Quad only)

RF Combiner/Peripheral
Module

Fan Assembly ¥ Consists of three fans used to keep the PA within predetermined operating

¥ Each module contains two Class AB amplifiers in parallel. Each module

amplifies one of three RF signals (~ 8 W average power) from the LDM
(via the Splitter/DC board). Three LFMs provide a sum RF output of
approximately 48 W average power. (40W, 800MHz)

¥ Each module contains two Class AB amplifiers in parallel. Each module

amplifies one of six RF signals (~ 8 W average power) from the LDM (via
the Splitter/DC board). Six LFMs provide a sum RF output of
approximately 97 W average power. (70W, 800MHz)

¥ Each module contains two Class AB amplifiers in parallel. Each module

amplifies one of six RF signals from the LDM (via the Splitter/DC board).
Six LFMs sum to provide the final RF power. (800MHz Quad)

¥ Each module contains two Class AB amplifiers in parallel. Each module

amplifies one of two RF signals (~ 17 W average power) from the LDM
(via the Splitter/DC board). Two LFMs provide a sum RF output of
approximately 75 W average power. (900MHz)

¥ Each module contains two Class AB amplifiers in parallel. Each module

amplifies one of two RF signals (~ 16 W average power) from the LDM
(via the Splitter/DC board). Two LFMs provide a sum RF output of
approximately 28 W average power. (1500MHz)

¥ Contains three transmission lines that interconnect the LFMs to the RF

Combiner/Peripheral Module

¥ Contains three separate Quadrature combiner circuits that respectively

combine the six RF outputs from the LFMs into three signals. These three
signals, in turn, are applied to the RF Combiner/Peripheral Module.

¥ Contains a combiner circuit that combines the three RF signals from the RF

Interconnect Board (40W PA) or the Combiner Board (70W PA and Quad
PA). It routes the combined RF signal through a circulator and a Low Pass
Filter. The final output signal is routed to the blindmate RF connector (800
MHz)

¥ Contains a Quadrature combiner circuit to combine the RF signal from the

two LFMs. It routes the combined RF signal through a circulator and a Low
Pass Filter. The output signal is routed to the blindmate RF connector (900
MHz and 1500 MHz)

¥ Contains an RF coupler that provides an RF feedback signal to the Exciter

via a blindmate RF connector. Also contains a forward and reverse power
detector for alarm and power monitoring purposes

temperatures

DC/Metering Board(Non-Quad)

The DC/Metering Board provides the interface between the PA and the Base Radio
backplane. The preamplified/modulated RF signal is input directly from the Exciter via
the Base Radio backplane.

The RF input signal is applied to the input of the Linear Driver Module (LDM). The RF
feedback signal is fed back to the Exciter, where it is monitored for errors.

The primary function of the DC/Metering Boards is to monitor proper operation of the PA.
This information is forwarded to the Base Radio Controller (BRC) via the SPI bus. The
alarms diagnostic points monitored by the BRC on the PA include the following:

¥

Forward power

y

¥

Reflected power

¥

PA temperature sense

DC/Metering Board (Quad only)

The DC/Metering Board in the Quad Radio serves the same function as does other radios.
However, its circuitry is modified to be compatible with the Quad Station. As such, the
logic circuitry is 3.3V.

In addition to the functions listed in the non-Quad version, the following metering points
are ported to the SPI bus:

¥

A and B Currents

¥

Fan Sensor

Linear Driver Module

Theory of Operation

800 MHz

The Linear Driver Module (LDM) amplifies the low-level RF signal from the Exciter.
The LDM consists of a two-stage cascaded amplifier.

The RF input signal applied to the LDM has an average power level of approximately 25
mW. The LDM amplifies this signal to an average output level of approximately 10 Watts.
(8W in Quad) The LDM output is fed to the RF Splitter/DC Distribution Board via an
Interconnect Board.

900 MHz

The Linear Driver Module (LDM) amplifies the low-level RF signal from the Exciter.
The LDM consists of a three-stage cascaded amplifier. This output is fed directly to the
RF Splitter/DC Distribution Board.

The RF input signal applied to the LDM has an average power level of approximately 25
mW. The LDM amplifies this signal to an average output level of approximately 17 Watts.

1500 MHz

The Linear Driver Module (LDM) takes the low level RF signal and amplifies it. The
LDM consists of a four stage cascaded amplifier. The RF input signal has an average
power level of 8 mW. The LDM amplifies the input signal to an average output level of
approximately 16 Watts. This output is fed directly to the RF Splitter/DC Distribution
Board.

The current drain of the Power Amplifiers is monitored by the A/D converter on the DC/
Metering board. A voltage signal representative of the LDM current drain is sent to the
BRC. A Power Amplifier alarm is generated if the signal is outside of either the upper or
lower limits.

y

Theory of Operation

Interconnect Board (800 MHz and 800MHz Quad only)

The output of the LDM is applied to the Interconnect Board, which provides an RF
connection to the RF Splitter/DC Distribution Board. As a separate function, area on the
Interconnect Board serves as a convenient mounting location for electrolytic capacitors
used for filtering the +28 VDC supply.

RF Splitter/DC Distribution Board

800 MHz

The RF Splitter portion of this board accepts the amplified signal from the LDM (via the
Interconnect Board). The primary function of this circuit is to split the RF signal into
drive signals for the LFMs.

In the 40W PA, this circuit splits the drive signal into three separate paths to be applied to
the three LFMs, where the signals will be amplified further. In the 70W PA and Quad PA,
this circuit splits the drive signal into six separate paths to be applied to the six LFMs,
where the signals will be amplified further.

The DC Distribution portion of this board interfaces directly with the DC/Metering Board
to route DC power to the LFMs.

Linear Final Modules

900 MHz and 1500 MHz

The RF Splitter portion of this board accepts the amplified signal from the LDM. The
primary function of this circuit is to split the RF signal into two separate paths. These two
outputs are fed directly to two separate Linear Final modules where the RF signals will be
amplified further.

The DC Distribution portion of this board interfaces directly with the DC/Metering Board
to route DC power to the LFMs.

800 MHz

The RF Splitter output signals are applied directly into the LFMs for final amplification.
Each LFM contains parallel PAs that amplify the RF signals.

In the 40W PA, the parallel LFMs amplify the input signals to a sum output level of
approximately 48 Watts average power. The amplified signal is then sent directly to the
RF Interconnect Board. In the 70W PA, the parallel LFMs amplify the input signals to a
sum output level of approximately 97 Watts average power. In the Quad PA, the function
is similar to the 70W PA. The amplified signal is then sent directly to the Combiner Board.

900 MHz

The RF signals from the outputs of the RF Splitter are applied directly into the Linear
Final Module (LFM) for final amplification. Each LFM contains dual PAs that amplify
the RF signals to a combined output level of approximately 75 Watts average power. The
amplified signal is then sent directly to the RF Combiner circuit for final distribution.

y

1500 MHz

The two RF signals from the outputs of the RF Splitter are input directly into the Linear
Final Module (LFM) for final amplification. Each LFM contains dual power amplifiers
that amplify the RF signals to an output equal to approximately 28 Watts average power.
The amplified signal is then sent directly to the RF Combiner circuit for final distribution.

The current drain of the Power Amplifiers is monitored by the A/D converter on the DC/
Metering board. A voltage signal representative of the LFM current drain is sent to the
BRC. A Power Amplifier alarm is generated if the signal is outside of either the upper or
lower limits.

RF Interconnect Board (40W, 800 MHz PA Only)

The RF Interconnect Board consists of transmission line paths which route the three
output signals from the LFMs to the three inputs of the RF Combiner/Peripheral Module.

Combiner Board (70W, 800 MHz PA and 800MHz Quad
PA Only)

The Combiner Board combines pairs of signals into single signals, thereby combining the
six signals from the LDMs into three signals. The resulting three signals are applied to the
RF Combiner/Peripheral Module.

Theory of Operation

RF Combiner/Peripheral Module

800 MHz and 800MHz Quad

This module consists of two portions: an RF combiner and a peripheral module. The RF
Combiner portion of the module combines the three RF signals from the RF Interconnect
Board (40W PA) or the Combiner Board (70W PA) into a single signal using a Wilkinson
coupler arrangement.

Following the combiner circuit, the single combined RF signal is then passed through a
directional coupler which derives a signal sample of the LFM RF power output. Via the
coupler, a sample of the RF output signal is fed to the Exciter as a feedback signal.
Following the coupler, the power output signal is passed through a circulator, which
protects the PA in the event of high reflected power.

The peripheral portion of the module provides a power monitor circuit that monitors the
forward and reflected power of the output signal. This circuit furnishes the A/D converter
on the DC/Metering Board with input signals representative of the forward and reflected
power levels.

For forward power, a signal representative of the measured value is sent to the BRC via
the SPI bus. The BRC determines if this level is within tolerance of the programmed
forward power level. If the level is not within parameters, the BRC will issue a warning to
the site controller which, in turn, will shut down the Exciter if required.

Reflected power is monitored in the same manner. The BRC uses the reflected power to
calculate the voltage standing wave ratio (VSWR). If the VSWR is determined to be
excessive, the forward power is rolled back. . If it is extremely excessive, the BRC issues
a shut-down command to the Exciter.

y

Theory of Operation

A thermistor is located on the RF Combiner/Peripheral module to monitor the operating
temperature of the PA. The thermistor signal indicating excessive temperature is applied
to the A/D converter and then sent to the BRC. The BRC rolls back forward power if the
monitored temperature is excessive.

900 MHz

The combined LFM output is applied to this module. The RF signal is first passed through
a directional coupler which derives a signal sample of the LFM RF power output. Via the
coupler, a sample of the RF output signal is fed to the Exciter as a feedback signal, thereby
allowing the Exciter to accordingly adjust signal drive. Following the coupler, the power
output signal is passed through a circulator, which protects the PA in the event of high
reflected power.

A power monitor circuit monitors the forward and reflected power of the output signal.
This circuit furnishes the A/D converter on the DC/Metering Board with input signals
representative of the forward and reflected power levels.

For forward power, a signal representative of the measured value is sent to the BRC via
the SPI bus. The BRC determines if this level is within tolerance of the programmed
forward power level. If the level is not within parameters, the BRC will issue a warning to
the site controller which, in turn, will shut down the Exciter if required.

Reflected power is monitored in the same manner. The BRC uses the reflected power to
calculate the voltage standing wave ratio (VSWR). If the VSWR is determined to be
excessive, the forward power is rolled back. If it is extremely excessive, the BRC issues a
shut-down command to the Exciter.

A thermistor is located on the RF Combiner/Peripheral module to monitor the operating
temperature of the PA. A voltage representative of the monitored temperature is sent from
the A/D converter to the BRC. The BRC rolls back forward power if the monitored
temperature is excessive.

1500 MHz

Both LFM outputs are input into this module where they are combined for a single output
signal. The RF signal is first coupled to the Exciter module so that it can be monitored.
The RF output signal is then passed through a circulator that acts as a protection device for
the PA in the event of reflected power.

A power monitor circuit monitors the forward and reflected power of the output signal.
This circuit provides the A/D converter on the DC/Metering board with an input signal
representative of the forward or reflected power levels.

For forward power, a signal representative of the measured value is sent to the BRC
module via the SPI bus. The BRC determines if this level is within tolerance of the
programmed forward power level. The programmed forward power is set through the use
of MMI commands. If the level is not within certain parameters, the BRC will issue a
warning to the site controller and may shut-down the Exciter module.

Reflected power is monitored in the same manner except that the BRC determines an
acceptable reflected power level. The BRC calculates the reflected power through an
algorithm stored in memory. If the reflected power is determined to be excessive, the
forward power is rolled back. If the reflected power level is extremely excessive, the BRC
will issues a shut-down command to the Exciter module.

y

Fan Module

Theory of Operation

A thermistor is located on the RF Combiner/Peripheral module to monitor the operating
temperature of the Power Amplifier. A voltage representative of the monitored
temperature is sent from the A/D converter to the BRC. The BRC issues a cut-back
command to the Exciter module if the monitored temperature is greater than 121û F (85û
C).

The PA contains a fan assembly to maintain normal operating temperature through the use
of a cool air intake. The fan assembly consists of three individual fans in which airflow is
directed across the PA heatsink.

The current draw of the fans is monitored by the DC/Metering Board. A voltage
representative of the current draw is monitored by the BRC. The BRC flags the iSC if an
alarm is triggered. The PA LED on the front panel of the BRC also lights, however the PA
does not shut down.

y

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Left Blank

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

Power Amplifier

4

40W, 800 MHz Power Amplifier – TLF2020 (TTF1580)

Functional Block Diagram

RF INPUT

SPI BUS

TO/FROM BRC

ADDRESS BUS

FROM BRC

RF OUT

TO ANTENNA

ADDRESS DECODE, MEMORY,

& A/D CONVERTER CIRCUITRY

CLK/DATA

MEMORY

CHIP SELECT

DECODE

CIRCUITRY

BOARD SELECT

DECODE

CIRCUITRY

CHIP SELECT

CHIP

SELECT

A/D

CONVERTER

LINEAR DRIVER MODULE

STAGE

1

CLASS AB

FAN SENSE
PA TEMP SENSE
FWD PWR
REF PWR

LOW-PASS

FILTER

STAGE 2

CLASS AB

50 OHM

LOAD

INTERCONNECT

+28 VDC

FAN ASSEMBLY

TEMPERATURE

SENSOR

BOARD

DC

FILTER

RF COMBINER/

PERIPHERAL MODULE

RF SPLITTER/DC DISTRIBUTION BOARD

50 OHM

LOAD

50 OHM

LOAD

LINEAR FINAL

MODULES

RF

INTERCONNECT

BOARD

68P81095E02-D 4/1/2000

RF FEEDBACK

TO EXCITER

MODULE

CIRCULATOR

50 OHM

LOAD

50 OHM

LOAD

Figure:4-5

STAGE 3

CLASS AB

EBTS611
051398LLN

TLF2020 (TTF1580B) 40 W, 800 MHz Power Amplifier
Functional Block Diagram (Sheet 1 of 1)

4-15

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

Power Amplifier

70W, 800 MHz Power Amplifier – TLN3335 (CTF1040)

Functional Block Diagram

RF INPUT

SPI BUS

TO/FROM BRC

ADDRESS BUS

FROM BRC

ADDRESS DECODE, MEMORY,

& A/D CONVERTER CIRCUITRY

CLK/DAT A

MEMORY

CHIP SELECT

DECODE

CIRCUITRY

BOARD SELECT

DECODE

CIRCUITRY

CHIP SELECT

CHIP

SELECT

A/D

CONVERTER

LINEAR DRIVER MODULE

STAGE

1

CLASS AB

FAN SENSE
PA TEMP SENSE
FWD PWR
REF PWR

STAGE 2

CLASS AB

INTERCONNECT

BOARD

DC

FILTER

+28 VDC

FAN ASSEMBLY

RF SPLITTER/DC DISTRIBUTION BOARD

50 OHM

LOAD

50 OHM

LOAD

LOAD

LOAD

50 OHM

50 OHM

LINEAR FINAL

MODULES

COMBINER

BOARD

50 OHM

LOAD

50 OHM

LOAD

50 OHM

LOAD

TO ANTENNA

RF FEEDBACK

TO EXCITER

MODULE

4-16

RF OUT

Figure:4-6

50 OHM

LOW-PASS

FILTER

LOAD

CIRCULATOR

TLN3335 (CTF1040) 70 W, 800 MHz Power Amplifier
Functional Block Diagram (Sheet 1 of 1)

TEMPERATURE

SENSOR

RF COMBINER/

PERIPHERAL MODULE

50 OHM

LOAD

50 OHM

LOAD

LOAD

50 OHM

STAGE 3

CLASS AB

EBTS417
120497JNM

68P81095E02-D 4/1/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

Power Amplifier

60W, 900 MHz Power Amplifier – CLN1355 (CLF1300)

Functional Block Diagram

RF INPUT

SPI BUS

TO/FROM BRC

ADDRESS BUS

FROM BRC

ADDRESS DECODE, MEMORY,

& A/D CONVERTER CIRCUITRY

CLK/DAT A

MEMORY

CHIP SELECT

DECODE

CIRCUITRY

BOARD SELECT

DECODE

CIRCUITRY

CHIP SELECT

CHIP

SELECT

A/D

CONVERTER

LINEAR DRIVER MODULE RF SPLITTER/

DC DISTRIBUTION BOARD

STAGE

1

CLASS A CLASS AB CLASS AB

STAGE

2

STAGE

3

LOAD

50 OHM

FAN ASSEMBLY

FAN SENSE
PA TEMP SENSE
FWD PWR
REF PWR

LINEAR FINAL MODULE

50 OHM

LOAD

LINEAR FINAL MODULE

LOAD

LOAD

50 OHM

50 OHM

68P81095E02-D 4/1/2000

RF OUT

TO ANTENNA

RF FEEDBACK

TO EXCITER

MODULE

LOW-PASS

FILTER

50 OHM

LOAD

CIRCULATOR

TEMPERATURE

SENSOR

RF COMBINER/

PERIPHERAL MODULE

50 OHM

LOAD

Figure:4-7

50 OHM

LOAD

EBTS326
011497JNM

60W, 900 MHz Power Amplifier Functional Block Diagram
(Sheet 1 of 1)

4-17

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

Power Amplifier

40W, 1500 MHz Power Amplifier – TLN3426

Functional Block Diagram

P ower Amplifier

Functional Block Diagram
Model TLN3426

RF INPUT

SPI BUS

TO/FROM BRC

ADDRESS BUS

FROM BRC

ADDRESS DECODE, MEMORY,

& A/D CONVERTER CIRCUITRY

MEMORY

(U5004)

CHIP SELECT

DECODE

CIRCUITRY

(U5000)

BOARD SELECT

DECODE

CIRCUITRY

(U5000)

CHIP SELECT

CHIP

SELECT

A/D

CONVERTER

(U5100)

LINEAR DRIVER MODULE
TLG4020

STAGE

1

CLASS A CLASS AB CLASS AB CLASS AB

LDM/LFM CURRENT SENSE
FAN SENSE
PA TEMP SENSE

FWD PWR
REF PWR

STAGE

2

LDM CURRENT SENSE

STAGE

3

STAGE

4

FAN ASSEMBLY

LFM CURRENT SENSE

FAN FANFAN

RF SPLITTER/
DC DISTRIBUTION BOARD
TLG4023

50 OHM

LOAD

LINEAR FINAL MODULE
TLG4021

(Q5433)

(Q5433)

50 OHM

LOAD

LINEAR FINAL MODULE
TLG4021

(Q5417)

LOAD

50 OHM

4-18

Figure:4-8

RF OUT

TO ANTENNA

RF FEEDBACK

TO EXCITER

MODULE

Power
Amplifier

LOW-PASS

FILTER

CIRCULATOR

TEMPERATURE

SENSOR
(RT5401)

50 OHM

LOAD

PERIPHERAL MODULE

RF COMBINER/

TLG4022

50 OHM

LOAD

LOAD

50 OHM

(Q5417)

LOAD

50 OHM

68P81095E02-D 4/1/2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

Power Amplifier

4

800 MHz QUAD Carrier Power Amplifier

Functional Block Diagram

RF INPUT

SPI BUS

TO/FROM BRC

ADDRESS BUS

FROM BRC

ADDRESS DECODE, MEMORY,

& A/D CONVERTER CIRCUITRY

CLK/DAT A

MEMORY

CHIP SELECT

DECODE

CIRCUITRY

BOARD SELECT

DECODE

CIRCUITRY

CHIP SELECT

CHIP

SELECT

A/D

CONVERTER

LINEAR DRIVER MODULE

STAGE

1

CLASS AB

FAN SENSE
PA TEMP SENSE
FWD PWR
REF PWR

STAGE 2

CLASS AB

INTERCONNECT

BOARD

DC

FILTER

+28 VDC

FAN ASSEMBLY

RF SPLITTER/DC DISTRIBUTION BOARD

50 OHM

LOAD

50 OHM

LOAD

LOAD

LOAD

50 OHM

50 OHM

LINEAR FINAL

MODULES

COMBINER

BOARD

50 OHM

LOAD

50 OHM

LOAD

50 OHM

LOAD

RF OUT

TO ANTENNA

RF FEEDBACK

TO EXCITER

MODULE

68P81095E02-D 11/9//2000

Figure:4-9

50 OHM

LOW-PASS

FILTER

LOAD

CIRCULATOR

DUAL Stage Isolator

QUAD Channel Power Amplifier Functional Block
Diagram (Sheet 1 of 1)

TEMPERATURE

SENSOR

RF COMBINER/

PERIPHERAL MODULE

50 OHM

LOAD

50 OHM

LOAD

LOAD

50 OHM

STAGE 3

CLASS AB

EBTS417
120497JNM

4-19

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

Power Amplifier

This Page Intentionally

Left Blank

4-20

68P81095E02-D 11/9//2000

EBTS System Manual - Vol 2 800/900/1500 MHz Base Radios

5 DC Power Supply

Overview

This section provides technical information for the DC Power Supply (PS). Table
5-1 describes covered topics.

Table 5-1

Chapter

DC Power Supply for Single Channel Base Radios 5-22 Describes the functions and characteristics of the DC Power

Single Channel DC Power Supply 5-29 Describes the functions and characteristics of the DC Power

Single Channel DC Power Supply 5-30 Functional Block Diagram for the Single Channel DC Power

QUAD Channel Power Supply 5-31 Functional Block Diagram for the QUAD Channel DC Power

Chapter T opics

Page Description

Supply (PS) module for the single channel Base Radio (BR).

Supply (PS) module for the QUAD channel Base Radio (BR).

Supply (PS)

Supply (PS)

FRU Number to Kit Number Cross Reference

DC Power Supply Field Replaceable Units (FRUs) are available for the iDEN
EBTS. The FRU contains the Power Supply kit and required packaging. Table 5-2
provides a cross reference between Exciter FRU numbers and kit numbers.

Table 5-2

Description

Single Channel DC Power Supply TLN3338 CPN1027

QUAD Channel DC Power Supply CLN1498 CLF1550

FRU Number to Kit Number Cross Referece

FRU Number Kit Number

68P81095E02-D 11/9/2000

5-21

800/900/1500 MHz Base Radios EBTS System Manual - Vol 2

DC Power Supply for Single Channel Base Radios

DC Power Supply for Single Channel
Base Radios

DC Power Supply Overview

The DC Power Supply provides DC operating voltages to QUAD Channel Base
Radio FRUs. The power supply accepts input voltage sources from 41Vdc to
60Vdc. Input sources may be either positively or negatively grounded.

On initial startup, the supply requires a nominal 43 Vdc. If the voltage drops
below 41 V, the DC Power Supply enters quiescent mode. In quiescent mode, the
power supply outputs no power.

The DC Power Supply is designed for sites with an available DC voltage source.
Output voltages from the DC Power Supply are 28.6 Vdc, 14.2 Vdc and 5.1 Vdc,
with reference to output ground. The supply is rated for 575 Watts of continuous
output power, with up to 113û F (45û C) inlet air. At 140û F (60û C), the 28.6 Vdc
output reduces to 80% of maximum power.

The DC Power Supply consists of the Power Supply and front panel hardware.
The DC Power Supply connects to the chassis backplane through an edgecard
connector. Two Torx screws on the front panel secure the DC power supply to the
chassis.

Figure 5-1 shows the DC Power Supply with the cover removed.

Controls and Indicators

Table 5-3 summarizes LED indications on the DC Power Supply during normal
operation. The ON/OFF switch behind the front panel turns DC power supply on
and off.

Table 5-3

DC Power Supply Indicators

LED

Green Solid (on) Power Supply is on, and operating under normal conditions with

Red Solid (on) Power Supply fault or load fault on any output, or input voltage is

Condition Indications

no alarms

Off Power Supply is turned off or required power is not available

out of range

Off Power Supply is operating normally, with no alarms

Performance Specifications

Table 5-4 lists the speciÞcations for the DC Power Supply.

5-22

68P81095E02-D 4/16/99